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Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, self-heating (SH), electromigration (EM), and various integration challenges. Even though single-level scaled graphene wires have been shown to possess better performance and reliability with respect to dual-damascene (DD) and SE-enabled metal wires, a multi-level graphene interconnect technology (with vias) has remained elusive, which is of paramount importance for its integration in future technology nodes. This work, for the first time, addresses that need by engineering a CMOS-compatible solid-phase growth technique to yield large-area multilayer graphene (MLG) on dielectric (SiO2) and metal (Cu) substrates and subsequently demonstrating multi-level MLG interconnects with metal vias. Using rigorous theoretical and experimental analyses, we demonstrate that multi-level MLG interconnects with metal vias undergo < 2% change in the via resistance under accelerated stress conditions, demonstrating its superior reliability against SH and EM, making them ideal candidates for sub-10 nm nodes.

The influence of SiO2 and SiNx capping layer on threshold voltage (${V}_{t}$) for FinFET with TiAl-based metal gate (MG) is studied. After metal gate-stack formation, SiNx capping is revealed to be able to serve as a new N source, resulting in the diffusion of N into the effective work function (EWF) TiNx layer. Correspondingly, the accumulation of N in the TiNx layer is demonstrated to be able to lower the EWF for both n- and p-FinFETs. Compared to SiO2 capping, SiNx capping can induce $\sim 100$ –150 mV ${V}_{t}$ lowering for short n- and p-FinFETs. No obvious ${V}_{t}$ shift is found for long-channel devices. [ABSTRACT FROM AUTHOR]

Carbon dot (CD) is a new kind of color-converting material for light-emitting diodes (LEDs) because of its good luminesce performance and low toxicity; however, the CD is built by a covalent bond and contains a lot of organic functional group and thus it is a kind of organic material and needs to be protected from oxygen and H2O in the air. Thin-film encapsulation (TFE) is introduced to LED encapsulation, and SiO2 nanoparticles are mixed with organic silica resin to replace the traditional LED encapsulation glue. The stability of devices encapsulated with the SiN film and hybrid organic silica resin (H-S resin) are tested at 95% relative humidity (RH) and 25 °C, and the residual photoluminescence (PL) intensity has increased by more than 30% after encapsulation. The stacked encapsulation with both the SiN film and H-S resin can keep residual PL intensity up to 98% after ten days at 95%RH and 25 °C. The temperature rise of the device has almost no change under a low working current and raise 8 °C under a high working current. This encapsulation structure is also available for micro-LED encapsulation. [ABSTRACT FROM AUTHOR]

We studied nitrogen (N) incorporation effects on the electrical characteristics of SiO2 fabricated by plasma-enhanced atomic layer deposition (PEALD). To determine whether N could be incorporated into the SiO2, nitrous oxide (N2O) plasma with different plasma powers (100, 150, and 200 W) was used during the SiO2 deposition, and the film properties were compared with SiO2 fabricated using a conventional oxygen (O2) plasma reactant. Compared to the O2 plasma reactant, the hard breakdown is improved by 27.5% as N2O plasma power increases up to 150 W, whereas it is degraded at a N2O plasma power of 200 W. These results are found to describe the relationship between the N content and film properties. The N content in the SiO2 films fabricated using increasing N2O plasma power of 100, 150, and 200 W gradually increased by 0.2%, 0.4%, and 0.5%, respectively. However, the N2O plasma power of 200 W results in increased O deficient Si bonding. To investigate the effects of continuous plasma exposure at the bottom layer during the SiO2 deposition, we fabricated indium–zinc oxide (IZO) top-gate bottom-contact (TG-BC) thin-film transistors (TFTs) using the SiO2 as a gate insulator (G.I). Compared to the O2 plasma, the IZO TFTs using N2O plasma reactant during the G.I deposition show stable transfer characteristics. The IZO TFT using N2O plasma with 150-W power during the G.I deposition shows the optimal positive/negative bias temperature stress (P/NBTS) results, with the threshold voltage ($V_{\mathbf {TH}}$) variations of 0.0 and −0.3 V, respectively. [ABSTRACT FROM AUTHOR]

This article presents a 96 $\mu \text{m}\,\,\times $ 106 $\mu \text{m}$ sized single-crystalline silicon (SC-Si) /Au thermopile infrared (IR) detector, with the thermopile and IR absorber located at different layers of a double-deck micromechanical structure for improving detectivity. In order to enhance IR-heat absorption within such a tiny device size, an umbrella-shaped SiN IR absorbing membrane instead of traditional plane IR-absorbing film occupies the whole area of the top layer structure. The umbrella-shaped IR absorber is suspended on top of the IR-detecting thermopile layer, with a central umbrella-stick to support the suspending and conducting the absorbed IR-heat to the bottom thermopile layer. The bottom thermopile layer consists of six pairs of spiral-shaped SC-Si/Au thermocouples that feature several times higher Seebeck coefficient compared to the traditional polysilicon/metal thermocouples. By combining surface-micromachining technique with a specific bulk-micromachining process performed in (111) silicon wafer, the double-deck structured IR-detector is successfully fabricated only from the front side of a single (111) silicon wafer for IC-foundry compatible low-cost manufacturing. Testing results show that this device of about 100- $\mu \text{m}$ scale achieves an ultrahigh IR detectivity of 1.01 $\times \,\,10^{{8}}$ cm $\cdot $ Hz $^{{{1}/{2}}}\cdot \text{W}^{-{1}}$ , which is two times improvement compared to the recently reported thermopile IR detectors, though the counterparts had larger device area. Featuring tiny size and batch fabrication capability, the proposed high-performance IR-detector is promising in both single-point detection and multipixel arrayed temperature imaging applications. [ABSTRACT FROM AUTHOR]

The underlying mechanism responsible for the unique dynamic ON-resistance behavior is unified by demonstrating the presence of critical drain stress voltage, above which dynamic ON-resistance increases significantly, in different gate stacks. Metal–insulator–semiconductor (MIS)- and Schottky-gated HEMTs show similar dependence of critical voltage on various parameters, which establishes that gate-stack design has negligible impact on the observed phenomena. Furthermore, using the physical insights developed, this work proposes a novel surface passivation scheme to improve the dynamic performance of the device. The proposed surface passivation scheme uses p-type Al0.5Ti0.5O (AlTiO), which is deposited over SiNx passivation (or GaN cap), and is shown to be an effective tool in improving the dynamic ON-resistance of the device by modulating the electric field in the GaN buffer. The proposed passivation scheme has avoided the critical voltage to appear for the entire drain stress voltage, stress time, and substrate bias range. Detailed computational analysis in conjunction with electroluminescence (EL) and photoluminescence (PL) studies revealed an electric field redistribution due to the p-type nature of AlTiO deposited over the surface passivation/capping layer, which is responsible for relaxed electric field profile in GaN buffer and observed improvement in dynamic performance. Besides, the new observations have further helped to understand the interplay between surface conditions and GaN buffer, defining its collective role in governing the dynamic performance of GaN HEMTs. Finally, various findings and the proposal in this work have been validated for buffers having higher carbon doping and devices with p-type AlTiO deposited over GaN cap instead of in situ SiNx cap. [ABSTRACT FROM AUTHOR]

In recent days, more hardware-driven artificial intelligence system capable of brain-like low-energy consumption is gaining ever-increasing interest. The hardware-driven property lies in the low-power synaptic device and its array along with the area and energy-efficient neuron circuits. In this work, a spiking neural network (SNN) based on analog synaptic device of resistive-switching random access memory (RRAM) is constructed from the experimentally fabricated devices. Furthermore, the capability of the designed SNN hardware for sequential tasks through an optimal reinforcement learning (RL) algorithm is demonstrated. More specifically, the Rush Hour game is conducted as an example of applications for the sequential task for which an SNN architecture is plausibly suited. The rule of the game is simple but has not been demonstrated by a hardware-oriented artificial neural network (ANN) yet, and in this work, it is reported that the analog RRAM synaptic devices in the cross-point array architecture successfully solve the problem via the RL algorithm. [ABSTRACT FROM AUTHOR]

The gate and drain bias dependence of hot electron-induced degradation in GaN-based metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) was investigated in this work. Devices exhibit an abnormal increase in peak transconductance (${G}_{m}$ ,max) during hot carrier stress (HCS) and a partially quick recovery of that after removing the electrical stress. A physical model is proposed to explain the abnormal electrical characteristics caused by HCS. By using density functional theory (DFT), we calculated the energy for electrons to dehydrogenate preexisting [NGaH3]−1 complexes in GaN layer during stress. The dehydrogenation of defects affects the Gm,max of devices. Meanwhile, the neutralization of donor traps in AlGaN barrier layer also plays a significant role in the increase of Gm,max and the detrapping effect of electrons from these traps after removing the electrical stress accounts for the partially quick recovery of ${G}_{m, \text{max}}$. [ABSTRACT FROM AUTHOR]

Rapid-thermal-chemical-vapor-deposition (RT-CVD) SiNx gate dielectric was utilized for the fabrication of enhancement-mode GaN-based metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) on ultrathin-barrier AlGaN/GaN heterostructure. A plasma-enhanced-atomic-layer-deposited (PEALD) SiNx interfacial layer was adopted to mitigate the high-temperature RTCVD process-induced degradation of the dielectric/III-nitride interface. Based on the dc- and pulsed transfer measurement results, the device with the PEALD-SiNx interfacial layer exhibits low ${V}_{\text {TH}}$ -hysteresis (0.1 V at ${V}_{\text {GS}} = 1, 10$ V) and low interface trap density. Constant-capacitance deep-level transient spectroscopy and high-resolution transmission electron microscopy were also conducted to confirm the improvement of the interface quality. [ABSTRACT FROM AUTHOR]

ScAlN/GaN dielectric superjunction high-electron-mobility transistors (HEMTs) with high-k passivation layer Bi1.5Zn1.0Nb1.5O7 (BZN) are demonstrated for enhancement of breakdown voltage. The BZN thin film deposited by RF magnetron sputtering has a dielectric constant of 192 after postdeposition annealing at 400 °C for 10 min. The HEMT with Lg = 200 nm and Lsd = 2.0 μ m has a maximum current density of 1.98 A/mm, a maximum transconductance of 0.52 S/mm, and a threshold voltage of Vth = −3 V. With the use of SiN/BZN/SiN sandwiched passivation layer, the average value of breakdown voltage is improved from 68.9 to 121.5 V, due to the reduction of the peak electrical field between the gate and the drain. The device has a cutoff frequency (ƒT) and maximum oscillation frequency (ƒmax) of 59 and 69 GHz, respectively. Overall, the devices exhibit a significantly higher breakdown voltage with essentially the same ƒT and ƒmax values. Pulse measurements suggest that SiN/BZN/SiN has a similar passivation effect in comparison with devices passivated by a SiN-only layer. This work demonstrates that high current and high breakdown voltage can be achieved simultaneously on semiconductor heterostructures with a high sheet charge density by integration of high-k dielectrics. [ABSTRACT FROM AUTHOR]

In this article, we report on the effective transconductance (gm) and gain linearity improvement of submicrometer gate AlN-barrier-based transistors using GaN/InGaN coupling-channel structures. The fabricated AlN/GaN/InGaN coupling-channel high electron mobility transistor (CC-HEMT) showed flat gm profile, greatly reduced gm derivatives, and constant dynamic source resistance compared with an AlN/GaN HEMT using the same fabrication process. The highest extrinsic current gain cutoff frequency (ƒT) of 55 GHz and the maximum oscillation frequency (ƒmax) of 80 GHz were obtained for 0.15- μm gate-length transistors, both of which remain constant values across wide input voltage (VGS) of 4 V. Moreover, a significant theoretical OIP3 value boost by 7.1 dB has been observed using the CC-HEMT as compared to the AlN/GaN HEMT. The superior linearity performance of the CC-HEMT can be attributed to the strong channel-to-channel coupling effect. The drain bias-dependence of gm, ƒT, and ƒmax versus VGS profiles illustrate that the linearity characteristics of the CC-HEMT greatly improve with an increase in VDS. These results demonstrate the AlN/GaN/InGaN material system as a viable platform for high frequency requiring high-linearity applications. [ABSTRACT FROM AUTHOR]

The hydrogen behavior in the amorphous In–Ga–Zn–O (a-IGZO) thin-film layer according to the device process with top gate structure was quantitatively investigated. The hydrogen quantities in the a-IGZO thin-film layer with gate insulator (w/GI) and after GI dry-etching were increased by 3.40 × 1020 and 2.50 × 10Da20/cm3, respectively, in comparison with without GI (w/o GI). In addition, the calculated carrier concentration of the a-IGZO thin-film layer by band alignment increased by 1.60 × 1018 and 7.38 × 1017/cm3, respectively, compared with w/o GI. Due to the plasma effect, the hydrogen quantity and the calculated carrier concentration in the a-IGZO thin-film layer after GI dry-etching slightly decreased from w/GI by 0.90 × 1020 and 8.62 × 1017/cm3, respectively. The increased hydrogen quantity in the a-IGZO thin-film layer can contribute to increase in carrier concentration by providing free electrons through the hydrogen reaction with oxygen ions or transition of hydrogen state. Here, we attempted to correlate the hydrogen effect to the increase of the carrier concentration through various physical analysis. [ABSTRACT FROM AUTHOR]

In this brief, the contact etch stop layer (CESL) stressor is introduced to improve the performance of n-type lateral double-diffused MOSFET (nLDMOSFET) with various operating voltages. Three groups of nLDMOSFETs were studied to demonstrate the effects of the CESL stressor. The electrical properties were carefully characterized, and the tip-enhanced Raman spectroscopy measurements were carried out to examine the process-induced strain directly. It is found that nLDMOSFETs with the strained SiN CESL have larger output current, transconductance (gm), and higher breakdown voltage (BV). The strained SiN CESL introduces tensile strain in the device and results in the performance boosts, which are verified by negative Raman peak shift mappings and TCAD simulations. The strained SiN CESL could effectively decrease the specific ON-resistance (Ron) and improve the BV of the nLDMOSFET, due to the mobility enhancement. [ABSTRACT FROM AUTHOR]

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured ~120~Ω/μm for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR. [ABSTRACT FROM AUTHOR]

This article reports a systematic study focused on the mechanical stress effect of field-plate dielectric film on the electric characteristics of AlGaN/GaN high-electron mobility transistors (HEMTs). AlGaN/GaN HEMTs were fabricated on SiC substrates, where the stress of a SiN field-plate dielectric film ranged from −252 (compressive) to +26.5 (tensile) MPa. Si-rich and compressive SiN films exhibited a significant increase in the isolation leakage. On the other hand, relatively N-rich and tensile SiN films showed a significant increase in the gate leakage current of HEMTs. In addition, pulsed I – V measurements showed the suppression in the current collapse by increasing the tensile stress. Consequently, small current collapse and small gate leakage current were obtained simultaneously with good isolation, as the film stress was optimized. [ABSTRACT FROM AUTHOR]

Characteristics of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) are highly dependent on the hydrogen (H) content within the device architecture, for example in the etch-stop layer (ESL) of the elevated-metal metal-oxide (EMMO) TFTs. The serious apparent “short-channel effect (SCE)” was caused by the H diffusion from source/drain (S/D) to channel. Such SCE deterioration can be suppressed by thermal dehydrogenation at a cost of long annealing time, especially for a transistor architecture with a-IGZO S/D covered with H-rich silicon nitride (SiNx:H) and further capped with metallic H-diffusion barrier. The dehydrogenation efficiency is found to be significantly enhanced by fluorinating the a-IGZO. By optimizing the device architecture and/or the fluorination process to enhance the dehydrogenation, the SCE can be efficiently eliminated with well-maintained performance even for 2~μm-long a-IGZO TFTs. [ABSTRACT FROM AUTHOR]

This article reports on sub-10-nm quaternary barrier InAlGaN/GaN high electron mobility transistors (HEMTs) grown by metal-organic-vapor-phase-epitaxy (MOVPE) with an in situ SiN passivation layer and an ultrashort gate length of 200 nm. Two batches of HEMTs with two SiN thicknesses (tSiN) of 14 and 22 nm are studied. Low-frequency noise (LFN) measurements of the drain current have been carried out in the linear regime and showed that the in situ SiN thickness has no impact on the noise performance. SID/ID2 in the linear regime dependence over the gate overdrive shows that the channel noise is located under the gate and that the noise is not impacted by the thickness of the in situ SiN layer. [ABSTRACT FROM AUTHOR]

A nonvolatile and programmable routing switch featuring two-varistor selected complementary atom switch (2V-1CAS also known as via-switch) is evaluated. The a-Si/SiN/a-Si varistor as a selector for the atom switch shows superior nonlinear current–voltage characteristics with high selectivity of ~105, which originates from the staircase barrier height in the layers. The two control lines connected to the varistors realize multiple fan-outs of the crossbar switch without select transistors. The $50\,\,\sf \times20$ crossbar switch block is demonstrated, where the atom switch is placed at each cross point and programmed through the varistors. The developed via-switch crossbar switch is a strong candidate for achieving energy-efficient nonvolatile field-programmable gate array in the Internet-of-Things applications. [ABSTRACT FROM AUTHOR]

This paper reports a novel tiny-sized ($116\,\,\mu \text {m} \times 134\,\,\mu \text{m}$) single-crystalline silicon/aluminum infrared (IR) thermopile detector, which is micromachined only from the front side of (111) wafer for IC-foundry compatible low-cost manufacturing. The tiny-sized detector consists of six serially connected p-silicon/aluminum thermocouples that show significantly higher Seebeck coefficient and lower noise compared with the traditional poly-silicon/aluminum counterparts. With the proposed symmetric helical structure, the length of thermocouple leg length as well as the thermal resistance of the detector can be enlarged within the tiny sensing area. Specific detectivity ($D^{\ast }$) is improved by optimizing the cross-sectional area of the two thermoelectric-material layers, which is more practically effective than traditional mathematic analysis methods. The device is fabricated in a (111) wafer [instead of normal (100) wafer] by using a novel single-side micromachining technique. The testing results show that the detector achieves an ultrahigh responsivity of 342 V/W and ultrashort response time of 0.56 ms. Featuring tiny-size, low-cost, and high-performance single-point detection, many thermopile detecting units can be integrated into an IR focal-plane array (IRFPA) for high-resolution imaging. [ABSTRACT FROM AUTHOR]

This paper reports the process integration and fabrication characteristics of a vertical thin poly-Si channel (VTPC) transfer gate (TG) pixel, which is one of the candidates for future 3-D CMOS image sensor (CIS) applications. The proposed process integration can effectively suppress grain boundary formation at the interface between the photodiode and the poly-Si channel by solid phase epitaxial growth (SPEG) mechanism. Furthermore, dopant diffusion characteristics for source–drain junction formation in poly-Si substrates are investigated using secondary ion mass spectroscopy (SIMS) depth profiles under various process conditions. In addition, combining SIMS results with ${I}_{d}$ – ${V}_{g}$ curve and scanning spreading resistance microscopy measurements, we explained the discrepancy in diffusion characteristics between the bulk and the thin-film poly-Si. Finally, by using optimized SPEG conditions and adopting the proposed VTPC-TG pixel structures in a commercial 5-Mpixel CIS image sensor product, we successfully verified the improvement in image quality. [ABSTRACT FROM AUTHOR]

A high-density and a highly scalable heterogeneous multi-die integration technology is presented in this paper. Central to this approach is a dense and face-to-face integration of heterogeneous ICs enabled by fine-pitch and multi-height compressible microinterconnects (CMIs) and stitch chips, which serve as the interface through which communication between active ICs occurs. Two separate testbeds are fabricated in order to characterize the proposed integration technology: the first testbed demonstrates the concatenated assembly of chips using the stitch chips with fine-pitch CMIs (in-line pitch of $20~\mu \text{m}$), while the second testbed demonstrates the fabrication of multi-height CMIs (75-, 55-, and 30- $\mu \text{m}$ tall CMIs) on the same die. Electrical characterization, including resistance and S-parameters, and mechanical characterization of interconnects are reported as well as the assembly of the testbeds. [ABSTRACT FROM AUTHOR]

This paper presents an extensive investigation of the impact of the resistivity of the silicon substrate on the vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different substrate resistivities were submitted to combined DC characterization, step-stress experiments, and electroluminescence (EL) analysis. The results described within this paper demonstrate that: 1) the use of a highly resistive silicon substrate can increase the vertical breakdown voltage of the transistors, due to the fact that the voltage drop on the GaN buffer is mitigated by the partial depletion of the substrate (this latter causes a plateau region in the drain to substrate I–V characteristic) and 2) highly resistive substrate results in stronger trapping effects, due to the capacitance of the depleted substrate and the resulting backgating effects. The results described within this paper indicate that the choice of the resistivity of the substrate is the result of a tradeoff between high breakdown voltage (that could be in principle achieved through a highly resistive substrate) and the minimization of trapping processes (which can be hardly obtained with a resistive substrate). [ABSTRACT FROM AUTHOR]

An ultrafast (10- $\mu \text{s}$ delay) measurement technique is used to characterize the negative bias temperature instability-induced threshold voltage shift ( $\Delta {V}_{T}$ ) in replacement metal gate-based high-K metal gate Si and SiGe p-FinFETs. The dc stress-recovery $\Delta {V}_{T}$ time kinetics, voltage acceleration factor (VAF), and temperature activation energy ( ${E}_{A}$ ) are compared for different germanium percentages (Ge%) in the channel and nitrogen percentages (N%) in the gate-stack. A comprehensive physical model framework based on uncorrelated contributions from the generation of interface ( $\Delta {V}_{\mathrm {IT}}$ ) and bulk oxide ( $\Delta {V}_{\mathrm {OT}}$ ) traps and hole trapping in preexisting defects ( $\Delta {V}_{\mathrm {HT}}$ ) is used to explain the measured data. The impact of Ge% and N% on $\Delta {V}_{T}$ , VAF, ${E}_{A}$ , temperature (T) dependence of VAF, and stress bias ( ${V}_{\mathrm {GSTR}}$ ) dependence of ${E}_{A}$ are quantified. The interface trap generation component is independently verified by direct-current ${I}$ – ${V}$ (DCIV) measurements. [ABSTRACT FROM AUTHOR]

An ultrafast (10- $\mu \text{s}$ delay) measurement technique is used to characterize ac negative-bias temperature instability-induced threshold voltage shift ( $\Delta \text {V}_\text {T}$ ) in replacement metal-gate-based high-K metal gate Si and SiGe p-FinFETs. Time kinetics of stress and recovery, voltage acceleration factor, temperature activation energy ( $\text {E}_\text {A}$ ), frequency (f), and pulse duty cycle (PDC) dependence are shown for different germanium percentages (Ge%) in the channel and nitrogen percentages (N%) in the gate insulator. A comprehensive physical model framework based on uncorrelated contributions from interface ( $\Delta \text {V}_\text {IT}$ ) and bulk oxide ( $\Delta \text {V}_\text {OT}$ ) trap generation and hole trapping in preexisting defects ( $\Delta \text {V}_\text {HT}$ ) is used to explain the measured data at different stress biases ( $\text {V}_\text {GSTR}$ ), temperatures (T), f, and PDCs. Direct-current I–V measurements are used to independently verify the interface-trap generation component for ac stress. End-of-life degradation for different processes under dc and ac conditions is estimated by using the calibrated model and compared to predictions from conventional analytical methods. [ABSTRACT FROM AUTHOR]

Performances of temperature sensors based on Divanadium Pentoxide/4H polytype of silicon carbide, V2O5/4H-SiC, and Schottky diodes are analyzed. The devices with an active area of 1.96 x 10-3 cm² were characterized in a temperature range between 147.22 and 396.75 K and in a current range between 1 µA and 1 mA. Measurements reveal that at a bias current of 16 µA, the diode forward voltage shows a linear dependence on the temperature, with a sensitivity of 1.86 mV/K and a temperature error of 0.64 K. Sensors have also shown a good repeatability of sensing over more cycles of measurements in the considered temperature range. Numerical simulations are performed, and device physical parameters are obtained from the best fit with experimental data. From simulation results,we showthat the conductionmechanism of the sensor is affected by traps at the V2O5/4H-SiC interface, which have been modeled with an exponential tail. Moreover, device parameters, as epilayer doping concentration and thickness, have been varied in order to evaluate the variations on the sensor performances. [ABSTRACT FROM AUTHOR]

In this paper we investigated the gate–drain access region spacing ( L\mathrm {GD}) effect on electrical and noise performance of InAlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) using in situ SiN cap layer as gate insulator. Different L\mathrm {GD} of InAlGaN/GaN MIS-HEMTs using sub-10 nm barrier layer are studied. Low-frequency noise measurements have been carried out for the first time in order to analyze the impact of the gate–drain spacing on the electrical characteristics. The noise of the channel under the gate has been identified as the dominant channel noise source for L\mathrm {GD} < 10~\mu \text{m} . Finally, the calculated Hooge parameter ( \alpha H) is equal to 3.1\times 10^-4 . It reflects the high material quality while using sub-10 nm InAlGaN layer, which is promising for high-frequency applications. [ABSTRACT FROM AUTHOR]

In this paper, we investigate Low Pressure Chemical Vapor Deposition (LPCVD) SiN as a gate isolation material for AlGaN/gallium nitride (GaN) MIS-high electron mobility transistor power transistors. We compared the dielectric failure by forward-biased constant-current stress time-dependent dielectric breakdown measurements and statistical Weibull analysis. Several 4” AlGaN/GaN-on-Si wafers have been processed with different gate isolations and processes. Our investigation includes the dependence of the dielectric breakdown on the process flow (influence of dry etch), the thickness of the dielectric (12–20 nm), the area scaling, and the gate electrode, where we also consider the recently presented poly-silicon electrode. Additionally, we show the influence of the current density through the gate on the charge-to-breakdown characteristics as well as the influence of the temperature on the breakdown behavior. Using the poly-silicon electrode and 20 nm LPCVD SiN as gate isolation, we achieved a charge-to-breakdown of Q\text {BD, 10~\text {mA}/\text {cm}^{2}} ={3.7} ~ \text {kC}/\text {cm}^{{2}} at \text T = 130 ^\circ \text C for j = 10 ~ \text mA/\text cm^2 . A 20-years lifetime (100 ppm, \text T = 130 ^\circ \text C ) extrapolation for a scaled area of 0.2 ~ \text mm^2 ( \buildrel \wedge \over = WG = {100} ~ \text {mm} ) leads to a positive gate voltage of V\text {G} = {9.4} ~ \text V . [ABSTRACT FROM PUBLISHER]

Direct conversion crystalline silicon X-ray imagers are used for low-energy X-ray photon (4–20 keV) detection in scientific research applications such as protein crystallography. In this paper, we demonstrate a novel pixel architecture that integrates a crystalline silicon X-ray detector with a thin-film transistor amorphous silicon pixel readout circuit. We describe a simplified two-mask process to fabricate a complete imaging array and present preliminary results that show the fabricated pixel to be sensitive to 5.89-keV photons from a low activity Fe-55 gamma source. This paper presented can expedite the development of high spatial resolution, low cost, direct conversion imagers for X-ray diffraction and crystallography applications. [ABSTRACT FROM PUBLISHER]

We fabricate Si-based blocked impurity band (BIB) terahertz detectors using p-dopant through a standard silicon device fabrication technology. Comparison of photoresponse of the detectors under alternate operating mode and conventional operation mode (COM) is made. We demonstrate that the detectors can achieve high responsivity through positive bias on the active layer side, namely, alternate operating mode (AOM). The response of the detectors terminates at wavelength of 35~\mu \textm (8.57 THz) under AOM; on the contrary, the response is cutoff at 31~\mu \textm (9.68 THz) with a positive bias on the blocking layer, namely, COM. The relative responsivity at 0.6 V under AOM is 2.3 times of that under COM. By developing an energy band model, we find that the response difference under the two modes originates from the change of band offsets. The electric field in the blocking layer under AOM is much smaller than COM and most of the voltage drops in the active layer under AOM, which leads to the bigger multiplication of the photon-generated carriers than COM. By analyzing the origination of the dark current under the AOM, a method to improve the performance of BIB detectors under AOM is proposed. [ABSTRACT FROM AUTHOR]

High electric fields and temperatures in high-voltage ICs (HV-ICs) can induce charge transport phenomena in the encapsulation material leading to reliability test failures. In this paper, the resistivity of epoxy-based resins with insulating microfiller weight fraction exceeding 70% has been experimentally and theoretically investigated for the first time. Electrical conductivity has been measured at high temperature (150 °C) using both dielectric spectroscopy analysis on bulk samples and charge-spreading characterizations on a dedicated test chip with integrated charge sensors. The use of a charge sensor close to the internal HV metallization leads to results more pertinent with the active area of HV-ICs. Remarkably, both experiments show an unexpected increase and a significant variability of the electrical conductivity as the microfiller fraction is increased. The strong correlation between bulk and lateral experiments clearly indicates that those features should be attributed to the bulk material. Numerical simulations of diffusion phenomenon in mold structures with random arrangements of spherical microfillers demonstrate that the conductivity increase with filler content can be ascribed to the role of the epoxy/filler interfaces. [ABSTRACT FROM AUTHOR]

Evolution of thyristor technology and the design concepts, which brought and maintain the phase control thyristor (PCT) at the top of a power pyramid, are discussed. The state-of-the-art device concepts like electrically triggered thyristor and light triggered thyristor are described for voltage classes up to 8.5 kV and maximal on-state rated current of 6 kA. Main focus is laid on the PCTs for high-voltage direct current transmission, the enabler of power transmission beyond the 10-GW level. [ABSTRACT FROM AUTHOR]

In this paper, we present a systematic investigation of metal–organic chemical vapor deposition-grown in situ SiN as the gate dielectric and surface passivation for AlGaN/GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs). The dielectric constant and breakdown field of the in situ SiN were extracted from devices with varied gate dielectric thicknesses. Using frequency-dependent capacitance–voltage and parallel conductance methods, we obtained a low trap density of \sim 3\times 10^12 cm ^-2 eV ^-1 at the SiN/AlGaN interface. The MISHEMTs with a source–drain distance of 3~\mu \textm show a maximum drain current of 1560 mA/mm and a high on/off current ratio of 10^9 . The device threshold voltage ( V_\textsf th ) stability was assessed by means of both negative and positive gate stress measurements, as well as temperature-dependent I_\textsf D – V_\textsfG measurements. We observed a minimal V_\textsfth shift of ~0.4 V under both 3000 s gate stress of V_\textsf GS= 4 V and up to 200 °C thermal stimulation. Furthermore, combining the in situ SiN with plasma-enhanced chemical vapor deposition SiN, we developed a bilayer passivation scheme for effective suppression of current collapse. Employing the high-quality in situ SiN, we have demonstrated large-area GaN MISHEMTs on Si with a gate width of 20 mm, showing a low off-state leakage of 2~\mu \textA /mm at 600 V and a low dynamic/static ON-resistance ratio. The device results show great advantages of employing in situ SiN in D-mode GaN MISHEMTs for high-efficiency power switching applications. [ABSTRACT FROM AUTHOR]

This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs submitted to high-voltage stress. The analysis was carried out on transistors with different lengths of the drain-side gate-head ( L\mathrm {GH} ), corresponding to different levels of electric field across the SiN passivation. Based on dc measurements, 2-D simulations, and optical analysis, we demonstrate the following original results: 1) when submitted to high drain voltages (in the OFF-state), the transistors can show catastrophic failure; 2) electroluminescence microscopy indicates the presence of hot-spots on the drain-side of the gate; 2-D simulations support the hypothesis that failure occurs in correspondence of the gate-head, on the drain-side edge, where the electric field in the silicon nitride passivation has its maximum; 3) this hypothesis is confirmed by the results of transmission electron microscope failure analysis that demonstrate the generation of a leakage path between the gate metal and the channel, 4) and by the dependence of the destructive voltage on the L\mathrm {GH} value. 5) in addition, we propose and demonstrate an approach for improving the reliability of the devices, i.e., using a graded SiN passivation with increased thickness. The results described in this paper provide important information for the device optimization of Schottky-gated HEMTs. [ABSTRACT FROM AUTHOR]

In this brief, a novel double-side silicon-embedded transformer (DSSET) is proposed and demonstrated for low-frequency high-isolation compact power transfer applications. The two spiral coils of the DSSET are embedded inside the substrate from the two sides to achieve a large coil thickness and a whole-area utilization for each coil. The isolation is achieved by the two insulating layers at the coil–substrate interfaces. The 2-mm ^2 DSSET fabricated achieved a best reported coil inductance to resistance ratio of 0.36~\mu \textH/\Omega , and can work at a low frequency of 10 MHz with a reasonable efficiency of 70% and a useful isolation capability of 1050 V. Such a low operating frequency is essential to reduce the switching and rectifying losses of the system. [ABSTRACT FROM AUTHOR]

We have developed 0.1- \mu \textm gate-length InAlN/GaN high electron-mobility transistors (HEMTs) for millimeter-wave (MMW) power applications, particularly at 71–76 and 81–86 GHz bands. The impacts of depth and width of the gate recess groove on electrical performance have been analyzed and compared. Competing passivation technologies, atomic layer deposition (ALD) aluminum oxide (Al2O3) and plasma-enhanced chemical vapor deposition (PECVD) SiN, have also been assessed in terms of dc, pulsed- $IV$ , and high-frequency characteristics. It has been found that while PECVD SiN-passivated HEMTs and the monolithic microwave integrated circuits slightly underperform their ALD Al2O3-passivated counterparts, their MMW power performance can be further boosted with the gate recess due to the improved aspect ratio and scaling characteristics. When biased at a drain voltage of 10 V, a first-pass two-stage power amplifier design based on recessed PECVD SiN-passivated 0.1- \mu \textm depletion-mode devices has demonstrated an output power of 1.63 W with a 15% power-added efficiency at 86 GHz. [ABSTRACT FROM PUBLISHER]

Nanostructured silicon oxide impedance biosensors with ordered nanopores promise highly sensitive and selective label-free electrical detection of biomolecules through unique frequency-dependent sensitivity characteristics. Despite these promising experimental results, the fundamental mechanisms controlling the frequency-dependent phenomena and hence the design considerations have not been explored. In this paper, we consistently model the fluid and the solid regions of the sensors and discuss the design issues with respect to the pore dimensions for enhancing the sensitivity, selectivity, and repeatability toward detection of ultralow and moderate concentration of target biomolecules. The simulation results have been validated with experiments. The results indicate that the optimal design of nanoporous silicon oxide biosensors is different from the conventional idea of increasing the surface-to-volume ratio of such sensors. Instead, the design approach is nontrivial and the optimum pore dimensions are dependent on the target biomolecule charge, concentration, and distribution. It has been observed that a figure of merit is essential to design such sensors with improved commercial viability. [ABSTRACT FROM PUBLISHER]

The hump effects of germanium/silicon heterojunction tunnel field-effect transistors are discussed. Simulation results show that they are originated when indirect band-to-band tunneling is converted into direct one as gate voltage ( Vg ) increases. In order to suppress the hump effects, two ideas are proposed. First, the length of intrinsic-germanium channel ( L\mathrm{ Ge} ) is optimized using a novel process flow. Second, gate-to-channel coupling is improved by increasing source doping concentration ( NS ). [ABSTRACT FROM AUTHOR]

In this paper, fully recessed-gate GaN MISFETs with two different gate dielectrics, i.e., plasma-enhanced atomic layer deposition (PEALD) SiN and ALD Al2O3 gate dielectric, are used to study the origin of positive bias temperature instability (PBTI). By employing a set of dedicated stress-recovery tests, we study PBTI during the stress and relaxation. Hence, a defect band model with different distributions of defect levels inside the gate dielectric is proposed, which can excellently reproduce the experimental data and provide insightful information about the origin of PBTI in GaN MISFETs. The results indicate that the serious PBTI in the device with PEALD SiN is mainly due to a wide distribution of defect levels ( \sigma \sim 0.67 eV), centered below the conduction band of GaN ( E_{C} -0.05 eV), and can be easily accessed by the channel carriers already at a low-gate voltage. On the other hand, ALD Al2O3 gate dielectric shows a narrower distribution of defects ( \sigma \sim 0.42$ eV), which are far from the conduction band of GaN ( E_{C} +1.15 eV). This observations explain the improved PBTI reliability observed in devices with ALD Al2O3. [ABSTRACT FROM AUTHOR]

We investigated the SiN/gallium nitride (GaN) interface properties formed by the microwave-excited plasma-enhanced chemical vapor deposition (PECVD) with SiH4/N2/H2 gases. The interface and insulating properties of SiN films on GaN formed by the microwave-excited PECVD strongly depend on SiH4 flow rate. Although the interface trap density is lower than 10^11 cm ^\mathrm -2 eV ^\mathrm -1 at the relatively high SiH4 flow rate of 1 sccm, the breakdown electric field is very low ( $\sim 1$ MV/cm). Using the SiH4 plasma pretreatment before the stoichiometric SiN deposition, both low interface trap density and high breakdown voltage greater than 2 MV/cm are obtained. In this case, the clearly ordered Ga bonding near the SiN/GaN interface is estimated by an electron energy loss spectroscopy. The formation of SiN film on GaN using the microwave-excited PECVD is a very useful technique for the high-quality interface properties. [ABSTRACT FROM AUTHOR]

Performance and reliability of wide bandgap high-power amplifiers are correlated with their thermal behavior. Thermal model development and suitable temperature measurement systems are necessary to quantify the channel temperature of devices in real operating conditions. As a direct temperature measurement within a channel is most of the time not achievable, the common approach is to measure the device temperature at different locations close to the hotspot and then to use simulations to estimate the channel temperature. This paper describes a complete thermal characterization of AlGaN/gallium nitride (GaN) on silicon carbide high electron-mobility transistors (HEMTs) when devices are operating in dc bias, pulsed, and continuous wave. Infrared thermography, charge-coupled device-based thermoreflectance microscopy, and micro-Raman spectroscopy have been performed to extract the thermal resistance of the components. Results have been compared with simulations using a 3-D finite-element model to estimate the operating channel temperature. Measurements have shown that the RF-biased thermal resistance and the dc-biased thermal resistance of GaN HEMTs are similar. [ABSTRACT FROM PUBLISHER]

Measurements of the near-interface oxide traps (NIOTs) aligned to the conduction band of silicon-carbide (SiC) are of particular importance as these active defects are responsible for degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this brief, a new method for measurement of the active NIOTs with energy levels aligned to the conduction band is proposed. The method utilizes transient-current measurements on 4H-SiC MOS capacitors biased in accumulation. Nitrided oxide and dry oxide are used to illustrate the applicability of the proposed measurement method. [ABSTRACT FROM AUTHOR]

This paper presents the results of an investigation of the steady-state safe operating conditions for large-signal silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) circuits. By calculating capacitive currents within the intrinsic transistor, avalanche inducing currents through the transistor junctions are isolated and then compared with dc instability points established through simulation and measurement. In addition, calibrated technology computer-aided design simulations are used to provide further insight into the differences between RF and dc operation and stress conditions. The ability to swing the terminals of a SiGe HBT beyond the static $I$ – $V$ conditions coincident with catastrophic breakdown is explained. Furthermore, hot-carrier effects are also compared from multiple perspectives, with supporting data taken from fully realized $X$ -band and $C$ -band cascode driver amplifiers. This analysis provides microwave circuit designers with the framework necessary to better understand the full-voltage-swing potential of a given SiGe HBT technology and the resultant hot carrier damage under RF operation. [ABSTRACT FROM AUTHOR]

An improved Bosch etching process using inductively coupled plasma system has been investigated for the etching of 4H-silicon carbide (SiC). By optimizing the etch parameters, a mesa structure with nearly vertical sidewall and without microtrench at the bottom corner has been fabricated, and the formation and elimination of the microtrench are preliminarily discussed for the Bosch cycles in this paper. Scanning electron microscopic analysis was used to demonstrate the etched morphology under different etching conditions. Simple mesa-terminated 4H-SiC p-i-n diodes were fabricated. The effect of the improved mesa structure on the dc characteristics of the diodes has been experimentally verified by comparing with the nonoptimized mesa structure with microtrench. The results exhibited a completely consistent forward tendency and a similar reverse leakage level less than −900 V for both diodes, but different blocking performances. A maximum blocking voltage of 1565 V at room temperature was obtained from the nonmicrotrenched device with a mesa height of 4.3 \mu \textm , corresponding to 66% of a parallel plane breakdown voltage for the drift layer of 15 \mu \textm . Slight microtrench is the main cause of premature breakdown. [ABSTRACT FROM AUTHOR]

Large-signal (P1dB ) and small-signal (OIP3) radio frequency (RF) linearities of silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) fabricated in a new fourth-generation 90-nm SiGe BiCMOS technology operating at cryogenic temperatures are investigated. The SiGe BiCMOS process technology has an ƒT/ƒmax of 300/350 GHz. SiGe HBTs with two different layout configurations, collector-base-emitter (CBE) and CBE-base-collector (CBEBC), were characterized over temperature. Both dc and ac figures-of-merit are presented to aid in understanding the linearity, and to provide an overall performance comparison between the two layout configurations. The extracted peak ƒT/ƒmax for CBE and CBEBC at 78 K are 387/350 and 420/410 GHz, respectively. The P1dB and OIP3 linearity metrics for both configurations are comparable. Source- and load-pull measurements were performed at each temperature at 8 and 18 GHz, with the devices biased at a JC of 18 mA/μm2. Two-tone measurements over bias were also performed at 300 and 78 K with 50-Ω terminations for the source and load impedances. The 50 Ω results follow a similar response to the source- and load-pull measurements at 300 and 78 K, and demonstrate that the small-signal linearity of the SiGe HBTs is not adversely impacted by operation at cryogenic temperatures. The CBEBC configuration demonstrated the most consistent RF linearity performance at cryogenic temperature out of the two layout options. [ABSTRACT FROM PUBLISHER]

TCAD finite-element process simulations have been performed on Ge-channel n and pMOSFETs with embedded source/drain stressors or a strained Ge channel on a relaxed SiGe strain relaxed buffer (SRB), respectively, and compared with nanobeam diffraction strain measurements. While there is overall a good agreement between the simulated and experimental strain profiles, some deviations may occur, due to the presence of extended defects in the strain relaxed Ge buffer layers. This highlights the importance of selection of a strain-free reference in the relaxed Ge or SiGe SRB. [ABSTRACT FROM AUTHOR]

Silicon carbide power diodes and transistors are enabling technology for power electronics capable of operating in extreme environments. In this paper, a AgBiX solder paste has been studied for SiC power device die attach to power substrates for 200 °C use in vehicle and downhole well logging applications. The solder paste has a controlled amount of Sn, which limits the amount of Sn intermetallic formation. This produces a stable solder joint as a function of time at high temperature. The die shear strength remained at $\sim 38$ MPa through 2000 h of storage at 200 °C. After 1000 thermal cycles from −55°C to 195 °C, the percent die attach area reduction due to solder cracking was <10%. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) p-i-n diodes having five different n−-layer ( $i$ -layer) thicknesses from 48 to 268~\mu $ m are fabricated. The forward characteristics of SiC p-i-n diodes are significantly improved by carrier-lifetime enhancement. After this improvement, the differential on-resistance is inversely proportional to the square root of current density for all the diodes with different thicknesses of n−-layer. As a result, the forward current density–voltage characteristics can be approximately expressed by a parabolic function, as in the case of Si p-i-n diodes. Using a 268- \mu $ m-thick n−-layer, the lifetime enhancement, and an improved space-modulated junction termination extension structure, a very high blocking voltage over 26.9 kV and low differential on-resistance of 9.7 m \Omega \cdot are achieved. [ABSTRACT FROM AUTHOR]

In this brief, we demonstrate a straightforward approach to obtain isothermal electrical characteristics of state-of-the-art SiGe:C BiCMOS heterojunction bipolar transistors designed for mmWave applications. DC and conventional continuous-wave RF measurements are performed at different chuck temperatures ( Tchuck ). Knowing the thermal resistance ( R TH ) of the device, all the isothermal dc and ac (above thermal cutoff frequency) data can be determined. The validation of the methodology is demonstrated by comparing the results with the pulsed dc and pulsed RF measurements, which are found to be in good agreements. This method could be applied with a standard measurement equipment. [ABSTRACT FROM PUBLISHER]

In this paper, a table-based large-signal model for silicon germanium heterojunction bipolar transistors with the introduction of a breakdown network is presented to describe the avalanche breakdown effect of the base-collector junction on direct current and RF characteristics completely. Input oscillation and output inductive behaviors in the breakdown regime are found to be due to impact ionization induced holes and electrons, respectively. The avalanche breakdown effect and early effect modeled by the breakdown network and output resistance, respectively, can be distinguished in the presented model. In addition, a good agreement between the extracted total input and output resistances at RF and dc is obtained. The validity of this presented large-signal table-based model with multibias intrinsic parameters has been verified through the measured output spectrum and waveform. [ABSTRACT FROM PUBLISHER]