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Monolithic integration of junction barrier-controlled Schottky (JBS) diode with SiC MOSFET (termed JMOS) offers unique advantages. However, the short-circuit (SC) ruggedness issue stands in the way of the development of the conventional JMOS. The purpose of this numerical study is to investigate a new 4H-SiC JMOS with a self-pinching (SP) structure formed in the JFET region (termed SP-JMOS). The SP structure features that an N-type current spread layer is sandwiched between the P+ layer and the buried P-shield layer, forming a lateral JFET channel. In the forward conduction state, the lateral JFET channel self-pinches off and clamps the potential, thus limiting the saturation current of the device. In the blocking state, both the P+ layer and the buried P-shield layer collaboratively shield the Schottky contact and the SiC/SiO2 interface from a high electric field for long-term reliable operation. Numerical simulation results show that the proposed SP-JMOS not only withstands a roughly $2.6\times $ longer SC withstanding time than that of the conventional JMOS, but also shows an ultralow oxide electric field in the SP-JMOS. [ABSTRACT FROM AUTHOR]

The multiterminal memtransistor based on trap-rich transition metal dichalcogenide (TMD) materials has gained significant research interest due to their ability to mimic both homosynaptic and heterosynaptic plasticity. However, the current understanding of the underlying device physics remains somewhat lacking. In this article, we use a quasi-static technology computer-aided design (TCAD) model for the memtransistor based on molybdenum disulfide (MoS2) to investigate the role of the trap profile in the electrical properties. Assuming a Gaussian trap profile within the monolayer MoS2, the simulation results using our experimentally calibrated TCAD model show that tunneling width and Schottky barrier (SB) height at the contact can be modulated by shifts in the trap profile. In contrast to previous observations, we found that the presence of traps directly beneath the source contact in the MoS2 dopes the channel and forms an accumulation region, which allows for the injection of carriers vertically from the source into the accumulation region. Moreover, the trap profile may dramatically affect the Fermi level and the surface potential of the channel, which may be attributed to the quantum capacitance and inhomogeneous trap-related capacitances. The quantum capacitance, ${C}_{\text {q}}$ , is extracted to be 1.8 $\mu \text {F/cm}^{{2}}$ , whereas the equivalent total trap capacitance, ${C}_{\text {trap}}$ , is 0.9–1.8 $\mu \text {F/cm}^{{2}}$ (depending on the trap profile). Our findings indicate a much more complicated relationship between the trap profile and the electrical properties of MoS2 memtransistors than previously understood. [ABSTRACT FROM AUTHOR]

Dirac-source field-effect transistors (DS-FETs) have been proposed as promising candidates for low-power switching devices by leveraging the Dirac cone of graphene as a low-pass energy filter. In particular, using 2-D materials as the channel in a DS-FET is of interest for ultimate scaling purposes. In this article, we investigate the design considerations for 2-D DS-FETs using ballistic simulations based on the Landauer formalism. We study the impact of several key device parameters on the device performance, such as graphene doping, Schottky barrier heights, and effective mass of the 2-D channel. In Part II of this article, we study the impact of nonidealities on the performance of DS-FETs and benchmark the performance of DS-FETs for different channel materials. [ABSTRACT FROM AUTHOR]

Recently, WS2 has been considered a promising photodetector material due to its benefits of atomic thickness, easily customized single-crystal van der Waals heterostructure, and efficient photon absorption. However, the photosensitivity obtained from the WS2 photodetector is still unsatisfactory. Therefore, this article proposes a WS2-based high sensitivity field-effect transistor (FET) based on avalanche multiplication. Under 532-nm illumination, WS2 FET has ultralow dark current ($10^{-{12}}$ A), high responsivity (74 A/W), and high detectivity ($1.45\times 10^{{13}}$ Jones). In addition, the avalanche breakdown voltage of the device is reduced by employing graphene as an electrode. Because the height of the Schottky barrier can be reduced by replacing the Au electrode with a graphene electrode, the lower Schottky barrier can result in higher electric field intensity in the WS2 channel. Meanwhile, the unique transfer and output characteristics are observed in WS2 FET with graphene electrode. The inherent mechanisms are discussed, considering the Fermi-level tenability of graphene flakes and ambipolar transport properties of WS2. These results open a promising door to realize the WS2 FET with low power consumption and ultrahigh photoresponsivity, which will be ideal for high-performance photodetectors. [ABSTRACT FROM AUTHOR]

High performance normally-OFF hydrogenated diamond (C-H diamond) metal–insulator–semiconductor (MIS) field-effect transistors (FETs) have been achieved with Al/BaF2 gate materials. The 15-nm BaF2 film was formed by electron beam evaporation at room temperature. The flat-band voltage and hysteresis voltage extracted from the capacitance–voltage characteristics of the Al/BaF2/ C-H diamond MIS diode indicate low positive fixed charges and trapped charges in the BaF2 film. The 4- $\mu \text{m}$ FET device with a threshold voltage (${V}_{\text {TH}}$) of −0.90 V exhibits distinct pinch-off characteristics. The enhancement mode could be due to primarily the Schottky barrier depletion effect of the gate metal on the channel, and secondarily the positive fixed charges present in the BaF2 layer. The maximum transconductance and maximum saturated drain current are 30 mS/mm and −96.5 mA/mm, respectively. The device performance benefits from the decent conductivity at the BaF2/C-H diamond interface with an almost constant effective hole mobility of about 225.0 cm2/ $\text{V}\cdot \text{s}$ for −2.1 V $\le {V}_{\text {GS}}$ – ${V}_{\text {TH}} \le -4.1$ V. [ABSTRACT FROM AUTHOR]

The electrical characteristics of 2.3-kV 4H-SiC power Junction Barrier Schottky Field-Effect Transistors (JBSFETs) fabricated with 55-nm gate oxide thickness are reported as a function of temperature for the first time. The behavior of three cell topologies (linear, hexagonal, and octagonal) is compared. Excellent JBSFET characteristics are demonstrated up to 150 °C. The ON-resistance was found to increase by 45% from 25 °C to 150 °C for the linear and hexagonal cell layouts, which is much less than the 100% increase previously reported for silicon carbide (SiC) power MOSFETs. The threshold voltage decreases with temperature but remains above 1.2 V even at 150 °C for all cases. The third-quadrant current flow via the integrated JBS diode is confirmed to suppress body diode conduction at all temperatures. The leakage current remains below $1~\mu \text{A}$ even at 150 °C despite the presence of the Schottky contact in the JBSFET structure due to optimum JBS diode design. The octagonal cell topology is shown to exhibit the best figures of merit (FOMs) FOM[ $ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{C}_{ \mathrm{\scriptscriptstyle GD}}$ ] and FOM[ $ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{ Q}_{ \mathrm{\scriptscriptstyle GD}}$ ] even at elevated temperatures. The observed device behavior is explained using device analytical modeling. The analytical modeling reveals that the reduced rate of increase in ON-resistance with temperature for the 2.3-kV SiC JBSFETs is due to the relatively large source contact resistance produced by the lower (900 °C) contact anneal temperature. The lower anneal temperature is required to simultaneously make the Schottky contact for the JBS diode. [ABSTRACT FROM AUTHOR]

In this article, a novel lateral Schottky barrier high-low impact-ionization-avalanche-transit-time (IMPATT) diode, i.e., the high-electron mobility transistor (HEMT)-like IMPATT (HIMPATT) diode, is proposed based on the AlGaN/GaN 2-D electron gas (2-DEG). Numerical simulation demonstrated that the HIMPATT diode shows better characteristics than the conventional vertical IMPATT diode because of a superior property of the AlGaN/GaN 2-DEG. Comparing with the vertical IMPATT diode, the optimum frequency of HIMPATT diode rises from 260 to 380 GHz, the maximum RF output power ${P}_{RF}$ rises from 2.30 to 3.06 MW/cm2, and the maximum conversion efficiency $\eta $ rises from 14.7% to 18.5%. In addition, simulation results reveal that the trench length ${L}_{r}$ and depth ${D}_{r}$ of the 2-DEG channel significantly influence the output performances of HIMPATT diode, where the frequency characteristic is more sensitive to the trench length ${L}_{r}$ and the RF power characteristic is more sensitive to the trench depth ${D}_{r}$. By designing the pattern shape of the trench area, a monolithic integrated HIMPATT diode oscillator array can be implemented on one chip to generate a wider frequency band with great RF performances than the vertical IMPATT diode. It provides more variable designing options for the applications of the HIMPATT diode in the terahertz regime. [ABSTRACT FROM AUTHOR]

For the first time, a novel analytical model of contact resistance (${R}_{\text{contact}}$) in vertically stacked nanosheet FETs (NSHFETs) with a silicide/Si (100) contact for a sub-3-nm node is presented. Generally, ${R}_{\text{contact}}$ consists of the interface resistance (${R}_{\text{interface}}$) and spreading resistance (${R}_{\text{spread}}$). Herein, a new model of ${R}_{\text{interface}}$ of silicide/Si (100) contact, which simultaneously considers the source/drain (S/D) doping concentration (${N}_{\text{si}}$), Schottky barrier height (SBH), and SBH lowering, is demonstrated simultaneously. In addition, a new model of ${R}_{\text{spread}}$ that divides S/D into multiple resistance components for vertically stacked NSHFETs is suggested. In vertically stacked NSHFET with 3-nm node, for TiSi2/n-Si (100) and NiPtSi2/p-Si (100) contacts, ${R}_{\text{spread}}$ shows more than ~50.0% higher values compared to ${R}_{\text{interface}}$. On the other hand, 3-nm node FinFET with TiSi2/n-Si (100) and NiPtSi2/p-Si (100) contacts, ${R}_{\text{spread}}$ shows more than ~53.7% lower values compared to ${R}_{\text{contact}}$. The results show that ${R}_{\text{spread}}$ becomes dominant in ${R}_{\text{contact}}$ compared to ${R}_{\text{interface}}$ when using NSHFETs, in contrast to the conventional FinFETs in which ${R}_{\text{interface}}$ is dominant in ${R}_{\text{contact}}$. The high ${R}_{\text{spread}}$ of the NSHFET is mainly caused by the low nanosheet thickness and vertical pitch between the nanosheets. This study provides critical insights into the design of the source/drain of NSHFET for sub-3-nm CMOS technology. [ABSTRACT FROM AUTHOR]

TCAD modeling of the dynamic threshold voltage shift (hysteresis) occurring under fast sweeping characterization in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) is reported, to the best of our knowledge, for the first time. Dynamic ${V}_{\text{TH}}$ hysteresis has been first experimentally characterized under different sweeping times, temperatures, and AlGaN barrier configurations. Then, TCAD simulations have been carried out, reproducing the experimental evidences and understanding the microscopic mechanisms responsible for such effect. In particular, nonlocal tunneling models implemented in Sentaurus TCAD, defined at the gate Schottky contact and assisted by traps in the AlGaN barrier layer, have been adopted and properly tuned against experiments. Results show that the dynamic ${V}_{\text{TH}}$ hysteresis is mainly caused by the time-dependent hole charging/discharging processes in the floating p-GaN layer, which are governed by the Schottky and AlGaN barrier leakage current components. [ABSTRACT FROM AUTHOR]

A bipolar equivalent circuit model is developed for silicon hetero-junction silicon solar cells (SHJ) with a Schottky contact between the p-type amorphous silicon and the transparent conducting oxide (TCO). The Schottky barrier is treated as a bipolar collector junction through which holes are transported by thermionic emission, while electrons reaching the barrier are swiftly collected. The electron current is shown to suffer an Early effect especially in cells with low a-Si:H(p) doping level. The results of the equivalent circuit analysis in the dark and under illumination perfectly match both the ${J}$ – ${V}$ characteristics resulting from AFORS-HET device simulations and the measured ${J}$ – ${V}$ characteristics of real cells, with low and with high doping levels in a-Si:H(p). The model provides a clear interpretation for the role of the Schottky diode in the degradation of the cell open circuit voltage and in the ${S}$ -shape distortion of the ${J}$ – ${V}$ characteristics under illumination. Such degradations disappear if hole tunneling through the Schottky contact prevails. [ABSTRACT FROM AUTHOR]

Though infrared (IR) photodetection is popular, it faces several problems. First, the main materials, compound semiconductors, require high temperature, low pressure, and high energy consumption facilities. Second, compound semiconductor elements are rare on earth. Third, compound semiconductors are difficult to integrate with Si-based integrated circuit (IC) manufacturing process. To overcome these problems, we utilized a Si-based Schottky junction and internal photoemission to break the detection limit of a Si photodetector. The spectral detection limit extends from 1100 nm, the bandgap wavelength of Si, to ca. 1600 nm, the Schottky barrier wavelength of the metal/Si junction. The Schottky junction is composed by Ag and n-type Si through simple thermal evaporation. The light incident direction, metal thickness, and device temperature were analyzed. As a result, under normal temperature and pressure, the Schottky barrier height of the Ag/Si junction is 0.742 eV. The detection limit is 1670 nm. If the 1550-nm laser is a detected light source illuminating from the metal film, the responsivity is 0.02122 mA/W. If the same detected light source illuminates from the Si substrate, the responsivity improves to 0.04567 mA/W due to the light absorption enhancement. Furthermore, if the metal thickness is increased to 100 nm, the responsivity increases to 1.242 mA/W, which is about 585.3% of the original value. In addition, the influence of the temperature on the electric properties of the devices indicates that a Ag/Si Schottky device could be a candidate for temperature detection. [ABSTRACT FROM AUTHOR]

The article reports a comprehensive study optimizing the OFF- and ON-state characteristics of 3.3 kV junction barrier Schottky (JBS) diodes made using nickel, titanium, and molybdenum contact metals. In this design, the same implants used in the optimized termination region are used to form the P-regions in the JBS active area. The width and spacing of the P-regions are varied to optimize both the ON- and OFF-state of the device. All the diodes tested displayed high blocking voltages and ideal turn-on characteristics up to the rated current of 2 A. However, the leakage current and the Schottky barrier height (SBH) were found to scale with the ratio of Schottky to p+regions. Full Schottkys, without p+regions, and those with very wide Schottky regions had the lowest SBH (1.61 eV for Ni, 1.11 eV for Mo, and 0.87 eV for Ti) and the highest leakage. Those diodes with the lowest Schottky openings of $2 ~\mu \text{m}$ had the lowest OFF-state leakage, but they suffered severe pinching from the surrounding p+regions, increasing their SBH. The best performing JBS diodes were Ni and Mo devices with the narrowest pitch, with the p+implants/Schottky regions both $2 ~\mu \text{m}$ wide. These offered the best balanced device design, with excellent OFF-state performance, while the Schottky ratio guaranteed a relatively low forward voltage drop. [ABSTRACT FROM AUTHOR]

Vertical field effect transistors (VFETs) based on conductive network electrodes feature high current density and compatibility in printing processes. Here, the device structures of VFETs are designed and optimized toward good current saturation and a better ON–OFF ratio. Among the three different structures, a simple structure stands out as the best: a semiconducting layer is inserted below the source electrode to increase the injected area of carriers and to enhance L-type channels (the channels along the semiconductor–dielectric interface and then to the drain), whereas an insulating layer is added on the top and two sides of the source electrode to generate a depletion region and to suppress I-type channels (the channels from the top of the source to the drain). The introduction of moderate Schottky barriers to the source electrodes further benefits the current saturation and gate tuning. The 2D-technology computer-aided design (TCAD) simulations are performed to analyze the physical mechanisms by quantifying the distribution of potentials, carrier concentrations, and current densities. The simulated current–voltage relations show a differential output resistance over 105 $\Omega \cdot $ cm and an ON–OFF ratio over 105, indicating that the problems of current saturation and the ON–OFF ratio in short-channel VFETs have been theoretically solved to some extent. [ABSTRACT FROM AUTHOR]

In this article, a novel ${p}$ -GaN high-electron-mobility transistor (HEMT) with a built-in Schottky barrier diode (SBD) is proposed and investigated by TCAD simulation. The anode contact of the integrated SBD is isolated from the ohmic contact of the source electrode by a ${p}$ -GaN isolation region. The cathode of the SBD is connected to the drain electrode. In the proposed Schottky barrier diode/HEMT (SB-HEMT), a channel under the ${p}$ -GaN isolation region is turned on during forward conduction to further reduce the specific ON-resistance (${R}_{ {\text{ON}},\text {sp}}$). With a minimum sacrifice on ${R}_{ {\text{ON}},\text {sp}}$ , the reverse ON-state voltage, ${V}_{\text {R}- {\text{ON}}}$ (at a current density of 50 mA/mm), for the SB-HEMT is reduced by 33% (from 2.43 to 1.62 V) when compared with a conventional HEMT (C-HEMT). Compared with the C-HEMT with a separate on-chip SBD (C-HEMT/SBD), the SB-HEMT shows much better trade-off between ${V}_{\text {R}- {\text{ON}}}$ and ${R}_{ {\text{ON}},\text {sp}}$. The total switching loss (${E}_{\text {total}}$) of the proposed SB-HEMT with resistive load is lower than that of the C-HEMT and is reduced by up to 21% when compared with that of the C-HEMT/SBD with different area ratio between the HEMT and SBD regions. [ABSTRACT FROM AUTHOR]

The popular Tung model for Schottky barrier inhomogeneity considers how low-barrier patches (embedded in a high barrier background) impact the diode current. However, Tung’s model fails to account for the image-force effect. We analyze how the image force alters the current through an inhomogeneous barrier and find that, in some circumstances, it will smooth the barrier, such that the current will effectively be that of a homogeneous diode. We also show that for a distribution of defect barriers and/or sizes, the diode current can be intermediate between that of a homogeneous diode and a diode dominated by the low-barrier patches. We calculate the parameter values associated with this transitional region. A survey of existing literature applications of Tung’s model shows that many diodes are actually operating in this transition region, where Tung’s equations are in error. We provide the corrected equations for this case and demonstrate their ability to model practical diode characteristics. [ABSTRACT FROM AUTHOR]

Schottky contacts have been used to fabricate normally- OFF lateral reverse-blocking MESFETs on p-type (boron-doped) O-terminated monocrystalline diamond. The devices utilized an ohmic source contact but both gate and drain contacts were Schottky in nature. Boron-doped p-channel diamond MESFETs reported to date display the less attractive normally- ON characteristics. Here, the normally- OFF transistor delivered a current level of ~1.5 $\mu $ Amm−1 at a negative ${V}_{\text {GS}}$ of 0.8 V and a transconductance (${g}_{m}$) of $16~\mu $ Smm−1, measured at room temperature (RT); at a temperature of 425 K, these values rose to $\sim 70~\mu $ Amm−1 for ${I}_{\text {DS}}$ and a ${g}_{m}$ value of $260~\mu $ Smm−1. In both cases, a negligible gate leakage current was measured with no breakdown apparent at the maximum field investigated here ($3.7\times 10^{{5}}$ V/m−1). The Schottky gate demonstrates a well-behaved control of the channel even at higher temperatures. The high-temperature operation, normally- OFF behavior, and diamond’s inherent radiation hardness make this transistor promising for harsh environment applications. [ABSTRACT FROM AUTHOR]

Carbon nanotube field-effect transistor (CNTFET) shows great potential for digital and analog applications due to the unique 1-D ballistic carrier transport in carbon nanotubes (CNTs). A new compact physical model for CNT Schottky-barrier transistors is proposed in this article. The Schottky barrier between the contact metal and CNTs is described by using an effective barrier height, and more importantly, the influence of using CNT arrays or networks rather than a single CNT as the device channel is considered in this model. Moreover, the trapping effect is investigated and modeled by adding RC delay element to the equivalent circuit. The model is proposed in a concise form to avoid complex operations such as integration and is compatible with circuit simulation. The simulation results of ${I}-{V}$ characteristics are verified to be in agreement with experimental data. [ABSTRACT FROM AUTHOR]

We fabricated Zr/p-diamond Schottky barrier diodes (SBDs) with and without a ultrathin atomic layer-deposited Al2O3 interlayer. The effects of the Al2O3 interlayer on the electrical properties of devices were investigated using the current–voltage (${I}-{V}$) and capacitance–voltage (${C}-{V}$) characteristics at room temperature. Compared with Zr/p-diamond SBDs without the interlayer, SBDs with a 2-nm-thick Al2O3 interlayer exhibited higher Schottky barrier height and breakdown voltage. The insertion of the Al2O3 layer effectively reduced the interface state and it is considered that the barrier enhancement is attributed to the significant reduction of interface state density. This work provides a simple method to passivate the diamond surface and modulate the barrier heights of diamond SBDs. [ABSTRACT FROM AUTHOR]

The electrical properties of NiSiGe alloys with different compositions have been investigated, as a function of Si content. It is found that the resistivity of NiSiGe decreases with increasing the Si content. In addition, the NiSiGe exhibits a smaller Schottky barrier height (SBH) with p-Ge with a higher Si component, attributable to the increased work function. As a result, the high Si content NiSiGe alloy is a promising candidate for the contact metal in the Ge pMOSFETs with sufficiently suppressed source/drain (S/D) parasitic resistance. It is confirmed that the NiSiGe is feasible to satisfy the requirements as the contact metal material for Ge pMOSFETs in 5-nm node and above technology node, by modulating the Si content. [ABSTRACT FROM AUTHOR]

This article reports GaN super-heterojunction Schottky barrier diodes (SHJ-SBDs) with substantially improved performance. Metal-2DEG sidewall n-ohmic contacts were deployed to achieve low contact resistance of $0.75~\Omega ~ \cdot ~mm$ , avoiding the risk of abnormally high contact resistance caused by inaccurate etch depth control. A pGaN notch formed near the cathode successfully eliminated excessive hole conduction caused by the sidewall n-ohmic contact. Isolation was improved by a high-energy Al implantation step. The resulting SHJ-SBD exhibited a breakdown voltage (BV) of ~12.5 kV and a specific resistance of 100.8 $\text{m}\Omega ~ \cdot ~cm^{2}$. [ABSTRACT FROM AUTHOR]

We report GaN vertical trench MOS barrier Schottky (TMBS) diodes with embedded p-GaN shielding rings (SRs) and systematically investigate the impact of different structural parameters of the p-GaN SRs on the breakdown performance of the GaN-based vertical TMBS diodes by numerical simulation. The charge coupling effect by the embedded p-n junction at the bottom of the trench homogenize the electric field at the trench corner and alleviate the electric field crowding effect at the Schottky contact region, which can effectively avoid the premature breakdown and improve the reverse blocking capability of the TMBS diodes. The p-GaN SRs can also broaden the overlapped depletion region and shift the pinch-off point into the n−-GaN drift region, thus facilitating the 2-D depletion in the n−-GaN drift layer and boosting the breakdown performance of the conventional TMBS diodes. We found that the doping concentration, thickness, and the width of the p-GaN SRs are closely associated with the electric field distribution and the reverse breakdown characteristics of the GaN-based vertical TMBS diodes. The vertical TMBS diodes with optimal p-GaN SR parameters featured a dramatic improvement in the breakdown voltage from 907 to 1281 V, without an obvious degradation in the ON performance. The proposed TMBS diodes with a p-GaN SR structure can pave the way toward a high-performance GaN vertical power device for high-power and high-efficiency power switch applications. [ABSTRACT FROM AUTHOR]

We present, here, advanced density functional theory and nonequilibrium Green’s function (DFT–NEGF) techniques that we have implemented in our ATOmistic MOdeling Solver (ATOMOS) to explore transport in novel materials and devices, particularly in van der Waals (vdW) heterojunction transistors. We describe our methodologies using plane-wave DFT, followed by a Wannierization step, and a linear combination of atomic orbital DFT that lead to orthogonal and nonorthogonal NEGF models, respectively. We then describe in detail our nonorthogonal NEGF implementation including the Sancho–Rubio method and electron–phonon (e–ph) scattering within a nonorthogonal framework. We also present our methodology to extract e–ph coupling from first principles and include them in our transport simulations. Finally, we apply our methods to the exploration of novel 2-D materials and devices. This includes 2-D material selection and the dynamically doped FET for ultimately scaled MOSFETS, the exploration of vdW tunneling field-effect transistors (TFETs), in particular the HfS2/WSe2 TFET that could achieve high ON-current levels, and the study of Schottky barrier height and transport through a metal-semiconducting WTe2/WS2 vdW junction transistor. [ABSTRACT FROM AUTHOR]

The design space of Ga2O3-based devices is severely constrained due to its low thermal conductivity and absence of viable p-type dopants. In this work, we discuss the limits of operation of a novel Ga2O3–Al2O3–diamond-based super-junction device concept, which can alleviate the constraints associated with Ga2O3-based devices. The improvements achieved using the proposed device concept are demonstrated through electrical and thermal simulations of Ga2O3–Al2O3–diamond-based super-junction Schottky barrier diodes (SJ-SBDs) and non-punch-through or conventional Schottky barrier diodes (NP-SBDs). The SJ-SBD enables operation below the ${R}_{\mathrm {\scriptscriptstyle ON}}$ -breakdown voltage limit of Ga2O3 NP-SBD, enabling >4 kV blocking voltage at ${R}_{\mathrm {\scriptscriptstyle ON}}$ of 1–3 $\text{m}\Omega $ cm2. The maximum switching frequency of SJ-SBD may be only a few kHz, as it is limited by the activation energy of acceptors (0.39 eV) in the diamond. Crucially, compared with NP-SBD, the use of diamond also results in ~60% reduction in temperature rise during static power dissipation. Polycrystalline diamond (PCD) properties depend on detailed microstructure and benefits compared to ideal Ga2O3 NP-SBD arise for diamond critical fields ≥6 MV/cm and thermal conductivities as low as 50–150 W/(m $\cdot $ K). [ABSTRACT FROM AUTHOR]

Contact-controlled devices, such as source-gated transistors (SGTs), deliberately use energy barriers at the source, and naturally, the positive temperature dependence (PTD) of drain current can be utilized for temperature sensing. We exploit the difference in drain current activation energy, which arises with contact doping in polysilicon n-type contact-controlled transistors, to demonstrate output current with either a PTD or negative temperature dependence (NTD). The range over which output current varies linearly with temperature, as well as the sensitivity, can be tailored by the choice of reference current magnitude and relative source contact properties within the current mirror. The sensing scheme simplifies the circuit design because it relies solely on thin-film transistors and it has inherent immunity to output voltage variation. This ability to tune the sign of temperature dependence allows facile integration in applications requiring homeostasis via feedback, e.g., electronic skin, in a minimal layout area and potentially with convenient reduction of patterning steps during fabrication. [ABSTRACT FROM AUTHOR]

A novel compact realization of the XNOR/ XOR function is demonstrated with multimodal transistors (MMTs). The multimodal thin-film transistors (MMT’s) structure allows efficient use of layout area in an implementation optimized for unipolar thin-film transistor (TFT) technologies, which may serve as a multipurpose element for conventional and emerging large-area electronics. Microcrystalline silicon device fabrication is complemented by physical simulations. [ABSTRACT FROM AUTHOR]

The operation of reconfigurable field effect transistor (RFET) is governed by Schottky barrier, ungated regions as well as control and polarity gates. The inherent architecture of RFET, apart from lowering the effective drain bias, impedes the use of existing mobility extraction methodologies. In this brief, we propose a simple and effective methodology to evaluate the resistance offered by various regions, ascertain the effective drain bias across the un-gated transistor, and extract apparent low field mobility and its degradation coefficients in RFET. The developed analytical expressions for drain current (${I}_{{\text {DS}}}$) and transconductance (${g}_{m}$) of RFET are able to accurately predict current (${I}_{\text {DS}}$) - control gate (${V}_{\text {CG}}$), and ${g}_{m}$ – ${V}_{\text {CG}}$ characteristics. [ABSTRACT FROM AUTHOR]

A ZnO-based Schottky thin-film transistor (TFT) utilizing palladium-titanium (Pd-Ti) source/drain electrodes as a sensing medium is used to fabricate a room temperature (RT) hydrogen sensor. In the absence of any heating element, the fabricated sensor is capable of reducing the design complications and power consumption considerably. The RT sensor response was realized with respect to drain current rise owing to the Schottky barrier height reduction depending on the H2 concentration (500–4500 ppm). For 500-ppm (minimum detection level) and 4500-ppm (maximum detection level) H2 gas concentrations, sensor responses of 18% and 78.2% with 65 s/35 s and 10.2 s/85 s response/recovery times are acquired, respectively. The Pd-Ti/ZnO Schottky barrier height variation is attempted to explain the incorporating energy band diagrams of the ZnO channel between source/drain electrodes at different gate and drain bias conditions. Performance analysis of the sensor in terms of repeatability, selectivity toward H2 over methane and acetone, hysteresis, reliability, and humidity exposure has also been examined. [ABSTRACT FROM AUTHOR]

The poor response time and incomplete recovery of MoS2 sensor at room temperature (RT) have been a serious issue to obstruct its widely sensing applications. In present work, we comprehensively studied three methods: rising temperature, building field-effect transistors (FETs), and adding light illumination to improve the performance of the device. The related sensing mechanism of the three processes was also analyzed. The high response rate up to 2510%, low theoretical concentration detection limit down to 693 ppb, and excellent recovery at RT to NO2 were achieved for the MoS2 FET sensor with the aid of light illumination. This significant improvement in sensing performances is mainly attributed to the activated sensing layer by phonon energy transfer and enhanced population of the charge carrier raised from optical energy. Schottky barrier modulation was also an important factor to impact sensing performance. Furthermore, the MoS2 nanosheets exhibit good photosensing characteristics such as rapid photon response, high light-induced photocurrent, and so on. It has been demonstrated that the light illuminated FET configuration can effectively accelerate response time and promote recovery rate of MoS2-based sensor operating at RT, which provides a strategy to design an optoelectronic device with optimal sensing properties. [ABSTRACT FROM AUTHOR]

We present analytical physics-based compact models for the Schottky barriers at the interfaces between the organic semiconductor and the source and drain contacts in organic thin-film transistors (TFTs) fabricated in the coplanar and the staggered device architecture, and we illustrate the effect of these Schottky barriers on the current–voltage characteristics of the TFTs. The model for the source barrier explicitly considers the field-dependent barrier lowering due to image charges. Potential solutions have been derived by applying the Schwarz–Christoffel transformation, leading to expressions for the electric field at the source barrier and for the contact resistance at the source contact. With regard to the drain barrier, a generic compact-modeling scheme based on the current–voltage characteristics of a barrier-less TFT is introduced that can be applied to any compact dc model. Finally, both models are incorporated into an existing charge-based compact dc model and verified against the results of measurements performed on coplanar and staggered organic TFTs with channel lengths ranging from 0.5 to $10.5~\mu \text{m}$. [ABSTRACT FROM AUTHOR]

Nanosheet gate-all-around field-effect transistors (NS GAAFETs) suffer from self-heating effects (SHEs), degrading their performance. This work demonstrates that using a Schottky barrier drain contact facilitates simultaneous optimization of the thermal resistance ($R_{{\text {th}}}$) and ON-current, leading to both ameliorated device performance and thermal reliability. Synopsis Sentaurus TCAD results delineate that thermoelectric cooling at the Schottky drain alleviates the SHEs reducing the maximum lattice temperature (${T}\,_{L}^{{\text {max}}}$) of up to 20.12 K compared to that at an ohmic drain contact. [ABSTRACT FROM AUTHOR]

We investigate the operation modes of a dual-gate reconfigurable field-effect transistor (RFET). To this end, dual-gate silicon-nanowire FETs are fabricated based on anisotropic wet etching of silicon and nickel silicidation yielding silicide-nanowire Schottky junctions at source and drain. We compare the program gate at source (PGAS) with the more usual program gate at drain (PGAD) operation mode. While in PGAD mode, ambipolar operation is suppressed, switching is deteriorated due to the injection through a Schottky barrier. Operating the RFET in PGAS mode yields a switching behavior close to a conventional MOSFET. This, however, needs to be traded off against strongly nonlinear output characteristics for small bias voltages. Our measurement results are supported by transport simulations employing a nonequilibrium Green’s function approach. [ABSTRACT FROM AUTHOR]

Experimental observations have long-established that there exists a smooth roll-off or knee transition between the temperature-limited (TL) and full-space-charge-limited (FSCL) emission regions of the emission current density-temperature (J – T) (Miram) curve, or the emission current density-voltage (J – V) curve for a thermionic emission cathode. In this article, we demonstrate that this experimentally observed smooth transition does not require frequently used a priori assumptions of a continuous distribution of work functions on the cathode surface. Instead, we find that the smooth transition arises as a natural consequence of the physics of nonuniform thermionic emission from a spatially heterogeneous cathode surface. We obtain this smooth transition for both J – T and J – V curves using a predictive nonuniform thermionic emission model that includes 3-D space charge, patch fields (electrostatic potential nonuniformity on the cathode surface based on local work function values), and Schottky barrier lowering physics and illustrates that a smooth knee can arise from a thermionic cathode surface with as few as two discrete work function values. Importantly, we find that the inclusion of patch field effects is crucial for obtaining accurate J – T and J – V curves, and the further inclusion of Schottky barrier lowering is needed for accurate J – V curves. This finding and the emission model provided in this article have important implications for modeling electron emission from realistic, heterogeneous surfaces. Such modeling is important for an improved understanding of the interplay of emission physics, cathode materials engineering, and the design of numerous devices employing electron emission cathodes. [ABSTRACT FROM AUTHOR]

Recently, 2-D transition metal dichalcogenides (TMDs) lateral heterojunction field-effect transistors (FETs) have been demonstrated experimentally, in which metallic TMDs were used for the source/drain. In this work, we systematically investigate the contact property and device performance of monolayer 1T/1T'-2H MoS2, MoSe2, and MoTe2 FETs. Schottky barrier (SB) heights are extracted from density functional theory calculations, and nonequilibrium Green’s function transport simulations have been performed to study device characteristics. Our simulation results show that the inherent SB strongly affects the overall performance of these devices. Here, we optimize the performance of TMD lateral heterojunction FETs by using two different approaches. First, we have improved the electrostatic control by scaling equivalent oxide thickness and gate underlap, which boosts both ON- and OFF-state characteristics, making the device suitable for high-performance applications. On the other hand, moderate doping has been used in the gate underlap region, improving ON/OFF current ratio with negligible impacts on ON-state characteristics, and this approach is more preferred for low-power applications. This study reveals that 1T'-2H MoTe2 FET shows the highest ON current (~ 1 mA/μm) among the three with a reasonably small subthreshold swing (80 mV/dec) if properly scaled, while 1T-2H MoS2 FET exhibits the highest ION/IOFF (~107) when ohmic contact is established with moderate doping in the gate underlap region. This study not only provides physical insight into the electronic devices based on novel TMD heterostructures but also suggests engineering practice for device performance optimization in experiments. [ABSTRACT FROM AUTHOR]

In this article, we have systematically investigated the effect of annealing of fabricated GaN Schottky barrier diodes (SBDs) and anode metals with various work-functions on the performance of AlGaN/GaN SBDs. It is found that after annealing of fabricated GaN SBDs, the interface states between the metal and GaN etching surface are suppressed, the device stability is enhanced, and the turn-on voltage (VON) shows negligible degradation. Meanwhile, high-performance AlGaN/GaN SBDs with various work-function metals as anode have been achieved by adapting the annealing treatment. The calculated Schottky barrier heights of the fabricated SBDs with Cr, W, and Ni anode is 0.27, 0.68, and 0.98 eV, respectively, which are almost the same as those estimated from XPS measurements. A low turn-on voltage of 0.42 V and low leakage current of 0.3 μA/mm are obtained by using the low work-function metal W (4.6 eV) as anode. Furthermore, the SBDs fabricated with the high work-function metal Ni (5.1 eV) shows an extremely low-leakage current of 6 nA/mm and exhibit a current ON/OFF ratio of 109 while also showing great characteristics at high temperature. [ABSTRACT FROM AUTHOR]

Dopant segregation (DS) technique has been extensively employed to tune Schottky barrier heights (SBHs) of NiSi/Si diodes, either leading to reduced specific contact resistivity (ρc) in source/drain (S/D) Ohmic contacts, or enhanced current drivability in Schottky barrier S/D MOSFET (SB-MOSFET) where metallic NiSi is employed as S/D. A capacitance–voltage (C – V) method is usually adopted to reliably extract the SBHs of NiSi/Si for investigating the effectiveness of such a DS technique. In order to avoid large reverse leakage current which rules out the possibility of SBHs extraction during C – V measurements, dopants with opposite polarity to that in epitaxial Si substrate segregate at the NiSi/Si interface, for instance, boron DS (B DS) for NiSi/n-Si and arsenic DS (As DS) for NiSi/p–Si. This, however, raises one critical question, i.e., NiSi/p+–Si (B DS)/n-Si and NiSi/n+–Si (As DS)/p–Si are p–n or Schottky junctions. In this work, a dedicated circuit is devised to distinguish the type of as-fabricated NiSi/Si diodes with DS based on different switching mechanisms between p-n and Schottky junctions. [ABSTRACT FROM AUTHOR]

Planar 650-V 4H-silicon carbide (SiC), inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors (JBSFETs) with three types of cells are compared in this article for the first time. Devices with linear, hexagonal, and octagonal layouts were fabricated in a commercial foundry. The JBS diode was integrated within each cell type. The Schottky contact width for the JBS diode was adjusted to optimize third-quadrant ON-state voltage drop to below 2.5 V for each cell type to ensure by-passing the body diode while maintaining good blocking characteristics in the first quadrant. The hexagonal cell case was the only one whose breakdown voltage (560 V) fell below the 650-V rating. The highest breakdown voltage (710 V) was observed with the octagonal cell layout with a low leakage current of 10 nA at 600 V. The lowest specific ON-resistance was observed for the hexagonal cell design. However, its gate–drain charge was twice that of the conventional linear cell design and four times that of the octagonal cell design. The data from this work demonstrate that the best overall performance for the 650-V SiC, inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors is achieved by using the octagonal cell design. [ABSTRACT FROM AUTHOR]

In this work, we have explored the design space for multifinger planar Schottky barrier diodes (SBDs) using AlN/GaN heterostructure for terahertz (THz) applications. Using a well-calibrated computational modeling framework, we have identified the critical design parameters and associated parasitic elements affecting diode’s THz performance. The 3-D modeling of parasitics components has been deployed as the 2-D design approach overestimates the performance or underestimates the parasitic components in a multifinger design. Device design guidelines and the tradeoff between various parameters are discussed in detail. The optimum design space and related tradeoffs were found to be nonintuitive due to the presence of 3-D parasitics capacitances and resistances. [ABSTRACT FROM AUTHOR]

The organic field-effect transistors (OFETs) have developed rapidly in recent years. However, compared with the p-type OFETs, the n-type devices always show poorer performance due to their hard electron injection and low stability. It is necessary to further improve the charge injection properties of n-type OFETs. In this work, indium (In) layers, as an interlayer above contacts, were adopted for electron injection improvement in the n-type poly((N, N'-bis(2-octyldodecyl)-1,4,5,8-naphthalenedicarboximide-2,6-diyl)-alt-5, 5'-(2, 2'-bithiophene)) (N2200) OFETs. The injection barrier, such as Schottky barrier, at the metal/semiconductor interface was effectively weakened with the In interlayers thickness (TIn) increasing from 0 to 6 nm. The mechanism of electron injection changed from thermionic emission to tunneling, as the TIn reaching 6 nm. It results in a marked improvement in electrical properties for N2200 OFETs. The mobility increased from 0.09 to 0.29 cm2 ⋅ V−1 ⋅ s−1 while the subthreshold swing decreased from 2.7 to 0.8 V ⋅ dec−1 with the TIn. This work provides an efficient approach for the electron injection improvement in n-type OFETs. [ABSTRACT FROM AUTHOR]

Integration of an enhancement-mode (E-mode) metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT) with a high-performance lateral Schottky barrier controlled Schottky (LSBS) rectifier in a compact layout is fabricated on an ultrathin-barrier AlGaN/GaN heterostructure grown on Si substrate. The state-of-the-art reverse conduction voltage (Vrev) of 0.455 V was achieved in the monolithic integrated E-mode power device with a threshold voltage of 1.55 V. Vrev exhibited a tiny temperature variation of 0.66% from 0 °C to 150 °C compared with that of 157% for the controlled E-mode HEMT. [ABSTRACT FROM AUTHOR]

The impact of As preamorphization implant (PAI) on specific contact resistivity (ρc) is investigated for Ti-based Ohmic contacts on n+-Si in this article. The ρc value of TiSix/n+ −Si contacts is greatly improved with low-dose As PAI whereas this improvement is impaired with increased dose of As PAI. The ρc results from the joint effort of the reduction of effective Schottky barrier height (SBH) to electrons (φbn,eff) , retardation of Ti silicidation, and annihilation of end-of-range (EOR) defects. Besides, the interfacial microstructures of TiSix/n+ −Si affect ρc, correlated with the post metal anneal (PMA). [ABSTRACT FROM AUTHOR]

In general, self-powered photodetectors are tedious and costly. Here, high-performance self-powered visible photodetectors based on MAPbI3 films were fabricated by using asymmetric Au electrodes. For this construction of photodetector, the illumination passing through the translucent MAPbI3 film can reduce the Schottky barrier between the lower electrode and perovskite, and the Au particles doping into the MAPbI3 at the contact areas between the upper electrode and films can also change the Schottky barrier, which leads to the formation of built-in potential. Without an applied bias, the photodetectors exhibit an ultralow dark current of ~ 3 pA. At the power intensity of 2.92 mW/cm2 under 635 nm illumination, a decent responsivity of 10 mAW−1, a high specific detectivity of 3.3 × 1011 cmHz1/2W−1, and an external quantum efficiency of 2.1% are obtained. The on/off ratio reaches 104 and the response speed is less than 50 ms. Our results pave a new design concept to form a self-powered perovskite-based photodetector. [ABSTRACT FROM AUTHOR]

In this brief, a high-performance quasi-vertical GaN Schottky barrier diode (SBD) on sapphire substrate with post-mesa nitridation process is reported, featuring a low damaged sidewall with extremely low leakage current. The fabricated SBD with a drift layer of 1 μm has achieved a very high ON/ OFF current ratio (ION/IOFF) of 1012 with a low leakage current of ~ 10−9 A/cm2@-10 V, high forward current density of 5.2 kA/cm2 at 3 V in dc, a low differential specific ON-resistance (RON,sp) of 0.3 mΩ ⋅ cm2, and ideality factor of 1.04. In addition, a transmission-line-pulse (TLP) I – V test was carried out and 53 kA/cm2 at 30 V in pulsed measurement was obtained without device failure, exhibiting a great potential for high power applications. [ABSTRACT FROM AUTHOR]

Fabrication of dual-barrier planar (DBP) structure diamond Schottky barrier diodes (SBDs) with only Ni Schottky contact was carried out by rapid thermal annealing. Ni/Au narrow stripes were first patterned on p− layer and annealed at 550 °C to decrease Schottky barrier height and form low barrier contact. Then, Ni/Au Schottky electrodes were deposited on the window area between stripes to serve as high barrier contact. Ti/Pt/Au ohmic contact was formed on the back side of p+ diamond substrate. The fabricated DBP structure SBDs exhibit low forward voltage drops compared with single high barrier diode, and reverse leakage current densities of two to three orders of magnitude smaller than that of single low barrier diode. The influence of stripes area proportion on device properties was investigated and the barrier height can be adjusted by changing dual-barrier ratio. This new device structure displays a small power dissipation of 0.54 W/cm2, which is a promising technology for high power diamond diodes. [ABSTRACT FROM AUTHOR]

Radio frequency (RF) sputtered ZnO thin-film transistors (ZnO TFTs) with titanium/palladium (Ti/Pd) Schottky source and drain electrodes grown on SiO2/n-Si substrate have been investigated with a compatible fabrication process for different channel thicknesses ranging from 50 to 200 nm as room temperature (RT) hydrogen sensors. Rapid and concentration-dependent (500–4500 ppm) sensor responses (in terms of drain current increase due to the lowering of the Schottky barrier height) with the maximum sensitivity of 72.7% have been achieved excluding the need of heating with relatively fast response/recovery times under RT. Apart from selectivity analysis of the sensors toward methane, acetone, and nitric oxide, structural, optical, mechanical, and electrical characteristics of the devices depending on film thickness are studied. The performance of the sensors in terms of repeatability, time-dependent stability, and under humid ambient conditions has been demonstrated. Hydrogen adsorption kinetics has also been investigated from a thermodynamic analysis. [ABSTRACT FROM AUTHOR]

Capacitively coupled neuromorphic system is very promising for spiking dynamic computing because of the inherent advantages of low static power and large fan-out. Here, flexible multigate indium–gallium–zinc–oxide (IGZO) Schottky thin-film transistors (TFTs) with configurable neuromorphic functions are investigated. The channel layer can be effectively modulated by the multigate terminals through electric-double-layer coupling effect. Plastic modulation of Schottky barrier is also demonstrated, which is highly desirable for dynamic synaptic weight modulation. Furthermore, configurable spiking dynamic functions, such as paired-pulse facilitation (PPF) and high-frequency spike filter, are also emulated in such flexible oxide-based Schottky neuromorphic device. [ABSTRACT FROM AUTHOR]

The low contact resistivity with the median value of 3.1 × 10#8722;9Ω ⋅ cm2 (the lowest value of 1.1 × 10#8722;9Ω ⋅ cm2) is achieved by Ti metal contact to in-situ B-doped GeSn with B segregation at Ti/GeSn:B interface. The newly developed two-sheet-resistance model is used to extract the contact resistivity, considering the different sheet resistance of GeSn:B in the gap regions and under the metal layers. Sn incorporation into Ge lowers the Schottky barrier height of holes, and the heavy B doping at the Ti/GeSn:B interface reduces the hole tunneling distance. Fully compressively strained GeSn:B epitaxial layer with the bulk active [B] of 1.9 × 1020 cm−3 and [Sn] of 4.7% on the Ge-buffered Si substrate is successfully grown by chemical vapor deposition. The effects of B2H6 precursor on growth rate and [Sn] are investigated. Low contact resistivity is obtained using conventional B-doping in GeSn grown at a temperature as low as 305 °C and submitted to a post epitaxy thermal budget of 400 °C for 30 s. [ABSTRACT FROM AUTHOR]

In this article, we report the development of a novel physics-based analytical model for explaining the current–voltage relationship in Schottky barrier (SB) 2-D-material field effect transistors (FETs). The model has at its core the calculation of the surface-potential (SP) which is accomplished by invoking 2-D density of states in conjunction with Fermi–Dirac (FD) distribution for electron and hole statistics. The explicit computation for the SP, carried out using the Lambert-W function together with Halley’s method, is used to construct the SP-based band-diagram for realizing the transparency of the SBs. Thereafter, the ambipolar current is derived in terms of the electron and hole injection phenomena—the thermionic emission and Fowler–Nordheim tunneling mechanisms—at the SB contacts. Furthermore, drift-diffusion current is derived in terms of the SP and incorporated in the model to account for the scattering in the intrinsic 2-D channel. Finally, the Verilog-A model is validated against experimental I-V data reported in the literature for two different 2-D-material systems. This is the first demonstration of an explicit SP-based SPICE model for ambipolar SB-2-D-FETs that is simultaneously built on tunneling-emission and drift-diffusion formalisms. [ABSTRACT FROM AUTHOR]

Schottky-barrier field-effect transistors (SBF-ETs) based on 2-D semiconductors had been investigated as a substitute for a conventional metal–oxide–semiconductor field-effect transistor (MOSFET) based on bulk silicon in the field of high-performance (HP) device. Especially, the monolayer SiC has been studied because it has a large band gap, which results in reducing the short-channel effect. In this article, the gate–source/drain underlap-dependent characteristics of HP SBFETs based on monolayer SiC with 5.1- and 4.6-nm gate lengths are investigated through ab initio simulations. The performances of the 5.1-nm monolayer SiC SBFET are degraded by the gate–source/drain underlap. The gate–source/drain underlap, however, shows the different improved performances for the 4.6-nm monolayer SiC SBFET. The gate–source underlap could enhance the ON-current to 2792~μA/μm and the gate–drain underlap can enhance the ON-current to 1754~μA/μm, which all far exceed the International Technology Roadmap for Semiconductors (ITRS) requirement. [ABSTRACT FROM AUTHOR]

This article presents a finger-type gallium nitride (GaN) Schottky barrier diode (SBD)-based microwave rectifier with medium-power capacity and wide power bandwidth. A complete solution including SBD design and fabrication, model extraction, circuit optimization, and demonstration is proposed. The finger-type anode and critical thickness epitaxial layer techniques are adopted to reduce the GaN SBD resistance to 1.9 Ω (0.011 m Ω ⋅ cm2) and achieve nearly constant junction capacitance over a wide range of voltages (17–25 V). Revised equivalent models including the effects of large pads, critical thickness epitaxial layer, and finger-type layout are proposed to describe the new features of the SBD. A 2.45-GHz microwave rectifier based on the GaN SBD is designed and measured, having a maximum power and an efficiency of 1.91 W and 78.5%, respectively. The high-efficiency power range (≥70% and ≥75%) is significantly extended to 14 and 10.8 dB. Finally, a wireless clinical examination prototype constructed by a rectifier, antennas, biomedical sensors, and a signal processer is proposed for demonstration. The resulting wireless electrocardiogram shown in computer is clear and stable. [ABSTRACT FROM AUTHOR]

The introduction of graphene (Gr) with high thermal conductivity between GaAs and metal electrode can reduce the internal temperature rise and thermal stress accumulation of high-power chips, such as photoconductive switches, protect the contact electrode, and improve the device stability. Meanwhile, the introduction of graphene has the potential to decrease the interface contact resistance. It is valuable to study the effect of graphene on the contact characteristics of the metal–semiconductor interface. The metallic composite Ni/Ge/Au/Ni/Au was obtained by electron beam evaporation, and the graphene was grown by CVD. The current–voltage (${I}$ – ${V}$) characteristics of the devices over a high-temperature range 300 K–420 K were measured by a semiconductor parameter analyzer. The Schottky barrier properties of metal/semi-insulating GaAs (M/SI-GaAs) with and without graphene interlayer were analyzed by some analysis techniques, such as forward ${I}$ – ${V}$ and Norde’s methods. It was observed that the barrier heights (BHs) were inhomogeneous in the high-temperature range. The mean BHs were extracted by the experimental BH versus 1/T. We found that the homogeneous BH of M/Gr/SI-GaAs was lower that of M/SI-GaAs. It is helpful to improve the performance of semiconductor devices, as we realized the specific contact resistivity lower by two orders of magnitudes via graphene insertion. [ABSTRACT FROM AUTHOR]