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The industry standard advanced SPICE model (ASM)-GaN compact model has been enhanced to model the GaN high electron mobility transistors (HEMTs) at extreme temperature conditions. In particular, the temperature dependence of the trapping behavior has been considered and a simplifying approximation in the temperature modeling of the saturation voltage in the ASM-GaN model has been relaxed. The enhanced model has been validated by comparing the simulation results of the model with the dc ${I}$ – ${V}$ measurement results of a GaN HEMT measured with chuck temperatures ranging from 22 °C to 500 °C. A detailed description of the modeling approach is presented. The new formulation of the ASM-GaN compact model can be used to simulate the circuits designed for extreme temperature environments.

In this article, the gate current in AlGaN/GaN high-electron mobility transistors is modeled in a surface potential-based compact model. The thermionic emission, the Poole–Frenkel emission, and the Fowler–Nordheim tunneling are the dominant mechanisms for the gate current in the forward- and reverse-bias regions. These conduction mechanisms are modeled within the framework of the ASM-GaN compact model, which is a physics-based industry-standard model for GaN HEMTs, hence yielding a consistent model for the drain and gate currents. The proposed model captures the gate voltage, drain voltage, temperature, and gate-length dependencies of the gate current. The results of dc gate-leakage measurements of two GaN HEMT, differing only in terms of gate length, over a wide range of temperature, showing these current-conduction mechanisms, are presented, and the proposed model is validated accordingly. The developed gate current model, implemented in Verilog-A, is in excellent agreement with the experimental data.

Because of charge trapping in GaN HEMTs, dc characteristics of these devices are not representative of high-frequency operation. The advanced spice model GaN model presented in Part I of this paper is combined with a Shockley–Reed–Hall-based trap model, yielding a comprehensive FET model for GaN HEMTs which can accurately model GaN devices exhibiting trapping-related dispersion effects. Measurement results of the dc and pulsed output and transfer characteristics of a commercially available GaN HEMT are presented, trapping in the device is modeled, and excellent fit to the measured data is shown. This paper presents an accurate model of trapping which is validated for eight different quiescent bias points of pulse measurements, with quiescent drain voltage ranging from 5 to 20 V and quiescent gate voltage ranging from −2.8 to −3.8 V, and a large range of gate and drain voltages to which the device was pulsed in the pulse measurements and at which the device was measured in the dc measurements, with gate voltage ranging from −4 to 0.4 V and drain voltage ranging from 0 to 40 V. This paper also presents high-frequency (10 GHz) large-signal RF validation of the model for optimal complex load condition.

Measurement results performed on a GaN high-electron-mobility transistor that show the presence of a double-energy-level (DEL) trap center in the device are presented. A novel, yet simple, circuit implementation of a DEL trap center in an FET is presented that is immediately extendableto a trap centerwithmore than two energy levels. The model is based on the Shockley–Read–Hall statistics of the trapping process. The implementation is suitable for both time-domain and harmonic-balance simulations. Simulation results validate the proposed model.

The temperature response of field-effect transistors (FETs) to instantaneous power dissipation has been shown to be significant at high frequencies, even though the self-heating process has a very slow time constant. This affects intermodulation at high frequencies. A major difficulty in characterizing the self-heating process in microwave FETs is to differentiate between the self-heating and charge-trapping rates. An iso-trapping measurement technique is proposed by which it becomes possible to characterize the self-heating process in an FET in isolation from the effect of the charge-trapping process in the FET. The results of iso-trapping measurements performed on a GaN high-electron-mobility transistor are presented, and used to successfully characterize the self-heating process.

The results of measurements performed on a GaN high electron-mobility transistor (HEMT) by two different pulse-measurement techniques are presented. By performing two-stage pulse measurements, two distinct current-injection mechanisms responsible for triggering the trapping process are identified. By performing three-stage pulse measurements, the trap center at which the trapping process occurs is identified to be a double-energy-level trap center, which is a trap center with two distinct energy levels between which there is an interaction. This result has a significant impact on the design of more accurate large signal models for GaN HEMTs.