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In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero-V-load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this paper, the analytical models for delay and power were developed for zero-V-load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero-V-load logic circuits.

In this paper, all-solution-processed low-voltage organic thin-film transistor inverters on polyethylene naphthalate plastic substrate were achieved in the bottom-gate bottom-contact device configuration. In the devices, 6,13-bis(triisopropylsilylethynyl)-pentacene blended with polystyrene was used as the channel layer, and ultraviolet cross-linked polyvinyl alcohol was used as the gate dielectric layer. With optimized inkjet jetting process parameters and a proper polymer dielectric substrate surface, fine silver electrodes were formed as the source, drain, and gate electrodes. The maximum processing temperature was 150°C. The devices show promising performance with a mobility of 0.8 cm2/(V·s), a subthreshold swing of 100 mV/decade and an ON/OFF ratio of about 104. The fabricated diode-load inverter has a high dc voltage gain up to 67.3 at a supply voltage of 3 V.

The noise margin (NM) of an inverter is an important feature for the operation stability of the digital circuits. Owing to their simple structure, easy processes, and relatively high gain, the unipolar zero-VGS-load logic design is widely used for implementation of digital circuits in various thin-film transistor (TFT) technologies. In this paper, a simple NM model clarifying the relationship between the NM and electrical/device parameters is developed for the zero-VGS-load inverter. The model is verified by circuit simulations, and is capable of providing a useful guideline for optimal design of unipolar TFT logic circuits. Finally, the application of the derived model in a static random access memory cell design is discussed.