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A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but also a sector-erase operation are successfully achieved with only a small cell-size increase over the conventional NOR cell. Moreover, this cell technology maintains all the advantages of the P-channel DIvided-bit-line NOR (DINOR) flash memory.

The P-channel DINOR flash memory, which uses the band-to-band tunneling induced hot electron (BBHE) program method having the advantages of high scalability, high efficiency, and high oxide reliability, was fabricated by 0.35-/spl mu/m-rule CMOS process and was investigated in detail. An ultra-high programming throughput of less than 8 ns/byte (=4 /spl mu/s/512 byte) and a low current consumption of less than 250 /spl mu/A were achieved by utilizing 512-byte parallel programming. Furthermore, we investigated its endurance characteristics up to 10/sup 6/ program/erase cycles, and window narrowing and G/sub m/ degradation were found to be very small even after 10/sup 6/ cycles. It is thought that the BBHE injection point contributes to the G/sub m/ stability and the oxide-damage-reduced operation contributes to the good window narrowing characteristics. The P-channel DINOR flash memory realizing high programming throughput with low power consumption is one of the strongest candidates for the next generation of high-performance, low-voltage flash memories.

It is found, even at room temperature, that hole fluence to breakdown Q/sub p/ of wet oxides is not a constant value for different oxide fields, but has a strong stress-electric-field dependence. Based on the neutral trap-generation characteristics related to SILC, this oxide-breakdown behavior dependent on the stress-electric field is analyzed. A novel model is proposed in which oxide breakdown is triggered when the current level of steady-state SILC via electron tunneling between traps reaches a critical value. From the spatial distribution of traps, we have concentrated on the critical trap pair whose electron-tunneling probability has the smallest value in the middle of the SiO/sub 2/ films. To verify this model, the convoluted trap density which is related to the electron-tunneling probability between the critical trap pair is investigated. As a result, it is found that this convoluted trap density remains constant regardless of stress-electric field and oxide thickness. This means that this convoluted trap density is a universal parameter for oxide breakdown.

Time-decay stress-induced leakage current (SILC) has been systematically investigated for the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress. From the three viewpoints of the reproducibility of the-current component for the gate voltage scan, the change of oxide charge during the gate voltage scan, and the resistance of the current component to thermal annealing, it has been found that time-decay stress-induced leakage current is composed of five current components, regardless of stress type. Trap models corresponding to each current component have been proposed. In addition, it has also been proven that holes generate the electron traps related to one of those current components.

In the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress, three reproducible stress-induced leakage current (SILC) components have been found for the repeated unipolar gate-voltage scans in 9.2 nm wet oxides. To clarify the mechanisms of these current components, a quantitative analysis has been developed. By precisely modeling the phonon assisted tunneling process, it has been shown that the E-J and t-J characteristics of the reproducible current components can be completely simulated as electron tunneling processes into the neutral traps, each with a single trap level. From this analysis, the physical parameters of the traps have been estimated with a reasonable degree of accuracy. Furthermore, the increase in distribution of the neutral trap density toward both the SiO/sub 2/ interfaces has also been estimated.

Time-decay stress-induced leakage current (SILC) has been systematically investigated for the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress. From the three viewpoints of the reproducibility of the current component for the gate voltage scan, the change of oxide charge during the gate voltage scan, and the resistance of the current component to thermal annealing, it has been found that time-decay stress-induced leakage current is composed of five current components, regardless of stress type. Trap models corresponding to each current component have been proposed. In addition, it has also been proven that holes generate the electron traps related to one of those current components.

Using a newly proposed method for estimating the neutral trap density, generation characteristics of the neutral trap during various stress types have been investigated. From the analysis of the trap-generation kinetics, two types of trap generation closely related to holes have been identified. At the first stage of stress application, holes interact with the pre-existing structural origins of the neutral traps, then the neutral traps are generated. Influence of hole energy on this type of trap generation is also identified. After that, as holes pass, they also create the structural origins of the traps. The holes interact with these structural origins and the neutral traps are generated as a secondary effect. Thus, the increase in the neutral trap density shows up clearly with increase in the hole fluence. The stress-strength dependence of the increase in the neutral trap density can also be interpreted in terms of the influence of hole energy on the trap generation.