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A first principle analysis of Fe/MgO/Fe magnetic tunnel junction (MTJ) having gate voltage over insulated barrier region (MgO) is presented. Because of different work functions of gate and barrier materials, transfer of density of states (DOS) in forbidden energy gap of MgO is found above Fermi energy due to Schottky effect. It is reported that diffused DOS allows high tunneling of majority channel current because of less interference of ${\Delta _{{1}}}$ symmetry of Bloch states with evanescent states in barrier. It shows high spin injection efficiency 0.9928, 0.9959, and 0.9871 with tunnel magneto resistance (TMR) ratios 1743.30%, 1450.06%, and 572.62% at gate voltages 1–3 V, respectively, with left and right electrodes at 0.5 V. Present work gives a basis for using MTJs as three terminal devices in magnetic random access memory (MRAM) applications. [ABSTRACT FROM AUTHOR]

The parameters for a kilowatt-level high-power terahertz amplifier were explored based on the higher-order mode and extended-interaction mechanism. It has been demonstrated that the antisymmetric electrical field mode (TM21) has a unique advantage in achieving high power. Physical factors on power extraction were studied. In particular, the heavily reduced ${Q}_{{0}}$ has a great effect on the coupling characteristic as well as the output power. It is found that the critical coupling state, i.e., ${Q}_{e} = {Q}_{{0}}$ , defines an upper limit of the power that can be extracted from the output circuit. The design of a complete interaction circuit was accomplished. The particle-in-cell (PIC) simulations showed that a saturated power of 1.2 kW can be achieved at 220 GHz with a voltage of 45 kV and a total current of $2\times0.6$ A where two beams were used. The saturated gain is over 30 dB with a 3-dB bandwidth of $\sim 400$ MHz. [ABSTRACT FROM AUTHOR]

A magnetic tunneling junction (MTJ) with very low energy barrier, which shows controllable stochastic property, is recently proposed to constitute the probability bit (P-Bit). With the P-Bit, Ising computation, which is a general and powerful computing platform for both conventional and non-conventional problems, is implemented. However, such hardware emulation suffers from the severe intrinsic variations of a stochastic MTJ device. The nonuniform probability switching curves of different stochastic MTJs hinder straightforward expansion of Ising computer to a large P-Bits array for solving more complicated problems. In this work, we propose a novel Ising computer using a single stochastic MTJ device. With the utilization of the time-division multiplexing (TDM) technology, a “Compute–Read–Switch” scheme is proposed, so that the single stochastic MTJ can act as multiple P-Bits during Ising computation. A design guide for the current magnitude and time duration of the “Compute–Read–Switch” scheme is investigated and provided. Furthermore, NOT and XOR logic gates are implemented with our proposal. An accuracy rate as high as 69% for the integer factorization is also achieved, which is comparable with conventional Ising computer. Meanwhile, the TDM Ising computer avoids the calibration process, which is mandatory in the conventional Ising computer. [ABSTRACT FROM AUTHOR]

The two-stage (TS) multibeam klystron (MBK) technology has recently attracted significant research attention due to its compactness and high-efficiency (HE) performance. However, there is still a lack of scientific research on the beam optics for such microwave power sources integrated with a postacceleration (PA) gap. In this article, a comprehensive optics study based on the newly developed 2-D optics code CGUN is conducted for the first time to demonstrate the most critical steps in the optics design process, by adopting the 400-MHz TS MBK for the future circular collider (FCC) as an example. Two specific challenges arise in this TS MBK, which are studied in this article, and solutions are given. First, due to the combination of slow electrons, impedance change from individual beamtubes into common volume, and the mild decay of the magnetic field, there are possible reflected electrons at the collector entrance. This requires an increase in the beam voltage to 80 kV, beyond the requirements from considering the output gap alone, as well as tighter control on bouncing electrons. The beam scalloping is also found to be highly sensitive to the position of the PA gap and magnetic field, which later demonstrates that large gap length and magnetic field are required. Final all-in-one particle-in-cell (PIC) simulations of this klystron equipped with this special optics design demonstrate that the specification of 1.2-MW continuous wave (CW) power is practically attainable with an efficiency of 77.5% and without the presence of reflected electrons at any point in the whole circuit. [ABSTRACT FROM AUTHOR]

In several recent studies, the probabilistic nature of magnetic tunnel junction (MTJ) switching has been utilized rather than suppressed for proposals and demonstrations of specific or novel scenarios or applications, such as true random number generation, neural spike generation, stochastic computing (SC), and probabilistic spin logic. Among all schemes of operations for generating tunable random signals, dual-biasing is very simple but also robust against device variations. When an MTJ is connected to a voltage source with polarity encouraging parallel (P)-to-antiparallel (AP) switching by spin-transfer torque (STT), and under a static bias field that favors P-state, the MTJ can switch back and forth between two states randomly, due to the state-dependent modulation of current by the tunneling magnetoresistance (TMR) of the MTJ. In this work, we demonstrate bipolar random signal generation by connecting two MTJs in series with a voltage source. [ABSTRACT FROM AUTHOR]

This article proposes novel nonvolatile (NV) static random access memory (SRAM) circuits based on spin transfer torque (STT) and spin orbit torque (SOT) operated magnetic tunnel junction (MTJ) device for energy-efficient power gating circuits. In which, two different designs of 9T-2MTJs and 10T-2MTJ-based NV SRAM circuits are proposed for low power, high noise margin, and faster switching speed with less area overhead. The proposed architecture uses a smaller number of transistor combinations to accommodate low-power operation with compact cell size when compared with available pieces of literature. Also, the combination of nMOS and pMOS transistors in the proposed architecture enhances the driving capability of the circuit for both low and high input operations. Here, the electrical characteristics of the proposed designs have been compared and contrasted with the available 11T-2MTJ and 7T-2D-2MTJ non volatile static random access memory (NVSRAM) and 6T SRAM circuits using a UMC-40 nm design kit and physics-based STT–SOT MTJ Verilog-A Model. The proposed 9T-2MTJ-based NVSRAM was found to be a better alternative and offers improved performance in terms of higher restore noise margin and lower power consumption than other circuits reported at this node. Moreover, the studied 10T-2MTJ exhibits an improved write and hold noise margin than the proposed/available 9T/7T-2D/11T-2MTJ circuits. [ABSTRACT FROM AUTHOR]

A back-end-of-line compatible 400 °C thermally robust perpendicular spin-orbit torque magnetic tunnel junction (p-SOT-MTJ) memory cell with a tunnel magnetoresistance ratio of 130% is demonstrated. It features an energy-efficient spin-transfer-torque-assisted field-free spin-orbit torque (SOT) switching and a novel interface-enhanced synthetic antiferromagnet (SAF). The optimal SAF with a Ru (9 Å) spacer sandwiched by Co/Pt multilayers has a high SAF coupling field of 2.8 kOe. The parallel magnetic coupling between the CoFeB-based reference layer and the bottom Co/Pt multilayer is enhanced by a magnet-coupling face-centered cubic textured Co/Pt (5 Å) multilayer buffer. The thermally induced Pt–Fe interdiffusion is effectively reduced by the W (3 Å) trilayers of texture-decoupling diffusion multibarrier. The Ta/ $\beta $ -W and TaN/ $\beta $ -W composite SOT channels are thick enough to be the etching stop and sustain 400 °C annealing without transforming to $\alpha $ -W. Using the harmonic Hall voltage measurement, the Ta/W and TaN/W channels exhibit the large effective spin Hall angle of approximately −0.21 and −0.27, respectively. Scaling magnetic tunnel junction (MTJ) down to 30 nm size can reduce the switching time due to single-domain switching based on the micromagnetic simulation. The damping constant of ~0.018 is obtained by the ferromagnetic resonance measurement. A bigger damping constant reduces the switching time as predicted by the calibrated simulation. [ABSTRACT FROM AUTHOR]

An effective overmoded circuit is proposed to support efficient interaction with two beams for the development of high power extended interaction oscillators (EIOs) toward sub-terahertz (THz) and higher frequency. The circuit design focuses on the effect of the frequency-determining parameter on mode characteristics of the $\mathrm{TM}_{{1} {n}}$ sequence. Frequency equivalence between $\mathrm{TM}_{{1} {n}}$ modes with different ${n}$ supports the mode selection for two-beam interaction. Accordingly, the TM13 mode is selected to duplicate the dispersion relation around the axial mode of $2\pi $ and ohmic loss of conventional TM11 mode used in conventional single-beam circuits. On this basis, the overmoded circuit is formed with two beams based on the TM13 mode. In order to verify its effectiveness, a 0.22-THz EIO is designed with the overmoded circuit and, most importantly, the effect of the uniformity of two beams on the EIO performance is simulated. When the current of one beam is assumed to be constant and that of another beam is increased, the power is increased linearly and then tends to be saturation. This shows good capability of the EIO in interacting with nonuniform two beams, which is critical for its stable operation. Simulation results have shown the achievement of the average power of 0.22-THz wave over 1.26 kW with double beams at 23 kV and each current of 0.2 A. [ABSTRACT FROM AUTHOR]

In order to enhance the power capacity of gyro-traveling wave tube (Gyro-TWT), a novel multisectorial-tunnel circuit is presented in this article. The multisectorial tunnel could extend the transverse dimension of RF circuit for higher power electron beam transportation. The azimuthal drifting and transportation distortion performance for rotated electron beam are analyzed. A multibeam magnetron injection gun (MIG) is designed. The electron beam with pitch factor of 1.09 and axial velocity spread of 3.5% is obtained. And the designed cathode was fabricated and temperature distribution was measured. It provides a possible method to enhance the power capacity of Gyro-TWT. [ABSTRACT FROM AUTHOR]

Binary neural networks (BNNs) are promising for resource-constrained Internet of Things (IoT) devices owing to the lightweight memory and computation requirements. Moreover, BNNs based on computing-in-memory (CIM) architectures have attracted much attention in both algorithm and hardware designs. Recently, a variety of CIM-based BNN hardware designs has been proposed, particularly based on emerging nonvolatile memories (NVMs), which have merits in terms of nonvolatility and intrinsic resistance-based computing capabilities. However, mainstream NVMs utilize the one transistor plus one memory device (1T1M) cell structure, limiting the computing efficiency and throughput. In this article, we propose a high-throughput CIM architecture for BNN hardware based on a voltage-controlled spin–orbit torque (VC-SOT) memory device, which enables parallel programming and computing operations thanks to its specific cell structure. In VC-SOT devices, multiple magnetic tunnel junctions (MTJs) are stacked on a heavy metal and share the same SOT write current. Furthermore, computing can be achieved based on the normal memory-like write and read operations. Based on a physics-based VC-SOT MTJ model, we designed and evaluated the proposed CIM-based key BNN hardware in the 40-nm technology node. Our simulation results validated the parallel programming/computing functionality and illustrated the performance in terms of power consumption (~4 fJ/bit) and speed (~2 ns/write, 0.36–1.5 ns/read). [ABSTRACT FROM AUTHOR]

This article presents a multilevel design for spin–orbit torque (SOT)-assisted spin-transfer torque (STT)-based 4-bit magnetic random access memory (MRAM). Multilevel cell (MLC) design is an effective solution to increase the storage capacity of MRAM. The conventional SOT-MRAMs enable an energy-efficient, fast, and reliable write operation. However, unlike STT-MRAM, these cells take more area and require two access transistors per cell. This poses significant challenges in the use of SOT-MRAMs for high-density memory applications. To address these issues, we propose an MLC that can store 4 bits and requires only three access transistors. The effective area per bit of the proposed cell is nearly 58% lower than that of the conventional 1-bit SOT-MRAM cell. The combined effect of SOT and STT has been incorporated to design SOT-STT-based MLC that enables more energy-efficient and faster write operation than the regular MLCs. The results show that SOT–STT-based 4-bit MLC is 52.9% and 40% more efficient in terms of latency and energy consumption, respectively, when compared to 3-bit SOT-/STT-based MLC. [ABSTRACT FROM AUTHOR]

The focusing and transmission of a sheet electron beam with periodic cusped magnetic (PCM) fields were studied for the terahertz traveling-wave tubes (TWT). Due to the limitation on the width of the sheet beam from the slow wave structure (SWS), the resulting transmission current density is inevitably high and the width of the sheet beam is highly disproportionate to the magnet system. This defines a situation different from before, which challenges the validity of the traditional PCM scheme. Thus, the focusing of a sheet beam in the above scenario was theoretically analyzed to evaluate the focusing conditions. A practical magnetic field system was then designed based on the offset-pole-piece PCM scheme with the shortened pole pieces, which can meet the focusing requirements, especially on the side focusing. The theoretical analysis and the modified PCM scheme lead to a significant improvement in the focusing/transmission of the sheet beam. The 3-D particle simulation showed that a stable long-distance transmission over 100 mm can be achieved with the two-plane PCM focusing where an elliptical-cross section sheet beam is assumed with dimensions of 0.6 mm × 0.11 mm, voltage of 24.5 kV, and current of 0.18 A. [ABSTRACT FROM AUTHOR]

We successfully developed 25-nm quad CoFeB/MgO-interfaces perpendicular magnetic tunnel junction (quad-MTJ) with enough thermal stability. To fabricate the quad-MTJ, a physical vapor deposition (PVD) process for depositing novel free layer and low resistance-area (RA) product MgO layer and low-damage fabrication processes were developed. The developed quad-MTJ technology and advanced process bring better tunnel magneto resistance (TMR) ratio and RA to quad-MTJ than those of double-interface MTJ (double-MTJ), even though quad-MTJ has an additional MgO layer. Scaling down the MTJ size to 25 nm, we demonstrated the advantages of quad-MTJ compared with double-MTJ as follows: 1) two times larger thermal stability factor (Δ), which results in over ten years retention; 2) superiority of large Δ in the measuring temperature range up to 200 °C; 3) ~1.5 times higher write efficiency; 4) lower write current at short write pulse regions at less than 100 ns; and e) excellent endurance of over 1011 thanks to higher write efficiency, which results from the reduced voltage owing to low RA and the low damage integration process technology. As a result, the developed quad-MTJ technologies will open the way for the realization of high-density STT-MRAM with low power, high speed, high reliability, and excellent scalability down to 2 × nm node. [ABSTRACT FROM AUTHOR]

For extended interaction structure devices (EIDs), the determinants of field flatness are analyzed. It is found that the flatness of field distribution is determined by a cutoff condition existing in EIDs, which is based on the concepts of both resonant cavity and wave propagation. Such an analytical conclusion is verified by a novel scheme for the measurement of field distribution in an extended interaction oscillator (EIO) based on the perturbation technique. The sinusoidal-like axial field components with different flatness are obtained by utilizing the measured frequency shifts. Based on the cutoff condition, three field distribution patterns are established, including middle-concentrated, flat-distributed, and side-concentrated types. Particle-in-cell (PIC) simulations of a W-band EIO show that three field distribution patterns have the advantages of low surface-loss power, high power-capacity, and low oscillating-threshold, respectively. [ABSTRACT FROM AUTHOR]

Spin logic devices based on domain wall (DW) motion offer flexible architectures to store and carry logic information in a circuit. In this device concept, information is encoded in the magnetic state of a magnetic track shared by multiple magnetic tunnel junctions (MTJs) and is processed by DW motion. Here, we demonstrate that all-electrical control of such nanoscale DW-based logic devices can be realized using a novel MTJ stack. In addition to field-driven motion, which is isotropic, we show the directional motion of DWs driven by current, a key requirement for logic operation. Full electrical control of an AND logic gate using DW motion is demonstrated. Our devices are fabricated in imec’s 300-mm CMOS fab on full wafers, which clears the path for large-scale integration. This proof of concept, thus, offers potential solutions for high-performance and low-power DW-based devices for logic and neuromorphic applications. [ABSTRACT FROM AUTHOR]

The traditional von Neumann computing architecture based on metal-oxide field-effect-transistors (MOSFETs) is more and more incompetent for the increasing demand for computing speed and energy efficiency in the Internet of Things (IoT) and intelligent development. Carbon nanotube field-effect-transistors (CNTFETs) are expected to achieve significant energy efficiency benefits versus today’s silicon-based FETs. In this article, we combine CNTFETs and spin-transfer torque magnetic tunneling junctions (STT-MTJs) to build near-memory computing circuits, whose high speed and low power consumption characteristics are shown through the investigation of three nonvolatile logic gates: The read speed of CNTFET/STT-MTJ nonvolatile logic circuit is approximately 40% of the MOSFET/ STT-MTJ analog circuit, and the total power consumption and read energy of the same logic circuit can be approximately saved 17%–37% compared with that of MOSFET/ STT-MTJ analog circuit. Our research shows the advantages of the integration of CNTFETs and STT-MTJs in the nonvolatile logic circuit, which has great significance for the development of beyond-complementary metal-oxide semiconductor (CMOS) electronics. [ABSTRACT FROM AUTHOR]

Spin-Torque-Transfer Magnetic Tunnel Junction (STT-MTJ) device shows wide applications in many important scenarios, including magnetic random access memory (MRAM), logic design, and high-frequency application. Its characterizations at the high frequency are studied intensively recently. In this article, the high-frequency properties of the STT-MTJ device are investigated thoroughly, including a de-embedding approach followed by an extraction procedure for removing the influences from the environment and the package. The de-embedding approach is performed on the STT-MTJ device operated at a high frequency, which can be used to calibrate its electrical characteristics by eliminating the environmental influence. After the calibration, the equivalent circuit for the MTJ device at high frequency can be set up, followed by the extraction procedure of the parasitic parameters of the high-frequency-equivalent-circuit. Combined with the extracted parameters, the equivalent circuit can be used for the simulation work with the MTJ device involved in the high-frequency operation. [ABSTRACT FROM AUTHOR]

We fabricated a quadruple-interface perpendicular magnetic tunnel junction (MTJ) (Quad-MTJ) down to 33 nm using physical vapor-deposition, reactive ion etching, and damage-control integration process technologies that we developed under a 300-mm process. We demonstrated the greater scalability and higher writing speed of Quad-MTJ compared with double-interface perpendicular MTJ: 1) it has twice the thermal stability factor—1X nm Quad-MTJ can achieve 10 years retention—while maintaining a low resistance-area product and high tunnel magnetoresistance ratio; 2) smaller overdrive ratio of write voltage to obtain a sufficiently low write-error rate; 2) smaller pulsewidth dependence of the switching current; and 4) more than double the write efficiency at 10-ns write operation down to 33-nm MTJ. The effective suppression of the switching current increase for higher write speeds was explained by the spin-transfer-torque model using the Fokker-Planck equation. Our 33-nm Quad-MTJ also achieved excellent endurance (at least 1011) owing to its higher write efficiency and low-damage integration-process technology. It is thus a promising method for low power, high speed, and reliable STT-MRAM with excellent scalability down to the 1X nm node. [ABSTRACT FROM AUTHOR]

Compactness and cost-effectiveness are two major concerns in the development of a Ka-band linearizer, which is a crucial accelerator component of the European CompactLight project. A higher order mode (HOM) multibeam Klystron (MBK) could accommodate a higher distributed electron current with a low operating voltage of 60 kV, thus making it competitive to deliver high RF power at high frequency compared with a single beam Klystron or a fundamental mode MBK. In this article, the modeling and design study of the 36-GHz HOM MBK is presented. The development of a double compression multibeam (MB) optics system is also elaborated in this article. The performance validation of such a device was done using sophisticated 3-D particle-in-cell (PIC) computer simulations of the entire device. PIC simulations confirmed that a power level of 2.5 MW is attainable with an efficiency of 35%. [ABSTRACT FROM AUTHOR]

Due to the complexity of device processing, the trade-off between yield and area has resulted in diminishing rate of scaling for the high-density static random access memory (SRAM) cell at advanced CMOS nodes. An introduction of extreme ultraviolet (EUV) and multipatterning has added additional cost to technology in order to realize 3-D device structure and ultrascaled metal routing. In this era, spin-transfer torque (STT)-MRAM technology can provide an alternative to high-density SRAM and for the last level cache (LLC) applications. In this article, we discuss the memory design and technology tradeoff to enable the STT-MRAM as a viable option. We have realized the technology over 300-mm wafer, measuring 1 million samples to build a SPICE model for circuit simulation. Occupying up to 83.3% of an area that of SRAM macro has been designed and simulated for the scaled 5-nm CMOS node. The simulated MRAM macro shows the best read and write access time of 3.1 and 6.2 ns, respectively. Magnetic tunneling junction (MTJ) pillar of 38-nm diameter is realized at 90-nm pitch, measuring resistance area (RA) of 5.2-Ω ⋅ μm2, Jsw of 5.5 MA/cm2 with improved Δ avg of 70, and breakdown voltage of 0.99 V. The energy comparison shows increasing gains versus SRAM for the increasing cache sizes crossing over at of 0.3 and 4 MB for the single-cycle read and write operations, respectively. [ABSTRACT FROM AUTHOR]

One method of creating and annihilating skyrmions in confined geometries is to use voltage-controlled magnetic anisotropy (VCMA). The previous study shows that robust voltage-controlled ferromagnetic reversal from “up” to “down” state in the soft layer of a perpendicular magnetic tunnel junction (p-MTJ) can be achieved by creating and subsequently annihilating an intermediate skyrmion state in the presence of room temperature thermal noise and anisotropy variation across grains. However, when scaling to 20 nm, thermal noise can annihilate the skyrmions, for example, by randomly moving the core toward the boundary of the nanostructure. In this work, we study three p-MTJs of different dimensions, specifically lateral dimensions of 100, 50, and 20 nm and investigate the change in switching behavior as the dimension is decreased. In particular, we show that while skyrmion-mediated switching of ferromagnets in the presence of thermal perturbation is feasible down to lateral dimensions ~20 nm, the large values of VCMA and Dzyaloshinskii–Moriya interaction (DMI) needed at ~20 nm lateral dimensions have only been theoretically predicted and are yet to be experimentally demonstrated to date. [ABSTRACT FROM AUTHOR]

The Ka-band extended interaction klystrons (EIK) have been developed at the Institute of Electronics, Chinese Academy of Sciences (IECAS), to satisfy the requirement for the high-power millimeter-wave sources in scientific researches. In this work, two kinds of high compression electron gun with the solid or hollow beams, the derivative electron optics systems using the compact permanent magnet uniform focusing and the shared efficient interaction circuit based on the multigap ladder cavity, have been studied in detail and well designed through a mass of calculations. After the mechanical design, finely manufacturing, and a series of technical processes, the Ka-band EIK prototype tubes have been successfully built and tested. For the solid beam scheme, the maximum output power achieves 20 kW in the bandwidth of 60 MHz, and, correspondingly, the gain of 53 dB and the efficiency of 24% are observed. The measured −1 and −3 dB bandwidths are about 220 and 350 MHz, respectively. Meanwhile, the beam transmission is excellent, that is over 97% in dc state and over 90% in RF operation. For the hollow beam case, an over 91% dc transmission test has finished. [ABSTRACT FROM AUTHOR]

We present, for the first time, a VerilogA compact model for an all-optically switchable magnetic tunnel junction (MTJ) using results of all-optical-switching (AOS) simulations. Our model is compatible with electronics and photonics design automation tools, and was tested using Cadence Specter and Virtuoso. This compact model can be used to design circuits and systems combining MTJs, photonic circuits, and electronic circuits giving the possibility to researchers working within this field to develop novel circuits and systems. [ABSTRACT FROM AUTHOR]

Recent progress has demonstrated that current-induced domain wall motion (CIDWM) is able to achieve efficient and ultrafast magnetic switching in the case of spin–orbit torque (SOT) and Dzyaloshinskii–Moriya interaction (DMI). CIDWM-based devices are taken as promising candidates for the next-generation nonvolatile artificial neurons and synapses due to its excellent programmability, fast operation speed, low write power, and so on. In this article, we present a physics-based model of CIDWM magnetic tunnel junction (MTJ), which exhibits high performance based on experimental results. The proposed model integrates the CIDWM dynamics and nanowire MTJ resistance, showing great agreement with extensive physical simulation. A learning circuit based on CIDWM-MTJ, as a hybrid MTJ/CMOS circuit example, has been designed and simulated to validate its functionality. The proposed SPICE-compatible compact model will be useful for high-performance circuit and system evaluation and is expected to promote the research and development of CIDWM-based spintronics devices. [ABSTRACT FROM AUTHOR]

This article proposes two different magnetic nonvolatile-static random access memory (MNV-SRAM) cell circuits for low-power, high-speed, and high-reliable backup operation with a compact cell area. They employ perpendicular magnetic tunnel junctions (p-MTJs) as nonvolatile backup storage elements and explore the spin–orbit torque (SOT) with the assistance of the voltage-controlled magnetic anisotropy effect (VCMA), referred to voltage-gated SOT (VGSOT), to perform the backup operation. By using an antiferromagnetic (AFM) layer that provides both an exchange bias and the SOT, no external magnetic field is required, making it suitable for practical applications. In addition, owing to the aid of the VCMA effect, the critical SOT write current (ISOT) for 1-ns backup operation can be reduced significantly, thus resulting in high speed, low power consumption, and high reliability. Moreover, such resulted ISOT allows to be driven by the cross-coupled inverters in the SRAM cell, instead of a dedicated write driver, thereby leading to low cell area overhead. By using a commercial CMOS 40-nm design kit and a physics-based VGSOT-MTJ model, we have demonstrated their functionalities and evaluated their performance. Compared with previous SOT-based MNV-SRAM cell circuits, the proposed MNV-SRAM cell circuits can achieve lower backup energy dissipation, smaller backup delay, lower backup error rate and less cell area overhead without the assistance of the external magnetic field. [ABSTRACT FROM AUTHOR]

Magnetoresistive random access memory (MRAM) is regarded as a reliable persistent memory technology because of its long data retention and robust endurance. Initial MRAM products utilized toggle mode writing of a balanced synthetic antiferromagnet (SAF) free layer to overcome problems with half-selected bits that challenged traditional Stoner–Wohlfarth switching. With the development of spin transfer torque (STT) switching in perpendicular magnetic tunnel junctions, the capability for scaling MRAM products increased markedly, enabling a 1-Gb device in 2019. Ongoing research will allow scaling to even higher capacities. Compared to traditional memories, STT-MRAM can save power, improve performance, and enhance system data integrity, which supports the growing computing demands for everything from data centers to Internet of Things (IoT) devices. This article provides a review of the technology that enabled present toggle and STT-MRAM products, future STT-MRAM products, and new MRAM technologies beyond STT. [ABSTRACT FROM AUTHOR]

We have proposed a novel quad-interface magnetic tunnel junction (MTJ) technology which brings forth an increase of both thermal stability factor Δ and switching efficiency defined as the ratio of Δ to intrinsic critical current IC0 (Δ/IC0) by a factor of 1.5–2 compared with the conventional double-interface MTJ technology. The free layer of the developed quad interface consists of bottom-MgO/FL1/middle-MgO/FL2/top-MgO stack structure. We successfully fabricated the quad-interface MTJ using a 300-mm process based on a novel low-damage integration process including physical vapor deposition (PVD), reactive ion etching (RIE), and so on. By developing the quad-interface MTJ, we have achieved about two times larger Δ and Δ/IC0 at the same time. Moreover, we have achieved about two times larger tunnel magnetoresistance (TMR) ratio at the same resistance area (RA) product by developing the FL1, bottom-MgO, and middle-MgO. The developed quad-interface MTJ technology considered as post-double-interface MTJ technology will become an essential technology for the scaling of the spin-transfer-torque magnetoresistive random access memory (STT-MRAM) beyond 20 nm. [ABSTRACT FROM AUTHOR]

Probabilistic machine learning enabled by the Bayesian formulation has recently gained significant attention in the domain of automated reasoning and decision-making. While impressive strides have been recently made to scale up the performance of deep Bayesian neural networks, they have been primarily standalone software efforts without any regard to the underlying hardware implementation. In this article, we propose an “all-spin” Bayesian neural network where the underlying spintronic hardware provides a better match to the Bayesian computing models. To the best of our knowledge, this is the first exploration of a Bayesian neural hardware accelerator enabled by emerging post-CMOS technologies. We develop an experimentally calibrated device-circuit-algorithm cosimulation framework and demonstrate 24× reduction in energy consumption against an iso-network CMOS baseline implementation. [ABSTRACT FROM AUTHOR]

High switching speed, endurance, and low-current-based perpendicular magnetic tunnel junction (p-MTJ) memory is attracting wide interest as a key promising candidate for next-generation spintronic memory technology. p-MTJ-based spin-transfer torque RAM (STT-RAM) has been extensively investigated, and despite the promise, there is concern about the high switching current density and low stability with regard to scaling. In this work, the current controllability of p-MTJ in iron (Fe)-enriched Co20Fe60B20 with a newly designed MgOxN1–x tunnel layer is systematically investigated, with the expectation that the introduction of N minimizes the oxidation of Fe to improve the performance of the device. A facile, plasma-based oxynitridation (MgOx = 0.57N1–x=0.43) of MgO through RF-sputter deposition serves as a reliable procedure to establish a tunnel barrier for an MTJ structure fabricated with ~300-nm diameter and pinned with synthetic antiferromagnetic (SAF) [Co/Pt]n multilayer stack. Current-controlled tunneling magnetoresistance (TMR) up to ~65% was observed at room temperature (RT) with ultralow switching current density (Jc) of 136 ± 17 kA/cm2. TMR along with tunnel conductance (g(V)) was measured to be highly stable in the read-bias regime (−200 to +200 mV) for MgOxN1–x as compared to the reported MgO barrier. The analogous MgOxN1–x-based MTJ structures were modeled using the nonequilibrium Green’s function (NEGF) with appropriate tunnel barrier parameters and incorporating modulated barrier height as compared with the MgO barrier. The current–voltage characteristics of the modeled device showed close agreement with experimental data indicating high spin current. Based on the field-induced magnetization analysis, the macro-magnetic reversal analysis suggests the free-layer switching duration of ~3 ns. These observations show the strong candidature of MgOxN1–x (x = 0.57) MTJs for STT-RAM device application. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junction (MTJ) has emerged as a viable candidate for next-generation memory and logic applications. Manipulation of the magnetic and electric field can control the spin and charge state variables that are of utmost importance in spintronics devices. In this article, the modeling of voltage-controlled spin–orbit torque (VCSOT)-based magnetic random access memory (MRAM) is demonstrated. VCSOT MRAM is an ultrafast device owing to a magnetic switching time of 0.7 ns. It is more energy-efficient as compared to spin–orbit torque (SOT) MRAM. VCSOT MRAM has been exemplified for multilevel cell (MLC) application to enhance the memory integration density. Two-bit serial MLC (sMLC) and parallel MLC (pMLC) designs are proposed using VCSOT MRAM. These MLCs are more energy-efficient as compared to SOT-MLCs. Moreover, 2-bit sMLC and pMLC VCSOT-MRAM significantly reduce average write energy by 91.5% and 49.6%, respectively, as compared to SOT-based MLC. Performance metrics for these devices have been illustrated, which shows the negligible read disturbance and write error rates. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJs) with low thermal stability at room temperature have been proposed as read units in beyond CMOS computing architectures including stochastic computing unit and probabilistic-bit (p-bit). Networks of multiple interconnected MTJs may face challenges due to potential device-to-device variations in thermal stability from design targets. Recently, we generated tunable telegraphic signals using a thermally stable MTJ through proper control over an external bias field and a dc voltage bias, where we showed that the average dwell times in the antiparallel (AP) and parallel states could be tuned separately. The implication for this method for p-bit designs is that it allows for p-bits to be compatible with the state-of-the-art magnetoresistive random-access memory (MRAM) technology and introduces a second degree of tunability to the input–output characteristics of the device. In this article, we expand on this method in two important ways. First, we demonstrate the applicability of our method to p-bit designs by modeling the transfer function using the existing p-bit models. Our results indicate that the transfer function can be adjusted with slight modifications to the bias field, which allows for the possibility of p-bit circuits capable of on-chip corrections against device-to-device variations in their thermal stabilities. Second, we identify the physical mechanisms that allow for two degrees of tunability in the output signal, which is explained through the Néel–Brown model. This article provides both applicability and predictability to the dual-biasing method. [ABSTRACT FROM AUTHOR]

Spintronic devices based on domain wall (DW) motion through ferromagnetic nanowire tracks have received great interest as components of neuromorphic information processing systems. Previous proposals for spintronic artificial neurons required external stimuli to perform the leaking functionality, one of the three fundamental functions of a leaky integrate-and-fire (LIF) neuron. The use of this external magnetic field or electrical current stimulus results in either a decrease in energy efficiency or an increase in fabrication complexity. In this article, we modify the shape of previously demonstrated three-terminal magnetic tunnel junction neurons to perform the leaking operation without any external stimuli. The trapezoidal structure causes a shape-based DW drift, thus intrinsically providing the leaking functionality with no hardware cost. This LIF neuron, therefore, promises to advance the development of spintronic neural network crossbar arrays. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic random-access memory (STT-MRAM) based on a single-barrier magnetic tunnel junction (SBMTJ) and a double-barrier magnetic tunnel junction (DBMTJ) has evolved along with a low switching current and low energy consumption to obtain a high areal density and a fast switching speed. The increment of initial temperature, ${T}_{{\text {in}}}$ , in STT-MRAM can achieve low switching energy, ${E}_{{\text {SW}}}$. However, this leads to an unavoidable decrease in $\Delta $ and switching efficiency. In this paper, SBMTJ and DBMTJ were analyzed in terms of the switching efficiency factor with ${E}_{{\text {SW}}}$ reduction by increasing the ${T}_{{\text {in}}}$. The switching temperature, ${T}_{{\text {SW}}}$ , was investigated using a finite-element method simulation. The results show that the DBMTJ(A) and SBMTJ with the same MgO layer thickness of 0.9 nm provide a higher switching current, ${I}_{{\text {C}}}$ , than the DBMTJ(B) with a MgO layer thickness of 1.3 nm. The ${T}_{{\text {SW}}}$ in a DBMTJ(A) is higher than that in an SBMTJ, while ${T}_{{\text {SW}}}$ for a DBMTJ(B) is the smallest because of its low ${I}_{{\text {C}}}$. The DBMTJ(A) and DBMTJ(B) can be applied in a higher temperature range than the SBMTJ at a $\Delta $ of 40. In addition, the STT efficiency factor, $\Delta /{I}_{{\text {C0}}}$ , for a DBMTJ is better than the factor for an SBMTJ. Although the temperature increment would cause an undesirable reduction in $\Delta $ , it can reach a low ${E}_{{\text {SW}}}$ for the requirement of a fast write access time. Therefore, the control device for increasing the ${T}_{{\text {in}}}$ in the MTJs is attractive and should be promoted in the advancement of memory technology. [ABSTRACT FROM AUTHOR]

Stochastic computing (SC) is a promising technology that can be used for low-cost hardware designs. However, SC suffers from its long latency. Although parallel processing can efficiently shorten the latency, duplicated stochastic number generators (SNGs) are necessary, which cause substantial hardware overhead. This paper proposes a scalable SNG based on the spin-Hall-effect (SHE), which is capable of generating multiple independent stochastic streams simultaneously. The design takes advantages of the efficient charge-to-spin conversion from the Spin-Hall material and the intrinsic stochasticity of nanomagnets. Compared to previous spintronic SNGs, the SHE-SNG can reduce the area by $1.6\times -7.8\times $ and the power by $4.9\times -13\times $ while increasing the degree of parallelism from 1 to 16. Compared to CMOS-based SNGs, the proposed SNG obtained $24\times -120\times $ and $53\times $ reduction in terms of area and power, respectively. Finally, three benchmarks were implemented, and the results indicate that SC implementations with the proposed SHE-SNG can achieve $1.2\times -29\times $ reduction of hardware resources compared to implementations with previous CMOS- and spintronic-based designs while scaling the degree of parallelism from 1 to 64. [ABSTRACT FROM AUTHOR]

The spin-transfer torque domain wall (DW) magnetic tunnel junction (MTJ) enables spintronic logic circuits that can be directly cascaded without deleterious signal conversion circuitry and is one of the only spintronic devices for which cascading has been demonstrated experimentally. However, experimental progress has been impeded by a cumbersome modeling technique that requires a combination of micromagnetic and SPICE simulations. This paper, therefore, presents a SPICE-only device model that efficiently determines the DW motion resulting from spin accumulation and calculates the corresponding MTJ resistance. This model has been validated through comparison to the authoritative micromagnetic-based model, enabling reliable prediction of circuit behavior as a function of device parameters with a 10 000 $\times $ reduction in the simulation time. This model thus enables deeper device and circuit investigation, advancing the prospects for nonvolatile spintronic computing systems that overcome the von Neumann bottleneck. [ABSTRACT FROM AUTHOR]

Although spin transfer torque (STT)-based magnetic tunneling junction (MTJ) owns advantages of nonvolatility, nonlimited endurance, and fast write/read, its demand for high current density significantly casts a shadow over its future prospects. Recently, a novel three-terminal MTJ cell that combines voltage-controlled magnetic anisotropy (VCMA) effect and negative capacitance (NC) effect is proposed. Drawing support from the NC amplified VCMA effect and the three-step operation scenario, this novel MTJ cell can dramatically lower the energy consumption to fJ as well as keep high operation speed within nanoseconds. The feasibility of the proposed NC enhanced VCMA spintronics device for memory and logic application is proved by extensive physical simulation in our previous work. However, a SPICE compatible compact model of the proposed NC enhanced VCMA spintronics device is still demanded for circuit and system level evaluation. In this paper, we provide an accurate and fast compact model of NC enhanced VCMA device for both memory and logic applications. [ABSTRACT FROM AUTHOR]

As the basic storage unit of spin transfer torque magnetic random-access memory (STT-MRAM), the perpendicular magnetic anisotropy (PMA) magnetic tunnel junction (MTJ) has been extensively studied in recent years. Lowering the critical switching current and improving the data retention are two crucial pathways to optimize the performance of STT-MRAM. However, the conventional MTJ can merely achieve both. In this paper, we present a physics-based compact model of Ta/CoFeB/MgO PMA double-barrier MTJ (DMTJ) with enhanced thermal stability recording structure. Combination of double-barrier and synthetic double-free layers can heighten the STT effect and enhance the thermal stability simultaneously. A larger STT switching efficiency, compared with conventional MTJ, can thus be realized. The modeling results show great agreement with experimental results. A 1-bit magnetic full adder (MFA) based on DMTJ, as a hybrid logic-in-memory circuit example, has been designed and simulated to validate its functionality. This SPICE-compatible compact model will be useful for high-performance hybrid MTJ/CMOS circuit and system designs. [ABSTRACT FROM AUTHOR]

This paper proposes a novel logic device (SkyLogic) based on skyrmions that are magnetic vortex-like structures having low depinning current density and are robust to defects. A charge current sent through a polarizer ferromagnet (P-FM) nucleates a skyrmion at the input end of an intragate FM interconnect with perpendicular magnetic anisotropy (PMA-FM). The output end of the PMA-FM forms the free layer of an magnetic tunnel junction (MTJ) stack. A spin Hall metal (SHM) is placed beneath the PMA-FM. The skyrmion is propagated to the output end of the PMA-FM by passing a charge current through the SHM. The resistance of the MTJ stack is low (high) when a skyrmion is present (absent) in the free layer, thereby realizing an inverter. A framework is developed to analyze the performance of the SkyLogic device. A circuit-level technique is developed that counters the transverse displacement of skyrmion in the PMA-FM and allows the use of high current densities for the fast propagation. The design space exploration of the PMA-FM material parameters is performed to obtain an optimal design point. At the optimal point, we obtain an inverter delay of 434 ps with a switching energy of 7.1 fJ. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the relationship between size, shape, and the performance of the voltage-controlled magnetic anisotropy (VCMA)-based magnetic tunnel junctions (MTJs) suitable for gigabit scale MRAMs with 10 years of retention time. A Fokker–Planck simulation framework is developed to model the magnetization dynamics in the presence of thermal noise. Here, we numerically show that the optimization of the MTJ geometry can significantly improve the performance of the VCMA-based MTJs. Using an elliptical MTJ with aspect ratio (AR) of 3 reduces the required supply voltage and energy consumption by 80.7% and 92%, respectively, compared to a circular MTJ when the minimum feature size is 50 nm. The design requirements on the VCMA coefficient, ${\xi }$ , are also reduced by 67%. However, the influence of AR is observed to diminish with reduction in the minimum feature size of the MTJ. For instance, when the minimum feature size is 20 nm, the required supply voltage and energy consumption reduce only by 60.29% and 65.30%, respectively. We, then, perform a comprehensive scaling analysis on the VCMA-based MTJs by varying size, geometry, and ${\xi }$ of the MTJs. The predicted scaling trends are then compared with those of the STT MTJs. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJs) with low switching current, high thermal stability, and small device size are strongly preferred for low-power, high-reliability, and high-density spintronic memory and logic applications. The research of MTJs from shape in-plane magnetic anisotropy to interfacial perpendicular magnetic anisotropy (i-PMA) has successfully paved the way down to 20-nm scale, below which, however, the i-PMA approach reaches a physical limit in sustaining sufficient thermal stability while achieving low-power spin transfer torque switching. Recently, studies have been reported a new approach to pave the way toward sub-10-nm MTJs satisfying the requirements by revisiting shape perpendicular magnetic anisotropy (s-PMA). In this paper, we present a compact model of the sub-10-nm s-PMA MTJ device, which captures both the static and dynamic physical behaviors. This model is SPICE-compatible for hybrid MTJ/CMOS circuit designs. This paper is expected to push forward the development of sub-10-nm-scale MTJ-based spintronic memory and logic circuits. [ABSTRACT FROM AUTHOR]

This paper describes a robust, modular, and physics-based circuit framework to model the conventional and emerging magnetic tunnel junction (MTJ) devices. Magnetization dynamics are described by the stochastic Landau–Lifshitz–Gilbert (sLLG) equation whose results are rigorously benchmarked with a Fokker–Planck equation description of the magnet dynamics. We then show how sLLG is coupled to the transport equations of MTJ-based devices in a unified circuit platform. Step by step, we illustrate how the physics-based MTJ model can be extended to include different spintronics phenomena, including spin-transfer torque, voltage-controlled magnetic anisotropy (VCMA), and spin–orbit torque phenomena by the experimentally benchmarked examples. To demonstrate how our approach can be used in the exploration of novel MTJ-based devices, we present a recently proposed MEMS resonator-driven spin-torque nano-oscillator (STNO) that can reduce the phase noise of STNOs. We briefly elaborate on the use of our framework beyond conventional devices. [ABSTRACT FROM AUTHOR]

We investigate scaling of technologically relevant magnetic tunnel junction devices in the trilayer and pentalayer configurations by varying the cross-sectional area along the transverse direction using the nonequilibrium Green's function spin transport formalism. We study the geometry dependence by considering square and circular cross sections.As the transversedimension in each case reduces, we demonstrate that the transverse mode energy profileplays amajor role in the resistance-area(RA) product. Both types of devices show constant tunnel magnetoresistance at larger cross-sectional areas but achieve ultrahigh magnetoresistance at small cross-sectional areas, while maintaining low RA products. We notice that although the critical switching voltage for switching the magnetization of the free-layer nanomagnet in the trilayer case remains constant at larger areas, it needs more energy to switch at smaller areas. In the pentalayer case, we observe an oscillatory behavior at smaller areas as a result of double barrier tunneling. We also describe how switching characteristics of both kinds of devices are affected by the scaling. [ABSTRACT FROM AUTHOR]

Nonvolatile logic computations are of particular interest due to their zero standby leakage power consumption. In this paper, we explore a nonvolatile majority logic using voltage-driven magnetoelectric (ME) switching of ferromagnets. Specifically, we employ ME magnetic tunnel junctions (ME-MTJs) connected in parallel to construct a majority gate. We also present the cascadability of the proposed majority gate using CMOS inverters. Furthermore, through a mixed-mode simulation framework consisting of magnetization dynamics and electron transport model, we analyze the robustness of the proposed majority gate under process variations. Our analysis shows that due to parallel connection of the ME-MTJs, high tunnel magnetoresistance (TMR) ratios are required for proper functioning of the proposed majority gate, in presence of variations. In order to relax the constraints on the TMR requirements, we present an alternate implementation of the majority logic that does not require a parallel connection of ME-MTJs, thereby increasing the robustness against process variations. Energy and delay metrics are presented for a full adder implementation using the proposed majority gates. [ABSTRACT FROM AUTHOR]

Intrinsic properties of magnetic tunnel junctions (MTJs) are exploited for low-power security electronics. The combination of: 1) fast and nonvolatile storage; 2) stochastic nature of subcritical switching; and 3) random variation in the magnetic anisotropy of MTJ make MRAM array ideal for implementing physically unclonable function (PUF). We develop two bit-pattern randomization procedures, one of which can be exercised at wafer level in process line, while the other can be completed in the in-line tester. The procedures generate unpredictable and unclonable bit patterns in a spin-transfer torque (STT)-MRAM array and store them securely in the array. We show the resistance of MTJ is stable through rounds of thermal baking, the readback from the PUF shows no ambiguity from 25 °C to 75 °C. A single embedded STT-MRAM PUF can cover many needs of security electronics. [ABSTRACT FROM PUBLISHER]

We propose, demonstrate, and assess a nontunneling-based nMOS voltage-controlled negative differential resistance (V-NDR) concept for overcoming the intrinsic efficiency and reliability shortcomings of magnetic random access memory memories (MRAM). Using nMOS V-NDR circuits in series with MRAM tunnel junctions, we experimentally observe 40 times reduction in current during switching, enabling write termination and read margin amplification. Large scale Monte Carlo simulations also show 5X improvement in write energy savings and demonstrate the robustness of the scheme against device variability. [ABSTRACT FROM PUBLISHER]

The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data. [ABSTRACT FROM PUBLISHER]

The aim of this paper is to introduce a compact model for perpendicular spin-transfer torque (STT)-magnetic tunnel junctions (MTJs) implemented in Verilog-A to assure easy integration with electrical circuit simulators. It takes into account the effects of voltage-dependent perpendicular magnetic anisotropy, temperature-dependent parameters, thermal heating/cooling, MTJ process variations, and the spin-torque asymmetry of the Slonczewski spin-polarization function in the switching process. This translates into a comprehensive modeling that was adopted to investigate the writing performance under voltage scaling of a $256\times256$ STT- magnetic random access memory array implemented at three different technology nodes. Obtained results show that scaling from 30- to 20-nm node allows a write energy saving of about 43%, while the supply voltage that assures the minimum-energy write operation increases. [ABSTRACT FROM PUBLISHER]

Stateful in-memory logic (IML) is a promising paradigm to realize the unity of data storage and processing in the same die, exhibiting great feasibility to break the bottleneck of the conventional von Neumann architecture. On the roadmap toward developing such a logic platform, a critical step is the effective and efficient realization of a complete set of logic functions within a memory. In this paper, we report a realization of stateful reconfigurable logic functions via a single three-terminal magnetic tunnel junction (MTJ) device within a spintronic memory by exploiting the novel voltage-gated spin Hall-effect driven magnetization switching mechanism. This proposed reconfigurable IML methodology can be implemented within either a typical memory array or a cross-point array architecture. The feasibility of the proposed approach is successfully demonstrated with hybrid MTJ/CMOS circuit simulations. We believe our work may promote the research and development of the revolutionary IML for future non-von Neumann architectures. [ABSTRACT FROM PUBLISHER]

Magnetic tunnel junctions integrated for spin-transfer torque magnetoresistive random-access memory are by far the only known solid-state memory element that can realize a combination of fast read/write speed and high endurance. This paper presents a comprehensive validation of high endurance of deeply scaled perpendicular magnetic tunnel junctions (pMTJs) in light of various potential spin-transfer torque magnetoresistive random-access memory (STT-MRAM) use cases. A statistical study is conducted on the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, pulsewidth, duty cycle, and temperature. The experimental results coupled with TDDB models project > 10^15 write cycles. Furthermore, this work reports system-level workload characterizations to understand the practical endurance requirements for realistic memory applications. The results suggest that the cycling endurance of STT-MRAM is “practically unlimited,” which exceeds the requirements of various memory use cases, including high-performance applications such as CPU level-2 and level-3 caches. [ABSTRACT FROM PUBLISHER]

Dielectric layers are gradually being downscaled in different electronic devices like MOSFETs and magnetic tunnel junctions (MTJ) with shrinking device sizes. As a result, time dependent dielectric breakdown has become a major issue in such devices. In this paper we propose a generalized way of modeling the stress-induced leakage current (SILC) and postbreakdown current (PBC) due to time dependent wear-out of the dielectric layer. We model the traps formed in dielectric layer using Büttiker probe and incorporate the Büttiker probe self-energies in standard self-consistent nonequilibrium Green’s function formalism in order to determine SILC and PBC. In addition, we have shown the impact of breakdown in the dielectric layer on the spin current and spin filtering characteristics of an MTJ. The proposed model is generic in nature. It can be extended from MTJs and conventional CMOS technology to any other devices with any type of single and multiple layers of dielectric material(s). [ABSTRACT FROM PUBLISHER]