Search

A low-noise video rate CMOS image sensor based on charge modulation technique for the time-resolved fluorescence lifetime imaging microscopy (FLIM) with subnanosecond time resolution is described. The CMOS image sensor and ultraviolet laser diode as a light source could be used to successfully measure the decaying images and lifetimes of fura-2 solutions having different concentrations.

Insufficient signal-to-noise ratio (SNR) limits the quality of cardiac pulses measured by multitap CMOS image sensors (CISs). We present an in-pixel temporal redundant samplings (TRS) method for enhancing the SNR through sampling the charges originated by one individual optical scene into the multiple storage taps in turn with the identical time window, enabling magnification of the image signal in shot noise domain. Modeling indicates that the linear SNR increases with a factor square root of TRS sampling number, which is also verified by characterization results utilizing a four-tap CIS. Application results show that the high-frequency (HF) noise components observed in the measured cardiac pulses can be attenuated by 67.9%, 48%, and 53.6% with heart rate detection accuracies up to 99.7%, 99.3%, and 98.7% by applying TRS modes under given conditions of stable ambient, background light (BGL) variation, and motion disturbance, respectively. Moreover, the proposed method is as well foreseeable to be extended to other multitap-involved imaging applications. [ABSTRACT FROM AUTHOR]

An analysis of the temporal read noise on the signal path of a complementary metal-oxide semiconductor image sensor was conducted in order to investigate the effectiveness of high-gain column amplifiers in enhancing sensor sensitivity. The analysis showed that by increasing the column amplifier gain the direct noise components can be greatly reduced which indicates that an extremely low-noise readout circuit could be achieved through the development of a double-stage noise-canceling architecture.

A description is provided of the measurement results of high-gain column readout circuits for CMOS image sensors. Results of the measurement show that the double-stage noise-cancelling architecture has better noise performance than that of the single-stage architecture at a first-stage gain of great than 6.

In this paper, a 1.1-μm-pitch 33-Mpixel 240-fps backside-illuminated 3-D-stacked CMOS image sensor with three-stage cyclic-cyclic-successive-approximation-register (SAR) analog-to-digital converters (ADCs) is developed. The narrow-pitch interconnection technology that connects the pixels and arrayed ADCs inside the pixel area is described. The 3-D-stacked architecture, constructed using the interconnection technology, makes it possible to place a 1932 (H) × 4 (V) correlated-double-sampling/ADC array underneath the pixel area. Furthermore, the pipelined and parallel operation of the three-stage cyclic-cyclic-SAR ADC architecture effectively reduces the conversion time period and power consumption and achieves 12-b precision within one horizontal scan time of 0.92 μs. As a result, the interconnection technology and ADC architecture achieved a high frame rate of 240 fps in 33 Mpixels. Random noise of 3.6 e- and low power consumption of 3.0 W were attained at an extremely high pixel rate of 7.96 Gpixel/s. A good figure of merit is achieved compared with recently developed image sensors. [ABSTRACT FROM AUTHOR]

A high-performance CMOS image sensor (CIS) with 13-b column-parallel single-ended cyclic ADCs is presented. The simplified single-ended circuits for the cyclic ADC are squeezed into a 5.6-µm-pitch single-side column. The proposed internal reference generation and return-to-zero digital signal feedback techniques enhance the ADC to have low read noise, a high resolution of 13 b, and a resulting dynamic range of 71 dB. ultralow vertical fixed pattern noise of 0.1 e-rms is attained a digital CDS technique, which performs A/D conversion twice in a horizontal scan period (6 µs). The implemented CIS with 0.18-µm technology operates at 390 frames/s and has 7.07-V/Ix sensitivity, 61-µV/e- conversion gain, 4.9-e-rms read noise, and less than 0.4 LSB differential nonlinearity. [ABSTRACT FROM AUTHOR]