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With experimental and numerical simulation, we report the origin of the performance enhancement in p-type SnO thin-film transistors (TFTs) due to fluorine plasma treatment (FPT). To study the effect of fluorination, using the reactive-ion-etching process, the devices are treated at various plasma powers upto 60 W. It is observed, through X-ray photoelectron spectroscopy and XRD measurements, that the plasma fluorination modifies the defect/trap states of SnO channel and SnO/HfO2 interface. These effects are introduced through density of state (DOS) model for SnO in numerical simulations, to understand the routes of electrical performance improvement. It is observed that the attributes of donor-like band-tail state and acceptor-like Gaussian defect states (Sn vacancies) are modified in overall DOS due to plasma fluorination. The treated device shows excellent electrical performances with high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ~107 and low substhreshold swing of ~ 100 mV/dec and field-effect mobility ( $\mu _{\text {FE}}$ ) of 2.13 cm2V−1s−1.

In this paper, we reported a ferroelectric HfAlO x negative capacitor transistor with gate-stress (GS) engineering. Compared to control device, the HfAlO x transistor with GS engineering percentage of $\text{I}_{ \mathrm{\scriptscriptstyle ON}}$ enhancement and 27% $\text{V}_{T}$ reduction under the assistance of the negative capacitance (NC) effect. The orthorhombic phase transition played a crucial role in realizing the NC effect. From the results of the material analysis, the theoretical Landau simulation and electrical measurement, we demonstrated that the GS is favorable for inducing orthorhombic phase crystallization of HfAlOx and stabilizing the NC effect, which shows the potential for the application of advanced technology node.

For the first time, we successfully demonstrated the dopant-free HfO2 negative capacitance (NC) transistor featuring a low gate-overdrive voltage and a nearly hysteresis-free sub-40 mV/dec swing. These excellent performances can be ascribed to the reduction of the monoclinic phase suppressed with the thickness scaling and gate stress engineering favorably rearranging oxygen vacancies to boost orthorhombic phase transition. The highly scalable and dopant-free NC transistor shows the potential for the application of advanced CMOS technology.

Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current–voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a $0.11~\mu \text{m}$ 32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure.