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In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high- $k$ , and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al2O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2O3) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow.

In this paper, we report the 2-D drain current model for asymmetric dual material (DM) junctionless double gate transistor. On the basis of channel potential, transconductance and its higher order derivatives are estimated and verified with the ATLAS 3-D device simulator results. The developed model is also applicable to investigate the digital performance of the device in terms of voltage transfer characteristics of nMOS inverter circuit. The impact of the length of control gate on the analog performance has also been investigated. Results also highlight the advantage of DM gate over the single material gate for digital and analog applications using CMOS inverter and common source amplifier through exhaustive circuit simulation.

The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control.

Recently, Gallium Nitride (GaN) power devices have become very attractive because of their high power density. GaN FETs, however, differ from MOSFETs, and it is possible that GaN-based power electronics circuits show lower efficiency than Si-based circuits because of their unique characteristics. A capacitor-less gate drive circuit is proposed as a solution. This paper shows the effectiveness of a capacitor-less gate circuit in terms of gate drive loss, reverse conduction loss, and recovery loss, and compares it with capacitor-type gate drive circuits for GaN FETs. Drive loss analysis of an inverted gate drive circuit showing the lowest losses among capacitor-type gate drive circuits and a capacitor-less gate drive circuit was made to examine the differences between them. The results show that higher efficiency operation is obtained by applying a capacitor-less gate drive circuit to simple test circuits.

Advanced dual control gate with surrounding floating gate (DC-SF) cell process and operation schemes are successfully developed for 3-D nand flash memories. To improve performance and reliability of DC-SF cell, new metal control gate last (MCGL) process is developed. The MCGL process can realize a low resistive tungsten (W) metal wordline, a low damage on tunnel oxide/inter-poly dielectric (IPD), and a preferable floating gate (FG) shape. Also, new read and program operation schemes are developed. In the new read operation, the higher and lower Vpass-read are alternately applied to unselected control gates to compensate lowering FG potential to be a pass transistor. In the new program scheme, the optimized Vpass are applied to neighbor WL of selected WL to prevent program disturb and charge loss through IPD. Thus, by using the MCGL process and new read/program schemes, the high performance and reliability of the DC-SF cell can be realized for 3-D nand flash memories.

State-of-the-art compact models of gate access resistance are investigated and compared with RF measurements for 28-nm high-k/metal gate MOS transistors. This work shows that the usual lumped gate resistance model fails to capture both geometry scaling and voltage dependence observed on silicon. The increasing role of the interface resistance is highlighted, and an improved gate access resistance model is proposed, featuring an encapsulation of the interface resistance component by parasitic capacitances. Theoretical insights and relevance of this new distributed model and associated parameters are also discussed.

This paper presents a novel low-power gate driver circuit fabricated from glass by using hydrogenated amorphous silicon (a-Si:H) technology and a standard five-mask process. The tolerance of the threshold voltage shift of the proposed gate driver circuit can be estimated as 30 V by using an H-SPICE simulator. Measurement results indicate that the rising and falling times of the output waveform are equal to those in the initial state. Moreover, the proposed gate driver circuit can operate reliably at a high temperature (T = 120 °C) for over 360 h. Furthermore, the proposed gate driver circuit reduces power consumption by 77.3% over that of a conventional gate driver circuit.

A new 3-D stacked NAND Flash memory is proposed to achieve high density by using common gate structure and shield layer. By adopting trench structure instead of through-hole structure, threshold voltage (Vth) variation in cells of a cell string can be reduced, and the number of stacked control-gate (CG) electrodes in a gate stack can be increased as a result. In the trench between adjacent CG stacks, gate O/N/O stack, poly-Si bodies, backside oxide, and shield layer are formed. To investigate the key characteristics of the memory, we fabricated proposed 3-D stacked NAND Flash memory cell strings which have three layers of vertically stacked CGs. Vth could be controlled by applying a bias to the shield layer. We also showed reasonable cycling and retention characteristics of a cell in a string and good pass-gate properties of the cell in the bottom of the trench.

This paper investigates the read operation of poly-Si nanowire silicon-oxide-nitride-oxide-silicon devices with independent double-gate (IDG) configuration. The device features oxide-nitride-oxide (ONO) stack as the charge storage medium in one of the two gated sides with pure oxide in the other. Owing to the IDG feature, the shift in the device's transfer characteristics due to a change in the amount of storage charges can be sensed with two different modes, which have one of the two gates applied with a sweeping bias (driving gate) and the other with a fixed bias (control gate). Our analysis and experimental data show that a larger memory window is obtained when the gate of the ONO side is used as the driving gate. Moreover, the memory window of this mode is essentially independent of the bias applied to the control gate. Based on this finding, a novel Flash structure featuring IDG cells with a common control gate is proposed.

The design of analog and RF circuits in CMOS technology has become increasingly more difficult as device modeling faces new challenges in the deep-submicrometer regime and emerging circuit applications. In this paper, we investigate the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications. The gate engineering technique used here is the dual-metal gate technology, and the channel engineering technique is the conventional halo doping process. For analog applications, importance is given to the subthreshold regime as CMOS circuits operated in this regime are very much attractive for ultralow-power high-gain performances. Gate- and channel-engineered devices show an increase of gain by 45% and 35%, respectively, compared with the single-metal DG MOSFET. The gate-engineered device shows an improvement of 21.6% and 20% in the case of fT and fMAX values, whereas the channel-engineered device exhibits a reduction of fT by 2.7% with nearly equal fMAX.

This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping (NA), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern.

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system

A novel dynamic gate capacitance characterization technique is proposed to evaluate switching losses in power devices. Dynamic gate capacitance is obtained by measuring the gate displacement current due to the application of a controlled gate voltage pulse, closely matching real operation conditions of power switches. Several architectures for 20-V MOSFET transistors, integrated in a low-cost power management 0.13-/spl mu/m CMOS technology, are studied. Experimental results are compared to a specific small-signal model for switching transition gate capacitance.

The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improvement of the memory performance is achieved. The key element of this improvement is access gate oxide thickness reduction combined with suitable design of the channel/source/drain doping profiles. An increase of the memory readout current by a factor of two was achieved with an excellent low-leakage current level of the access gate transistor. The increase of the read current allows faster read access, while the excellent subthreshold behavior of the access gate transistor allows aggressive scaling of the access gate length down to 160 nm. A gate voltage as low as 1 V can be used for reading the cell, so there is no need for voltage boosting. The source-side injection programming speed is increased by one order of magnitude for devices with thin access gate oxide. The compact cell is suited for embedded applications in sub-100-nm CMOS generations.

We propose a compact model for a Flash memory cell that is suitable for circuit simulation. The model includes a hot-electron gate current model that considers not only channel hot electron injection but also channel initiated secondary electron injection to express properly substrate bias dependence of gate current. Tunneling gate current for erasing is expressed by the BSIM4 tunneling gate current model. Good agreement between measured and simulated results of both programming and erasing characteristics for 130-nm technology Flash memory cells indicates that our model is useful in designing and optimizing circuit for Flash memories.

EEPROM devices with either N-type or P-type floating gate were fabricated and characterized. Program/erase speeds and stress-induced leakage current-related retention characteristics for both types of devices are explained. Discrepancies between previously published reports on P-type floating gate devices and PMOS gate current measurements are resolved. The feasibility of integrating P-type floating gate EEPROMs in high density memory arrays is examined.

Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon-on-insulator nanometer-scale wire are proposed and fabricated, using the combination of the conventional lithography and process technology. Clear Coulomb oscillation originated from the two electrically induced tunnel junctions and the single Si island between them is observed at 77 K. The island size dependence of the electrical characteristics shows the good controllability and reproducibility of the proposed fabrication method. Furthermore, the device characteristics are immune to gate bias conditions, and the position of Coulomb oscillation peak is controlled by the sidewall depletion gate voltage, without the additional gate electrode. Based on the current switching by sidewall gate voltage, the basic operation of the dynamic four-input multifunctional SET logic circuit is demonstrated at 10 K. The proposed SET offers the feasibility of the device design and optimization for SET logic circuits, in that its device parameters and circuit parameters are controllable by the conventional VLSI technology.

Numerical device-simulation results, supplemented by analytical characterizations, are presented to argue that asymmetrical double-gate (DG) CMOS, utilizing n/sup +/ and p/sup +/ polysilicon gates, can be superior to symmetrical-gate counterparts for several reasons, only one of which is its previously noted threshold-voltage control. The most noteworthy result is that asymmetrical DG MOSFETs, optimally designed with only one predominant channel, yield comparable, and even higher drive currents at low supply voltages. The simulations further give good physical insight pertaining to the design of DG devices with channel lengths of 50 nm and less.

The use of polycrystalline SiGe as the gate material for deep submicron CMOS has been investigated. A complete compatibility to standard CMOS processing is demonstrated when polycrystalline Si is substituted with SiGe (for Ge fractions below 0.5) to form the gate electrode of the transistors. Performance improvements are achieved for PMOS transistors by careful optimization of both transistor channel profile and p-type gate workfunction, the latter by changing Ge mole fraction in the gate. For the 0.18 /spl mu/m CMOS generation we record up to 20% increase in the current drive, a 10% increase in the channel transconductance and subthreshold swing improvement from 82 mV/dec to 75 mV/dec resulting in excellent "on"/"off" currents ratio. At the same time, NMOS transistor performance is not affected by gate material substitution.

We describe a physically based model for a two-dimensional (2D) MESFET, a novel hetero-dimensional transistor. The model is valid for a "single" gate in which the sidewall contacts are biased together, a dual-gate configuration in which the gates are biased independently, and a multiple-gate configuration for three or more side gates. The model has been implemented in the circuit simulator AIM-SPICE. The modeling results are in good agreement with the experimental data.

This paper presents an improved figure-of-merit (FOM) for CMOS performance which includes the effect of gate resistance. Performance degradation due to resistive polysilicon gates is modeled as an additional delay proportional to the RC product of a polysilicon line. The new FOM is verified from delay measurements on inverter chains fabricated using a 0.25-/spl mu/m CMOS process. A furnace TiSi/sub 2/ process is used to underscore the effect of increased sheet resistance of narrow polysilicon lines. Excellent correlation between measured and predicted inverter chain delays is obtained over a variety of design, process and bias conditions. An expression for the gate sheet resistance requirement is derived from the new FOM. Using this expression, requirements on the gate sheet resistance are calculated corresponding to a technology roadmap for performance and oxide thickness.

This paper describes the high performance of T-shaped-gate CMOS devices with effective channel lengths in the sub-0.1-/spl mu/m region. These devices were fabricated by using selective W growth, which allows low-resistance gates smaller than 0.1 /spl mu/m to be made without requiring fine lithography alignment. We used counter-doping to scale down the threshold voltage while still maintaining acceptable short-channel effects. This approach allowed us to make ring oscillators with a gate-delay time as short as 21 ps at 2 V with a gate length of 0.15 /spl mu/m. Furthermore, we experimentally show that the high circuit speed of a sub-0.1-/spl mu/m gate length CMOS device is mainly due to the PMOS device performance, especially in terms of its drivability.

The delay time of an inverter or NAND chain at a gate length yielding equal standby current and active current is used as the definition of a maximum Figure of Merit (FOM), FOM/sub max/. The circuit power that occurs under this condition of equal standby and active currents is an equally important measure. This FOM/sub max/ technique is particularly useful in characterizing complementary metal-oxide-semiconductor (CMOS) technologies in the deep submicron regime. A knowledge of the exact value of gate length is not necessary to apply the FOM/sub max/ methodology. For a fixed supply voltage and gate oxide thickness, node capacitance and transistor drive, and off currents determine the value of FOM/sub max/. The value of gate length at which FOM/sub max/ occurs decreases with decreasing supply voltage. FOM/sub max/ analysis is applied to the comparison of CMOS technologies using gate oxide thicknesses of 5.7 and 3.8 nm.

An experiment to determine the effect of gate electrode resistivity on circuit speed gave unexpected results: circuits with the lowest sheet resistance had the poorest circuit speed. Explanation of this behaviour required development of a new high-frequency method of measuring the impedance of the gate electrode. This method revealed that the circuits with a composite gate electrode had been formed with a partial discontinuity. The measurement technique is described, and the evidence of the discontinuity is shown. The effect of the discontinuity on device and circuit speed is demonstrated.

A new dual poly-Si gate CMOS fabrication process is proposed. The incorporated technology features a boron-penetration-resistant MBN gate structure for pMOSFET's, and a dual poly-Si gate CMOS process involving separate depositions of in-situ doped n/sup +/ and p/sup +/ poly-Si for the nMOS and pMOS gates, 0.2-/spl mu/m CMOS devices with 3.5-nm gate oxide have been successfully fabricated. The advantages of the new process are demonstrated on these test devices. A CMOS 1/16 dynamic frequency divider fabricated by the new process functions properly up to 5.78 GHz at a 2-V supply voltage. >

A floating-gate MOSFET device that can be used as a precision analog memory for neural network LSIs is described. This device has two floating gates. One is a charge-injection gate with a Fowler-Nordheim tunnel junction, and the other is a charge-storage gate that operates as a MOSFET floating gate. The gates are connected by high resistance, and the charge-injection gate is small so that its capacitance is much less than that of the charge-storage gate. By applying control pulses to the charge-injection gate, it is possible to charge and discharge the MOSFET floating gate in order to modify the MOSFET current with high resolution over 10 b. The charge injection can be carried out without disturbing the MOSFET output current with high voltage control pulses. This device is useful for on-chip learning in analog neural network LSIs. >

0.6- mu m CMOS technologies were developed on thin SIMOX film and applied to a 16 K gate CMOS gate array. High-speed operation with low power consumption characteristics was verified with ring oscillators on the thin SOI CMOS gate array with V/sub D/=3 V, compared with bulk-Si ring oscillators with the same dimension. Parasitic capacitances in thin SOI and bulk-Si circuits were estimated to clarify the origin of the speed gain from the propagation delay times of the ring oscillators with various kinds of controlled load capacitances. Full functional operation was achieved for a 16 b*16 b multiplier on the SOI CMOS gate array with 1.4 times higher speed operation and 0.8 times lower power consumption than the multiplier on a bulk-Si substrate. >

The M-SGT has a three-dimensional structure, which consists of the source, gate, and drain arranged vertically. The gate electrode surrounds the crowded multipillar silicon islands. Because all the sidewalls of the pillars are used effectively as the transistor channel, the M-SGT has a high-shrinkage feature. The area occupied by the M-SGT can be shrunk to less than 30% of that occupied by the planar transistor. The small occupied area and the mesh-structured gate electrode lead to the small junction capacitance and the small gate electrode RC delay, resulting in high-speed operation. The fabrication of the M-SGT CMOS inverter chain is discussed. The propagation delay reduces to 40%, compared with the planar transistor inverter chain. >

A simple formula is proposed for the analysis of the gate delay of CMOS gate under low V/sub DD/. The effects of device parameters on gate delay and energy are readily obtained using the formula. Thus, it has the potential for use in the design of device parameters in the low V/sub DD/ CMOS circuits.

A theoretical description of gate tunnel current in an MOS transistor is presented, and the results of calculations for the case of an n-channel MOSFET with extremely thin gate oxides are given. A comparison shows that the gate tunnel current is low in comparison with the drain current, even in the case of extremely thin gate oxides. This is in agreement with experimental results published in the literature. It is concluded that the minimal gate oxide thickness in MOS/VLSI circuits will result if very good quality ultrathin oxides are realized in a controllable way rather than from the flow of too large a gate tunnel current. However, in some circuit applications of the MOS transistor the problem of input leakage current can be especially important, and then gate tunnel current can limit the minimal oxide thickness. >

The impact of gate leakage current on MOSFET performance is examined and limits on gate oxide thickness for static and dynamic logic are determined. Leakage current has been found to be a greater problem for static logic than for dynamic logic circuits. Gate leakage current limits the minimum oxide thickness to approximately 2 nm for static logic configurations, and to approximately 3 nm in dynamic logic circuits. A poor drain design can become a limiting factor for dynamic logic circuits and raise the minimum oxide thickness required. Switching delay of static logic is relatively immune to the effects of leakage current. A MISFET with a 2.6 nm thick gate insulator of Si/sub 3/N/sub 4/ has been fabricated showing typical drain current characteristics, but with a large amount of gate leakage current. >

A novel hetero-material gate MOSFET intended for integration into the existing deep-submicron silicon technology is proposed and simulated. It is shown that by adding a layer of material with a larger workfunction to the source side of the gate, short-channel effects can be greatly suppressed without degrading the driving ability. The threshold voltage roll-off can be compensated and tuned by controlling the length of this second gate. The new structure has great potential in breaking the barrier of deep-suhmicron MOSFET's scaling beyond 0.1 /spl mu/m technologies.

A 770-gate single-level metallized Si-gate CMOS/SOS gate array has been fabricated using a new customization technique: cutting pre-defined n+epitaxial silicon lines. Simple process and quick turnaround time are both realized. Total fabrication steps are reduced to 53 percent of those of the double-level metallized CMOS/bulk gate array because of a simplified CMOS/SOS process and only three-mask customization. Customization steps are also reduced to 55 percent. High packing density and high switching speed comparable to those of the double-level metallized CMOS/bulk gate array are also obtained. The number of the silicon wiring channels of the conventional single-level metallized gate array is reduced by a factor of two by the cutting technique. This value corresponds to a 24 percent decrease in the chip area. Even with a conservative 4-µm technology, gate delay of 0.8 ns is obtained at the power-supply voltage V DD of 5 V. Up to 25 MHz operations are verified for a shift register. On this gate array a control unit for a CCD camera is fabricated; 95 percent of the internal basic cells are utilized. The active power dissipation of this unit is 1.0 mW at V DD of 5 V.

Allowable design regions for thin-film SOI/CMOs device structures, taking account for the relation between SOI film thickness and the concentration of SOI substrate impurities, are investigated. Not only are the advantages of thin-film SOI MOSFETs verified, but constraints on threshold voltage and kink-free controls are also shown. Conventional n/sup +/ poly-Si gate NMOSFETs tend to have difficulty in maintaining high transconductance for deep submicrometer gate length because of the constraints of normally-off threshold voltage and kink-free characteristics. By choosing a gate with the same work function as the intrinsic silicon semiconductor, the allowable design regions for deep submicrometer gate SOI MOSFETs are expected to have a low-impurity SOI substrate and an optimized threshold voltage for high-performance SOI/CMOS LSIs. The device scaling for various gate electrodes are also discussed for 1- to 0.2 mu m gate SOI/CMOS devices. >

A small-signal equivalent circuit for the GaAs MESFET, suitable for the design of integrated circuits, was developed that includes the following features: (1) at high frequencies, the gate channel has the character of an RC transmission line, for which a pi -equivalent representation is used; (2) under saturated current conditions, a stationary high-field domain may be present in the conducting channel, for which an equivalent is derived in terms of a small-signal admittance. The resulting equivalent circuit was optimized with very good results by modeling process average S-parameters between 1 and 25 GHz for a 1 mu m gate device. The basic structure of the model is relevant for other FET designs such as heterostructure FETs (HEMTs) and devices with submicrometer gate lengths. >

An E-shaped Gunn-effect device is proposed as a high-speed logic gate. It is composed of two Gunn diodes connected by a gate section which is located between the two diodes adjacent to the common cathode. Along the gate edge, an ohmic electrode is established to control the electric field at the gate section. It is fabricated into monolithic circuitry of GaAs, and its performance is found to be in good agreement with the result of a computer simulation. From this, it is concluded that the transverse extension of a high field domain can be controlled by changing a potential on the ohmic gate, which allows this device to be employed as a binary logic gate performing Z = X + Y.∼W (X, Y, W: binary inputs). The delay time of about 50 ps has been obtained with the gate width of 100 µm. For the convenience of designing a smaller device in order to reduce the delay time, a result of small signal analysis on the two-dimensional domain initiation is given. Also referred to is an H-shaped Gunn device which is profitable if considerable delay is required in performing the above-mentioned logic operation.

A gate family called modified variable threshold logic (MVTL) is proposed. The OR gate is a two-junction interferometer with one magnetically coupled control line. Magnetic coupling and current injection are used to switch the logic state of the gate. By optimizing the gate parameters, an operating margin of +or-43% and a switching speed of 2.5 ps/gate are obtained. the gate area is 30 mu m*24 mu m with a 1.5- mu m minimum junction diameter. The gate family consists of an OR gate, a single-junction AND gate, and a timed inverter (TI) that consists of the OR gate, a junction, and resistors. The delay time of the gate operated in the actual circuit was found to be less than 10 ps. Circuits having up to 1000 gates, the critical path model of a 16-bit*16-bit multiplier, and a 16-bit arithmetic logic unit have been successfully operated. When the Josephson gate is operated with three-phase power, it is possible to construct any sequential circuit without the complex latch circuit required to prevent the race condition for one- or two-phase power supplies. >

A silicon-gate n-well CMOS process for an application of digital circuits operated by TTL compatible supply voltage was developed. Full ion-implantation technology, a new photolithography technique, n+-doped polysilicon gate which contain no boron impurities, and thin gate oxide of 65 nm can realize CMOS circuits of 2-µm gate length. Average impurity concentrations measured from substrate bias effect of MOSFET's and junction depth are in good agreement with those expected from impurity profiles calculated by a simple diffusion theory. So, the process design for CMOS circuits operated by any supply voltage is possible, by adjusting threshold voltages. The process can easily be extended to n-MOS/CMOS process (E/D MOS and CMOS on the same chip), if a photomask to fabricate depletion-type n-MOSFET's is provided.

A complementary logic circuit employing heterostructure MISFET's is shown to have a larger logic swing and noise margin than an E/D MESFET logic circuit. The noise margin is calculated using a new gate current model that is derived by taking into account the small surface potential dependence on the gate voltage at the heterointerface. The circuit simulation indicates that, for multi-input logic gates, a NAND gate configuration is superior to a NOR gate configuration from the viewpoints of noise margin and switching speed. The normalized high- and low-level noise margins are comparatively balanced (34 and 49 percent) for a three-input NAND gate. For a fan-in/fan-out of 3/3 and a 100-fF wiring capacitance condition, a 54-ps delay time and 57-μW power dissipation/gate at a 100-MHz clock frequency are possible for a NAND gate with 0.5-μm gate-length MISFET's at 77 K.

This paper describes an effect of the "gate isolation" technique and its application to a 10K-gate CMOS gate-array VLSI chip. This gate array is fabricated using a 2-/spl mu/m n-well CMOS technology, with double-level metallization. As an example, a 32-bit parallel array multiplier is designed using a fully automatic CAD system. The density of CMOS gate arrays using gate isolation is estimated to be 1.10 to 1.26 times greater than that of the arrays using several types of oxide isolation, when implementing circuits with complexities on the order of 10K gates.

An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-µm gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.

A novel Josephson logic gate called the asymmetrical interferometer device (AID) is presented. It is composed of a pair of asymmetrical interferometers whose outputs are injected into a single junction. The interferometers are individually operated as two input OR and the single junction is worked as AND. (A + B) (C + D) operation is accomplished by only one AID gate. They have a serial fan-in capability due to their magnetic coupling scheme. The gate size is reduced by half, compared with the previous current injection logic (CIL) gate. With these AID gates, a high-speed two-bit dual rail adder circuit is configured, which provides the logic circuits performing with both true and complement inputs and without any timing circuits. The AID gate fabricated by standard 5-µm Pb-alloy technology showed a wide margin over ±20 percent that was in good agreement with statically designed characteristics. Experimental adder operation was also successfully performed.

A double-well n-epi CMOS process was used to investigate the influence of technological parameters relevant to high-speed performance. Dopant concentrations, well depths, channel lengths, and epi-layer thickness have been varied with regard to low propagation delay times measured by three-input NOR/NAND ring oscillators. Parasitic bipolar effects like latchup have been taken into consideration. Ring oscillator circuits designed in general with 3.5-µm design rules and with geometrical gate lengths ≤2 µm exhibited gate delays ≤0.9 ns. The influence of low temperature processing on short-channel and field oxide transistors is discussed.

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. n-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on a oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200°C ± 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous. The advantages of the new structure are: avoidance of field inversion, elimination of guard rings, and thinner and more stable oxides.

A model is presented which takes into account the distributed nature of the gate in microwave field-effect transistors (FET's). The model is used to derive an expression for the equivalent gate impedance. The result is suitable for determining the reduction in the available gain tlue to gate losses.

Hot-electron effects were investigated via direct measurements of gate currents in both n-channel and p-channel devices for 1-µm CMOS structures. Results reveal substantial gate currents in p-channel transistors biased into saturation, implying that the P-MOS device may also pose a significant reliability hazard in a modern CMOS structure.

Summary form only given. In order to overcome the scaling limitations on planar transistors for future LSIs, the authors propose a novel surrounding gate transistor (SGT), whose gate electrode surrounds multipillar silicon islands. The new SGT offers large drain currents even in a very small occupied area. The large channel width is achieved by using all the sidewalls of the crowded multipillar silicon islands as the channel regions. Owing to this multichannel structure, a transistor with extremely small occupied area and sufficient drivability can be obtained. The small occupied area and the mesh-structured gate electrode lead to small gate electrode RC delay and small junction capacitance, resulting in very high-speed operation, contrary to the cases of the planar transistor and the conventional SGT. A new SGT CMOS inverter chain was fabricated. The propagation delay is reduced to 20% of that for the case of the planar transistors. This new SGT is extremely attractive for future high-speed ULSI devices. >

The Silicon Gate Technology is a new approach to fabricating insulated gate field effect transistor circuits, in which the metal gate electrode is replaced by a doped, silicon electrode. The work function difference between the gate electrode and semiconductor bulk will now be determined by the doping of the gate electrode. This leads to normally off p-channel devices with threshold voltages typically between 1.1 v and 2.5 v on material with 1000A gate oxide. It is a self-aligned gate structure and has a buried-gate electrode which allows crossover of gate regions and closer spacing of source-drain contact. The fabrication needs 4 masking steps and was found to be compatible with existing planar technology.