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The shape of the channel cross section in rectangular nanowire (NW) gate-all-around (GAA) MOSFETs turns trapezoidal due to process variations. In this article, the impact of process-induced inclination of sidewalls on gate-induced drain leakage (GIDL) current in the trapezoidal channel NW GAA MOSFETs has been systematically investigated using experimental and calibrated TCAD simulation results. The GIDL current has also been analyzed against the variation in other device parameters, such as channel length, height, and width. The lateral band-to-band tunneling (L-BTBT) mechanism at the channel/drain junction has been considered in simulations to obtain the GIDL current. The investigation reveals that the GIDL current increases up to two times if the process-induced sidewalls inclination angle increases from 0° to 20°. [ABSTRACT FROM AUTHOR]

Two typical topology shapes of the microstrip meander line (MML) including round U-shaped and V-shaped slow-wave structure (SWS) for ${D}$ -band traveling wave tubes (TWTs) are comparatively investigated, fabricated, and tested in this article. As a critical factor applied in millimeter-wave frequency, the high-frequency losses of the MML SWS are emphatically discussed. The two types of golden SWSs are both fabricated with the thin-film circuit technology on quartz substrates. After the surface roughness test and the cavity fabrication, the SWS samples are assembled and tested. According to the experimental test results, the ${S}_{11}$ parameters of the U-shaped and V-shaped transmission models are below −13.5 dB versus −15 dB, and the “cold” ${S}_{21}$ parameters are over −6.4 dB versus −4.9 dB, which are approached to the simulation results with the consideration of the silver conductive paste (SCP). At 140 GHz, the tested transmission losses for the U-shaped SWS and V-shaped SWS are about 0.35 and 0.29 dB/mm, respectively. Although particle-in-cell (PIC) simulations for the two SWSs both predict more than 100-W output power, the V-shaped MML TWT shows better bandwidth and loss performances than the U-shaped MML TWT. [ABSTRACT FROM AUTHOR]

In this work, high-performance GaN vertical Schottky barrier diodes (SBDs) are successfully fabricated on the GaN-on-GaN substrate by using the self-alignment trench structure and argon (Ar) ion implantation. The fabricated diodes achieve a high current ON/ OFF ratio of 108 and high breakdown voltage (BV) of 656 V due to the reduced surface electric field effect. Besides, the temperature-dependent reverse leakage characteristics show that two Poole–Frenkel emission (PFE) processes dominate the carrier transport. This work shows great potential of the self-alignment trench structure in fabricating GaN vertical SBDs to improve the BV with simply fabrication process. [ABSTRACT FROM AUTHOR]

Currently, the semiconductor industry requires test escape levels that approach the ppb level for application domains, such as automotive. Such quality levels, however, can only be reached if latent defects are screened out, as they have become the major bottleneck in analog and mixed-signal IC testing. Latent defects can be activated using accelerated aging, but this procedure has several drawbacks. Most notably, activation can move latent defects to the product lifetime that, otherwise, would not even have expressed themselves. Therefore, methods are needed that allow the detection of these defects without using activation. Developing such methods, however, has been hampered by the lack of compact latent defect models that allow simulating circuits affected by this type of defect. This article alleviates this problem by experimentally validating a recently presented compact model for latent defects and establishing the practical range of model values that should be used in simulations. The experiments performed on a 0.35- $\mu \text{m}$ technology consist of characterizing transistors containing latent defects that have been artificially introduced by etching pinholes in their gate. The measurement results corroborate that the drain current in transistors with defects increases with the area and depth of the defect, and that this behavior can be accurately modeled using an effective ${t}_{ox}$ value. [ABSTRACT FROM AUTHOR]

In this article, we present a novel electronic nose fabrication process based on highly programmable anodic aluminum oxide (AAO) nanoarchitectonics and ultrasonic spray pyrolysis (USP) deposition. Featuring an ultralow manufacturing cost, the deposited material’s morphology can be accurately controlled with fabricated general-purpose AAO template. Compared with nonstandard lithography-based template fabrication method, the need of complicated Bosch etching process and its associated complex process parameter tuning is eliminated. As a result, the cost-effective mass production of 3-D nanotemplate-based material and devices can be enabled. In addition, the target material’s limited coverage and time efficiency issues widely existing in the previous deposition methods are well-addressed by our customized USP deposition, especially for the 3-D nanotemplate with large surface-to-volume ratio, leading to significantly improved gas-sensing performance. Moreover, the proposed fabrication recipe, together with the adopted gas recognition algorithms based on linear discriminant analysis (LDA), is validated based on the reported extensive measurement results for five gas biomarkers widely exploited for patients’ exhaled gas-sensing and recognition applications. This shows great potential for the early disease diagnose of diabetes, breast cancer, acute lung injury, colon diseases, lung cancer, and so on. [ABSTRACT FROM AUTHOR]

Graphene with atomic layer thickness has excellent mechanical properties and provides tremendous potential for developing high-performance pressure sensors. However, bare graphene is sensitive to humidity, and oxygen in the air also significantly affects the stability of graphene pressure sensor. In this work, a highly sensitive pressure sensor was fabricated through the MEMS process and nanofilm transferring. The graphene sensing element is entirely isolated from the external environment by the initial protection of h-BN, followed by the secondary protection of Cu–Sn solid–liquid interdiffusion bonding. After the static test, an average sensitivity of $2.9\times10$ −4 kPa−1 was achieved over a pressure range from −80 to 0 kPa. Also, it exhibited excellent repeatability and minimal hysteresis. As graphene pressure sensor was exposed to ambient air for 30 days, the relative resistance change was just 2.3%. The resistance of graphene pressure sensor can also keep stable even if the device was stored in a high-temperature or high-humidity environment. Thus, this work provides a promising approach for the practical application of high-performance graphene pressure sensors. [ABSTRACT FROM AUTHOR]

The operation of a capacitorless (1T) dynamic random access memory (DRAM) can be compromised if the storage region is located near metal–semiconductor junction in a reconfigurable field-effect transistor (RFET). Through subtle modifications, without affecting current drive, capacitance, and reconfigurable features, the present work showcases feasible 1T-DRAM operation in a RFET with an intentionally misaligned polarity gate. Analysis based on device physics and operation, highlights 1T-DRAM for standalone and embedded applications with impressive performance indicators: sense margin $\ge 6~\mu \text{A}/\mu \text{m}$ , retention time ≥16 ms (for embedded), and ≥64 ms (for standalone) at 85 °C, current ratio of ~104 along with a low write (~ 1 ns) and read (~ 2 ns) time. Guidelines in terms of scalability of total length and biases for implementing 1T-DRAM cell are presented. [ABSTRACT FROM AUTHOR]

Threshold switching (TS) devices based on NbOx materials show intriguing potential for constructing artificial neurons in a neuromorphic machine. However, the high electroforming voltage, the low TS yield, and the poor device uniformity hinder the practical application of NbOx-based TS devices. In this work, we systematically investigate the effect of film composition on device performance by adjusting the oxygen contents in the NbOx films. The electroforming voltage decreases with lowering the oxygen content, and the forming yield for activating TS behavior increases without an additional reset process. Moreover, we propose a stacked method by inserting a NbOy layer with high oxygen content between the low oxygen NbOx layer and the bottom electrode. The intercalated NbOy layer serves as a virtual bottom electrode after breakdown, enhancing the local electrical field and improving cycle-to-cycle stability and device-to-device uniformity. These results demonstrate that the device performances are greatly improved by optimizing the oxygen content and structure, guiding for practical applications of NbOx-based TS devices in neuromorphic computing. [ABSTRACT FROM AUTHOR]

The collector engineered bidirectional insulated gate bipolar transistor (CEB-IGBT) with p-buffer and semi-superjunction (Semi-SJ) is proposed. The structural modification at collector side provides support to reverse breakdown voltage ($\text {BV}_{R}$) in two ways. First, the p-buffer layer allows the device to deplete completely and eliminates premature breakdown effects. Second, the Semi-SJ region introduces an electric field component in the ${x}$ -direction (${E}_{X}$) in order to further improve the $\text {BV}_{R}$. The overall increased electric field, which is a resultant of ${E}_{X}$ and ${E}_{Y}$ , improves $\text {BV}_{R}$ by 53.83% compared to nonpunchthrough IGBT (NPT-IGBT). The efficient potential distribution in the drift region provides support to forward breakdown ($\text {BV}_{F}$) as well. The n-layer below p-body acts as a field stop (FS) layer, which reduces the leakage current during the OFF-state condition. The p-buffer, which injects higher minority charges along the drift side and n-layer with charge storage effect collectively, provides conductivity modulation in the epitaxial region in order to increase current handling capability. This high collector current density leads to reduce ${V}_{ \mathrm{\scriptscriptstyle ON}}$ by 14.5% compared to NPT-IGBT. Furthermore, the charge coupling effect of Semi-SJ region enables the proposed device to turn-off quickly with higher pillar doping and reduces turn-off loss (${E}_{ \mathrm{\scriptscriptstyle OFF}}$) in comparison with NPT-IGBT. [ABSTRACT FROM AUTHOR]

The impact of process-induced inclination angle ($\theta $) of nonvertical sidewalls of the fabricated quadruple gate (QG) metal–oxide–semiconductor field-effect transistor (MOSFET) on subthreshold characteristics has been analytically modeled and analyzed using the equivalent width, equivalent oxide, and coupling between the two equivalent double gate (DG) MOSFETs. A quasi-3-D scaling length model has been formulated accounting $\theta $ and corner gates, which was subsequently applied to derive the channel center potential, threshold voltage, subthreshold current, subthreshold swing (SS), and noise margin (NM) for subthreshold logic applications of trapezoidal (Tz) gate-all-around (GAA) MOSFETs. The newly formulated models were successfully verified using TCAD calibrated to the experimental results of our fabricated QG-MOSFETs. We found that for channel length, ${L}_{g}$ = 50 nm, Fin height, ${H}_{Fin}$ = 20 nm, and Fin top width, ${W}_{top}$ = 10 nm, the potential barrier of TzGAA MOSFET falls by 4.7% at $\theta =30^\circ $ compared to rectangular cross section, thereby, deteriorating the short-channel immunity of the device. The SS roll-up, threshold voltage roll-off, drain induced barrier lowering (DIBL), voltage transfer curve (VTC) of subthreshold CMOS inverter, and NM degradation due to inclined sidewalls have been calculated using the developed models. According to the scaling theory, the minimum ${L}_{g}$ for a NM degradation of 5 mV is 30.5 nm corresponding to $\theta =0^\circ $ , and 42.7 nm at $\theta $ = 30° for ${H}_{Fin}$ = 20 nm. [ABSTRACT FROM AUTHOR]

By means of Monte Carlo simulations of gallium nitride (GaN) planar Gunn diodes, the epilayer structure on which they are fabricated is optimized in order to achieve ultrahigh-frequency oscillations. Practical considerations, such as the limitations of the technological fabrication process and the mitigation of the huge self-heating effects expected to appear in the devices, have been also contemplated for the choice of the optimal epilayer parameters. The best results are obtained for an active layer thickness of 150 nm with doping of 5 $\times 10^{{18}}$ cm−3, which would provide 350 GHz Gunn oscillations when using a contact separation of $0.5~\mu \text{m}$. [ABSTRACT FROM AUTHOR]

To realize the complementary circuit on the GaN-on-Si platform, an investigation of p-channel heterostructure field-effect transistors (p-HFETs) is necessary. In this study, an analytical model for the estimation of the threshold voltage (${V}_{\text {TH}}$) for GaN-based p-HFETs was developed. In this model, the impact of polarization charges at different interfaces, the influence of interface charges at oxide/GaN interface, as well as the out-diffusion effect of Mg dopant in the p-GaN layer were all taken into consideration for systematic exploration. Herein, GaN-based p-HFETs were fabricated to verify the relationship between the ${V}_{\text {TH}}$ and the thickness of the GaN channel layer by using the proposed model. The ${V}_{\text {TH}}$ model was further confirmed through TCAD simulations. The influences of the thickness of oxide layer, Mg doping concentration in p-GaN layer, and the Al mole fraction of AlxGa $_{{1}-{x}}\text{N}$ layer on ${V}_{\text {TH}}$ were also discussed in detail. The model serves as more accurate guidance for the optimization of such p-HFETs design and complementary circuits. [ABSTRACT FROM AUTHOR]

The design, fabrication, and cold test of a mode generator to excite the circular TE01 or TE21 mode for ${H}$ -band (220–325 GHz) gyrotron traveling-wave-tubes (TWTs) are presented in this article. The mode generator is composed of two parts: a TE $^{\Box }_{10}$ –TE $^{\Box }_{20}$ mode converter based on a two-way H-T junction power divider and a TE $^{\Box }_{20}$ –TE $^{\circ }_{01}$ /TE $^{\circ }_{{21{ }}}$ mode converter with a tapered waveguide ($^{{\Box { }}}$ and ° represent the rectangular and circular waveguide, respectively). By adjusting the ratio of width and height of the tapered waveguide, the TE $^{\circ }_{01}$ or TE $^{\circ }_{\vphantom {D_{l}}21}$ mode could be excited. The primary advantage of this technique is that it has a relatively compact and easy-to-fabricate configuration, which is especially useful in the terahertz-band. To verify the design, two identical mode generators joined back-to-back were manufactured and measured. The measured ${S}$ -parameters were in good agreement with the simulated ones, which predicted that the TE $^{\circ }_{\vphantom {D_{l}}21}$ /TE $^{\circ }_{01}$ mode generator obtained a 1-dB transmission bandwidth of ~38.1 and ~48.0 GHz, respectively. Meanwhile the reflection coefficient $S_{11}$ was below −10 dB over that bandwidth. [ABSTRACT FROM AUTHOR]

2-D-material channels enable ultimate scaling of MOSFET transistors and will help Moore’s Law scaling for years. We demonstrate the state of both n- and p-MOSFETs using monolayer transition metal dichalcogenide (TMD) channels of sub-1 nm thickness and manufacturable CVD, molecular beam epitaxy (MBE), or seeded growth. nMOS devices on transferred MBE MoS2 using novel contact metal show low variation, one of the lowest reported contact resistances (${R}_{\text {c}}$) of 0.4 $\text{k}\Omega \cdot \mu \text{m}$ , low hysteresis, and good subthreshold swing (SS) of 77 mV/dec. pMOS devices using CVD WSe2 show 89 mV/dec SS, best reported for pMOS on grown films, but ON-current remains behind nMOS. We show ${R}_{\text {C}}$ is improved by $5\times $ by using a bake process prior to contact metal deposition. Transfer-free, area-selective seeded growth techniques for WS2 and MoS2 are demonstrated as options for wafer-scale TMD channel growth. WS2 transistors achieve 10 $\mu \text{A}/\mu \text{m}$ ON-current, highest reported on WS2 using seeded growth. A new capacitance method is shown to monitor 2-D material contact interface quality. Gate-oxide interface engineering through metal seeding and atomic layer deposition (ALD) demonstrates that a single 2-D channel material can selectively make pMOS or nMOS transistors, alike Si CMOS, and can also be used as a method to achieve p-type doping. We compare back-gated bare channel devices with dual-gate devices and observe hysteresis-free operation and an improvement in mobility with proper passivation. [ABSTRACT FROM AUTHOR]

A novel width-modulated sine waveguide traveling-wave tube (SWGTWT) is proposed for G-band operation. The broadband single-section and two-section SWGTWT are analyzed, which has the potential to address various technological challenges in the THz regime, such as fabrication difficulty, reflection, and attenuation of RF power. The two-section design has separate RF structures for input and output sections of the TWT, which helps to eliminate undesired reflection during high-power operation. The width modulation is employed to enhance the interaction impedance and also to realize the flat dispersion characteristic of the slow wave structure (SWS). The fabrication feasibility of the structure is demonstrated by fabricating the scaled structure at the Ku-band. A 20.4-kV, 50-mA cylindrical beam is employed in the particle-in-cell (PIC) simulation. The single-section structure offers a maximum power of 53 W with a 5.19% efficiency at 210 GHz. The peak power and a 3-dB bandwidth for the two-section structure are estimated to be 38.9 W and 32.5 GHz, respectively. The structure produces greater than 10 W of output power over a 46-GHz frequency band covering the range of 200–246 GHz. [ABSTRACT FROM AUTHOR]

We report high-performance amorphous Indium-Gallium-Zinc-Oxide nanowire field-effect transistors ($\alpha $ -IGZO NW-FETs) featuring an ultrascaled nanowire width (${W}_{{\mathrm {NW}}}$) down to ~20 nm. The device with 100 nm channel length (${L}_{{\mathrm {CH}}}$) and ~25 nm ${W}_{{\mathrm {NW}}}$ achieves a decent subthreshold swing (SS) of 80 mV/dec as well as high peak extrinsic transconductance (${G}_{m,{\mathrm {ext}}}$) of $612~\mu S/\mu \text{m}$ at a drain–source voltage (${V}_{{\mathrm {DS}}}$) = 2 V ($456~\mu S/\mu \text{m}$ at ${V}_{{\mathrm {DS}}}$ = 1 V). The good electrical properties are enabled by using an ultrascaled 5 nm high- ${k}$ HfO2 as the gate dielectric, a water-free ozone-based atomic layer deposition (ALD) process, and a novel digital etch (DE) technique developed for indium-gallium-zinc-oxide (IGZO) material. By using low-power BCl3-based plasma treatment and isopropyl alcohol (IPA) rinse in an alternating way, the DE process is able to realize a cycle-by-cycle etch with an etching rate of ~1.5 nm/cycle. The scaling effects on device performance have been analyzed as well. It shows that the downscaling of ${W}_{{\mathrm {NW}}}$ improves the SS notably without sacrificing ON-state performance, and the shrinking of ${L}_{{\mathrm {CH}}}$ boosts the ${G}_{m,{\mathrm {ext}}}$. The ultrascaled $\alpha $ -IGZO NW-FETs could play an important role in applications where high performance and high density are highly desired. [ABSTRACT FROM AUTHOR]

This article presents the design and fabrication results of the silicon carbide (SiC) super-junction Schottky barrier diode (SBD). The impact of two key device structure parameters, i.e., mesa width (MW) and trench width (TW), on the device forward and reverse performance is studied by numeric simulations and measurements. Furthermore, a simple and efficient termination structure, i.e., wide-trench termination, is proposed to protect the device edge. With this termination, the simulated device breakdown voltage is significantly increased from 1423 to 2600 V with a wide-trench termination width (WTW) larger than $20~\mu \text{m}$. The outermost MW (OMW) of the transition region is also investigated. It is found that the narrower OMW can mitigate the electric field crowding at the top of the outermost mesa and reduce the electrical stress of the dielectric. Devices with different structural parameters are fabricated and measured. The device with WTW $= 50\,\,\mu \text{m}$ and the optimum OMW demonstrates the highest breakdown voltage of 1920 V. The specific ON-resistance (${R}_{{\rm \scriptscriptstyle {ON}},\text {sp}}$) of this device is 1.6 $\text{m}\Omega \cdot $ cm2. Subtracting the substrate resistance, the ${R}_{{\rm \scriptscriptstyle {ON}},\text {sp}}$ is only 1.2 $\text{m}\Omega \cdot $ cm2. Such device performance successfully breaks the theoretical 1-D limit of the SiC unipolar device. Furthermore, the leakage current path of the fabricated device is investigated by thermal emission microscope (EMMI). Future improvements to reduce the leakage current are also provided. [ABSTRACT FROM AUTHOR]

In fluid rheological studies, viscosity measurement is one of the most significant phenomena leveraged in a variety of studies. Viscometers are broadly employed in a wide range of sensing and monitoring applications, such as biochemical diagnostics and numerous adulteration detections. Therefore, it is pertinent to develop a miniaturized, automated, and cost-effective device that can measure the fluid viscosity from small samples. In this work, for fluid viscosity measurements, a new low-cost automated electro-microfluidic viscometer (EMV) has been fabricated on a hydrophilic laser-induced graphene (LIG) platform with integrated electronics to monitor viscosity from a small sample of fluid of $1.5~\mu \text{L}$. The principle of operation of the fabricated device is based on the modified Hagen–Poiseuille equation, which imitates the Ostwald viscometer. Under laminar flow, the proposed standalone and portable device automatically evaluates the travel time of fluid with high accuracy. This travel time was used to obtain viscosity accurately of various fluids, such as water, milk, and acetic acid, with a minimum error of up to ±1.08%. Overall, the device provides a pathway for a convenient, robust, and plug-and-play platform for different applications, including various adulteration monitoring and biosensing. [ABSTRACT FROM AUTHOR]

The rapid growth of flexible electronic devices greatly stimulates the demand for planer and microscale energy storage devices. Flexible and planer microsupercapacitors (MSCs) with their interdigitated electrode architecture serve as a promising platform for energy and power sources for flexible microelectronics. This study reports the fabrication of in-plane interdigitated structure-based MSC device utilizing TiO2 nanofibers (NFs) as an active material via binder-free, cost-effective, and environmental-friendly electrophoretic deposition (EPD) technique. The fabricated MSC device delivers an excellent areal capacitance (${C} _{A}$) of 9.4 mF/cm2 at 10 mV/s scan rate. Furthermore, the flexible MSC device shows 80% capacitance retention after 10 000 successive GCD cycles and 73% retention after 2000 bending cycles. Moreover, the maximum areal energy density and areal power density obtained for the device are $0.64~\mu $ Wh/cm2 and $307.2~\mu \text{W}$ /cm2, respectively. [ABSTRACT FROM AUTHOR]

This report demonstrates the fabrication and performance of a novel, transient, stable breath sensor based on black phosphorus quantum dots (BPQDs) and polyvinyl alcohol (PVA) composite. BPQDs were utilized as the conduction medium, while the PVA provides a flexible substrate that disintegrates in water. The device presents an innovative solution to black phosphorous (BP) degradation in which the copper (Cu) contacts are placed within the filler of the composite, ruling out the effects of surface degradation in the evaluation of the device performance. Stability studies at the end of eight weeks have been included wherein a negligible change in device performance to breath is observed. The sensor demonstrates chemiresistive properties with a change in resistance of ~100% to exhaled breath. The fabricated device was successful in identifying different breath patterns by monitoring the amplitude and the frequency of the device’s current change upon exposure to breath. The fabricated device achieves complete transience in ~10 min when immersed in water. The study opens up possibilities for applications in the fields of biosensors, military, and consumer electronics. [ABSTRACT FROM AUTHOR]

In this article, tight binding model and nonequilibrium Green’s function technique have been used to investigate the electronic properties of armchair black phosphorene nanoribbons in ballistic transport regime as well as in the presence of line-edge roughness. The results indicate that although the ballistic electrical conductance is almost independent of ribbon width for the narrow ribbons and has no significant changes by temperature, at the presence of line-edge roughness, the electrical conductance varies by temperature and could be highly dependent on the ribbon width, especially in the case of long channels. In contrast to the graphene nanoribbons in which the line-edge roughness limited effective mean free path (MFP) is about tens of nanometer, in the black phosphorene nanoribbons, the effective MFP could be as high as ${2}~\mu \text{m}$ in ribbons with width of about 5 nm. For ribbons wider than 3 nm, the line-edge roughness scattering is almost negligible in comparison with electron–phonon scattering. [ABSTRACT FROM AUTHOR]

A novel compact realization of the XNOR/ XOR function is demonstrated with multimodal transistors (MMTs). The multimodal thin-film transistors (MMT’s) structure allows efficient use of layout area in an implementation optimized for unipolar thin-film transistor (TFT) technologies, which may serve as a multipurpose element for conventional and emerging large-area electronics. Microcrystalline silicon device fabrication is complemented by physical simulations. [ABSTRACT FROM AUTHOR]

In this study, we examine the effect of oxygen vacancies (${V}_{O}$) near the back surface of p-type tin monoxide (SnO) semiconductors on the device performance of its thin-film transistors (TFTs). Non-stoichiometry of the SnO surface layer was controlled through oxidant exposure conditions during alumina (Al2O3) growth using plasma-enhanced atomic layer deposition (PEALD). During the initial period of Al2O3 deposition, trimethylaluminum precursors absorbed oxygen from the SnO layer and created the ${V}_{O}$ , which can form a ${V}_{O}$ -rich region at the Al2O3/SnO interface. By modulating the oxygen plasma density during the PEALD process, the ${V}_{O}$ was effectively controlled, allowing the electrical characteristics to transition from ambipolar behavior to ${p}$ -channel only conduction. This study demonstrates the importance of the back surface of SnO, suggesting a new perspective of ambipolar behavior in p-type SnO semiconductors. [ABSTRACT FROM AUTHOR]

This work explores the fabrication and characterization of an ionic liquid channel field effect transistor (FET) incorporated within the trench structure on SiO2. The trench structure allows any liquid to be accommodated, thereby eliminating the mold creation on the device or the requirement for an intricate architecture to store liquid. For the fabrication of the trench, we followed a standard photolithography process with the help of selective etching of aluminum and SiO2. The fabricated trench surface is characterized using atomic force microscopy (AFM) and contact angle analysis. The electrical characterization of the proposed FET structure is also performed with 0.01-mM potassium chloride (KCl) solution as an ionic channel. We tested both the n-FET and p-FET type characteristics which can be controlled by the back gate biasing condition. The dc characterization shows a high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of 105 for both the n-FET and p-FET. The device further shows an improvement in K+ mobility and Cl− mobility of $2.24 \times 10^{-4} {\mathrm {m}}^{2}/{\mathrm {Vs}}$ and $4.96 \times 10^{-4} {\mathrm {m}}^{2}/{\mathrm {Vs}}$ , respectively. We also carried out the FET structure modeling to estimate the effective ${C}_{{\mathrm {ox}}}$ for the trench SiO2 structure. It is observed that the total capacitance after the inclusion of Debye length is $1.29 \times 10^{-4} {\mathrm {F/m}}^{2}$. Furthermore, the number of ions is also calculated from the electrical characteristics, and it is almost comparable with the number of ions in the molar solution. Overall, the proposed fabricated structure, although simple, enables to accommodate any liquid as a channel and provides an easy way to develop electrolyte-based sensors. [ABSTRACT FROM AUTHOR]

The dual-functional resistive random-access memories (RRAMs) are presented as the nonvolatile switching (NVS) memory and volatile threshold switching (VTS) devices by changing the operation polarities in the identical memory device. The built-in nonlinearity is demonstrated of~102 in NVS for the selectorless memristor, and the selectivity is of ~103 in volatile switching for the selector device application. The crossbar array of HfOx/graphite stacks is implementing an improved read margin with nonvolatile selectorless unit. In comparison with current memory technology, the dual-functional hybrid selectorless memristor in this work is presented by low thermal budget, high ON– OFF ratio (~102), good self-selectivity in selectorless memory (~1012), high selectivity in selection device (~103), and low switching voltage for both memory and selection devices. The dual-functional switching behaviors not only provide the effective ways to 3-D integration for storage class memory, but also for emerging computing paradigms such as in-memory computing and neuromorphic computing applications. [ABSTRACT FROM AUTHOR]

In this article, a new type of metal–insulator–semiconductor (MIS) tunnel diode (TD), trench MIS TD, was investigated. From the current–voltage characteristics, memory retention, and memory endurance measurements, we found that the trench MIS TDs not only have lower reverse bias current, but also show stronger transient current compared to traditional planar structure MIS TDs. For example, in the 1000-cycle memory endurance test, we observed a 25 times larger current window (CW) in trench devices than the CW of planar devices. We attribute the lower reverse bias current to the fewer minority carriers (electrons) in trench MIS TDs, which is supported by the high-frequency capacitance–voltage (C–V) measurement. As for the enhanced transient behavior of trench MIS TDs, we proposed a mechanism based on the understanding of fewer minority carriers in trench devices to explain our observation. Eventually, we examined the effect of different equivalent oxide thicknesses (EOTs) on the CW and found that the trench devices have better CW in a wide EOT range. Because of the enhanced transient behavior leading to better memory CW, trench MIS TDs have the potential to serve as memory devices. [ABSTRACT FROM AUTHOR]

Ubiquitous wireless distribution of multigigabit per second data rate for enabling new 5G and 6G paradigms can be only achieved by exploiting the wide frequency bands available in the sub-THz spectrum (90–305 GHz). The high total attenuation at sub-THz, in particular because of rain and humidity, poses a substantial challenge to achieve long links, not yet resolved because of the lack of amplifiers with adequate transmission power. Sub-THz traveling wave tubes (TWTs) are emerging as key components to ensure high signal-to-noise ratio over a large coverage area or for long distance. This article will describe the design and fabrication of a novel TWT for enabling point to multipoint wireless distribution at ${D}$ -band (141–148.5 GHz). To be suitable for the wireless market, TWTs need to be low cost and easily manufacturable for large-scale production. The proposed ${D}$ -band TWT uses a double corrugated waveguide as slow wave structure and a new electron gun, both designed for easy assembly and low fabrication cost. This article describes the design process, the development of the parts of the TWT, and the first prototype assembly. [ABSTRACT FROM AUTHOR]

A new hydrogen (H2) gas sensor, synthesized with a radio frequency (RF) sputtered cerium oxide (CeO2) thin film and rapid thermal evaporated palladium (Pd) nanoparticles (NPs), is fabricated and reported herein. The employed Pd NPs can effectively increase the surface area/volume (${S}_{A}$ /V) ratio and catalytic reactivity of Pd metal, thereby substantially enhancing the adsorption effect of hydrogen molecules on the device surface and improving the related sensing performance. Energy-dispersive X-ray spectroscopy (EDS), atomic force microscopy (AFM), scanning electron microscopy (SEM), and transmission electron microscopy (TEM) were employed to characterize the related properties of the studied device. Experimentally, a high sensing response of 120.2 under 1% H2/air gas at 350 °C with a relatively shorter response (recovery) time of 5 s (17 s) is obtained. The studied Pd NP/CeO2-based sensor device shows wide operating ranges of temperature (200 °C–400 °C) and hydrogen concentration (10 ppm—1% H2/air). A thermodynamic analysis employed to study the surface coverage of hydrogen molecules is reported in this work. The studied sensor device also exhibits the advantages of a simple structure, easy fabrication process, and relatively low cost. [ABSTRACT FROM AUTHOR]

Three-independent-gate FETs (TIGFETs) are Schottky-barrier-based devices, which can be reconfigured to be either n- or p-type allowing for innovative compact logic gate implementations. In this article, we present an aggressively scaled 10-nm gate-all-around silicon–germanium nanowire TIGFET device evaluated with Synopsys Sentaurus Poisson-based Technology Computer-Aided Design (TCAD) simulations at a 0.7-V nominal supply voltage as typically used at this technology node. The operation of the TIGFET device is described in detail, with particular care given to the majority current contributions for each operating mode. When considering a silicon–germanium channel, the maximum TCAD-simulated current drive is 880.20 and $806.58~\mu \text{A}/\mu \text{m}$ for n- and p-type operation, respectively, thus making TIGFET devices competitive with FinFET technology at the 10-nm node. These simulations are verified using device physics calculations. Further simulations of the carrier densities for each of the TIGFET-operating configurations are performed to confirm that the simulated device is operating as intended. [ABSTRACT FROM AUTHOR]

To achieve lower specific ON-resistance (${R}_{{ \mathrm{\scriptscriptstyle ON},\text {SP}}}$), a novel accumulation lateral double-diffused MOSFET (ALDMOS) characterized by a convex-shaped field plate (CFP) structure is proposed and investigated experimentally. The CFP structure above the ${N}$ -drift region consists of two diodes, with its contact regions embedding into the drain and source region. Hence, the proposed device could shrink the drift length and utilize the drift region effectively to sustain the same level of breakdown voltage in the OFF-state. Furthermore, the CFP structure enables to form a continuous electron accumulation layer at the drift surface in the ON-state. Consequently, the proposed CFP ALDMOS could obtain an ultralow ${R}_{{ \mathrm{\scriptscriptstyle ON},\text {SP}}}$ and achieve a better tradeoff relationship between BV and ${R}_{{ \mathrm{\scriptscriptstyle ON},\text {SP}}}$. The experimental results show that the CFP ALDMOS realizes a BV of 448 V and ${R}_{{ \mathrm{\scriptscriptstyle ON},\text {SP}}}$ of 16.9 $\text{m}\Omega \cdot $ cm2 with an extremely high figure of merit of 11.87 MW/cm2, decreasing ${R}_{{ \mathrm{\scriptscriptstyle ON},\text {SP}}}$ by 55.6% compared with theoretical triple-REduced SURface Field (RESURF) LDMOS at the same BV. [ABSTRACT FROM AUTHOR]

In this article, we have focused on the concept of junction-free transistor to propose and simulate the ultrathin dielectric modulated (DM) bulk-planar junctionless field-effect transistor (BP-JLFET) as a biosensor device. The proposed device is incorporated with a label-free detection of neutral (proteins, enzymes, streptavidin, and APTES) and charged [deoxyribonucleic acid (DNA)] biomolecules in terms of dielectric constant (K) and charge densities (ρ). For the detection of the biomolecules, the nanocavity is formed by etching out the oxide underneath the gate dielectric at source end. The presence/absence of biomolecules has been detected by the factor of sensitivity with the immobilization of dielectric constant (K) and the charge density (ρ) in the formed nanocavity. Moreover, the comparative study of the BP-JLFET, the dielectric-modulated tunnel field-effect transistor (DM-TFET), and the conventional dielectric-modulated field-effect transistor (DM-FET)-based biosensor in terms of their drain current (Ids) and the sensitivity have been carried out. From the study, it can be depicted that the BP-JLFET has higher sensitivity to sense the biomolecules compared to both the DM-TFET and the conventional DM-FET. Furthermore, we have also analyzed the noise characteristics for the simulated structures to measure the ability of the proposed device for sensing the biomolecules in the presence of noise. [ABSTRACT FROM AUTHOR]

A class of vertical 1700-V 4H-SiC superjunction (SJ) Schottky diodes have been simulated and optimized, producing results that are below the unipolar limit, while also ensuring practical and costeffective realization. A conventional vertical SJ is obtained in T-CAD software, using an n-type drift region of 9-μm and etching trenches through this region to the substrate to leave isolated mesa structures. P-columns are then created through implantation into the trench sidewalls. The charge-balanced SJ diode maximizes the breakdown voltage (VBD) and minimizes the specific ON-resistance (RON,SP). However, a narrow implantation window would make the vertical structure hard to fabricate. Therefore, by introducing an angled trench sidewall (α), 10° off vertical, a graded charge profile is introduced reducing VBD by 2.5% and increasing RON,SP by 9%. However, the implantation window is widened by 20% compared with the vertical device, making the successful production of the devices more likely. To rebalance the 10° structure, a 1-μm region of increased n-type doping is introduced at the top of the n-pillar. This partially recovers the lost VBD and RON,SP while maintaining an implantation window wider than the vertical SJ. The balance between RON,SP and implantation window can be tuned depending on the doping of the 1-μm top region. The 10° structure can also be rebalanced by introducing a second 4-μm region of intermediate n-type doping, underneath the 1-μm surface region. This recovers RON,SP, while maintaining an implantation window that is 7% wider. [ABSTRACT FROM AUTHOR]

This article focuses on how to improve the negative capacitance (NC) properties of NMOSFET in the gate-last process flow. The impacts of the HfZrO ferroelectric film thickness, metal gates with different work functions, stress of filled metal gate, the thickness of seed layer underneath HfZrO etc. on NC effect are investigated, and the corresponding possible mechanisms are discussed. These techniques have been successfully applied to the fabrication of NC-NMOSFETs with physical thickness 1.5-nm HfZrO, and underneath with 1.0-nm ZrO2 seed layer. The NC-NMOSFETs with much improved subthreshold swing (SS) of 38.6 mV/decade and nearly hysteresis free are developed with a gate length of 900 nm, and the SS is over 40 mV/decade smaller than that of the control-2 NMOSFETs with 2.5-nm HfO2 gate dielectric only. [ABSTRACT FROM AUTHOR]

Main issues of large-scale and large-area production of the solar cell are the high cost of fabrication due to the involvement of costly and sophisticated equipment and the use of costly materials in fabrication. Here, an effective and low-cost approach has been proposed for the fabrication of reduced graphene oxide (rGO)–ZnO/silicon heterostructure solar cells. The hybrid composite of rGO–ZnO has been synthesized by using a low-cost chemical method and deposited on a pcSi substrate by a sol-gel process for application in heterojunction solar cells. The morphology, crystal phase, surface functional groups, and optoelectronic properties of the heterostructure have been investigated by using SEM, XRD, the Fourier transform infrared (FTIR) spectroscopy, the Raman spectroscopy, and the UV-vis spectroscopy. The I – V characteristics of the fabricated heterojunction cell show a power conversion efficiency of 4.35% (Voc = 0.51 V, Jsc = 14.47 mA ⋅ cm−2, and fill factor (FF) = 51.60) due to having enhanced conductivity/charge transfer efficiency by the hybrid semiconductor. This simple approach assures the low-cost mass production of heterojunction solar cells. [ABSTRACT FROM AUTHOR]

To scale the ferroelectric random access memory (FeRAM) technology toward 28 nm or beyond, it is critical to develop stacked capacitor (with sufficient surface area) to allow good sense margin for the 1-transistor- 1-capacitor (1T1C) bit cell. Therefore, to enable 3-D integration in back-end-of-line (BEOL) process, it is essential to optimize the fabrication recipes in low-thermal budget (< 400 °C). In this regard, we investigated the low-temperature process for ferroelectric Hf0.5Zr0.5O2 (HZO) capacitor with the plasma-enhanced atomic layer deposition (PEALD). It was found that, with sufficient annealing time (>50 s) in low temperature (~ 350 °C), the ferroelectric properties of HZO could be fully manifested. No degradation is shown in the remnant polarization (Pr) under the optimized low-temperature process. Furthermore, the retention/endurance characteristics with different Pr states were measured to determine the minimally required write voltage. Finally, the SPICE simulation is conducted to evaluate the sense margin of the projected 28-nm 1T1C array with stacked cylindrical capacitors using the measured Pr drift behavior over time. [ABSTRACT FROM AUTHOR]

A multifaceted simulation procedure, addressing the electron beam properties, the beam-wave interaction, and the internal losses, has been used for the simulation of the experimental operation of a 1.5-MW 140-GHz short-pulse preprototype gyrotron. The preprototype is related to the development of 1.5-MW gyrotrons for the upgrade of the electron cyclotron resonance heating system at the stellarator W7-X. A very good reproduction of experimental results has been achieved by simulation, without resorting to arbitrary speculations. This validated the numerical tools as well as the design and fabrication of the short-pulse preprototype, which fully reached the target of efficient 1.5-MW operation in millisecond pulses. Special attention has been given to simulating the possibility of parasitic after-cavity interaction in the gyrotron launcher. Also, parasitic backward-wave excitation in the gyrotron cavity has been demonstrated by simulation, at a frequency and voltage range in agreement with experimentally observed parasitic oscillations. This offers an additional possibility with respect to the origin of deleterious parasitic oscillations in high-power gyrotrons, which are usually attributed mainly to the gyrotron beam tunnel. [ABSTRACT FROM AUTHOR]

We present the experimental demonstration of a traveling-wave tube (TWT) power amplifier operating in the W-band (75–110 GHz) frequency range. The device is based on a serpentine waveguide (SWG) amplification circuit, a slow wave circuit type capable of high power and broad instantaneous bandwidth in the upper millimeter-wave range. A 20 kV, 140-mA round solenoid-focused electron beam powers the device. At 20 kV, we measure 215 ± 2 W peak RF output power at 93 GHz with 20.1 ± 0.15 dB saturated gain, pulsed at 0.1% duty. We observe 10-GHz instantaneous amplification bandwidth at 100-W minimum output power, covering the range 88–98 GHz. Operating at 20.8 kV, the TWT produces 285 ± 3 W at 91 GHz with 22.4 ± 0.15 dB gain, and 7 GHz, 3-dB bandwidth. The peak electronic efficiency measured is approximately 10%. [ABSTRACT FROM AUTHOR]

In recent years, rising need of microfluidics-based point-of-care devices has led to cost-effective solutions at or near the location of patients. With this motivation, herein, laser-induced graphene (LIG)-based electrochemiluminescence (ECL) system loaded with U-shaped bipolar electrode (U-BPE) has been developed and its application for enzymeless sensing of various biomarkers has been validated. Low-cost and easily available flexible polyimide (PI) sheet has been effectively used for the fabrication of LIG U-BPE ECL device. With optimized speed and power, the ablation of CO2 laser on PI has been carried out to create graphenized driving electrodes and U-BPE in a single step. A cost-effective and portable 3-D printed platform has been developed for image sensing of ECL signals. The bulky power supply was effectively replaced by a dual-functional android smartphone to provide power to the LIG U-BPE ECL sensor and to capture the ECL signals. With this mini-platform, determination of various analytes, such as H2O2, D-glucose, lactate, and choline, has been accomplished in a linear range of 0.1–50, 0.1–70, 1–100, and 1– 100 μM with limit of detection (LOD) of 4.36, 2.51, 5.32, and 4.01 μ M, respectively. An interference study has been performed and it was found that after adding interfering compounds in analytes, ECL signal intensity was reduced to less than 5%. Hence, it was proven that LIG U-BPE ECL device was very selective to different analytes concerning to their voltages. [ABSTRACT FROM AUTHOR]

The threshold voltage (Vth) distributions of ground-select-line (GSL) cells and edge dummy (DMY0) cells in a 3-D NAND flash memory are investigated. We characterize the Vth distributions in 3-D NAND flash samples with different fabrication processes and bitline voltages. Large DMY0 and GSL Vth distribution tails are observed in certain fabrication process and operation voltage conditions. The DMY0 Vth tail is attributed to a random distribution of grain boundary (GB) traps in a poly-silicon channel between GSL and DMY0. The GSL Vth tail is affected by ion implant energy in an epitaxial silicon layer underneath a GSL. A 3-D TCAD simulation is performed to study the effects of a GB trap position and a bitline voltage on the Vth distribution of DMY0. The influence of an implant dose profile in the epitaxial silicon on the GSL Vth distribution is also analyzed by 3-D simulation. The GSL and the DMY0 Vth distributions can be significantly improved by optimizing a fabrication process and choosing an appropriate bitline voltage. [ABSTRACT FROM AUTHOR]

In this article, we demonstrate atomic-layer-deposited (ALD) indium oxide (In2O3) transistors with a record high drain current of 2.2 A/mm at VDS of 0.7 V among oxide semiconductor transistors with the enhancement-mode operation. The impact of back-end-of-line (BEOL) compatible low-temperature annealing is systematically studied on these highly scaled In2O3 transistors with channel length (Lch) down to 40 nm, channel thickness (Tch) down to 1.2 nm, and equivalent oxide thickness (EOTs) of 2.1 nm, at annealing temperatures from 250 °C to 350 °C in N2, O2, and forming gas (FG, 96% N2/4% H2) environments. Annealing in all different environments is found to significantly improve the performance of ALD In2O3 transistors, resulting in enhancement-mode operation, high mobility, reduced bulk and interface trap density (Dit as low as 6.3 ×1011 cm−2 ⋅ eV−1), and nearly ideal subthreshold slope (SS) of 63.8 mV/dec. Remarkably, the ALD In2O3 devices are found to be stable in hydrogen environment, being less affected by the well-known hydrogen doping issue in indium–gallium–tin-oxide (IGZO). Therefore, low-temperature ALD In2O3 transistors are highly compatible with the hydrogen-rich environment in BEOL fabrication processes. [ABSTRACT FROM AUTHOR]

We demonstrate the bistable microelectromechanical system (MEMS) sleep-transistor for CMOS integrated circuits (ICs). The sleep transistor has infinite sleep mode resistance and ~2.5-Ω resistance in active mode. The hold bias in active mode is zero for the bistable MEMS sleep transistor. The proposed bistable MEMS switch is an ideal candidate for gating the power-hungry digital circuits. The dynamic random access memory (DRAM) supply rails gated with bistable MEMS sleep transistors offer ~6 order reduction in refresh rate. This article also reports on the design guidelines for the CMOS compatible fabrication of bistable MEMS sleep transistor. Only ~0.31 pJ of energy is consumed, in toggling between the modes of bistable MEMS sleep transistor. The MEMS gate can drive large area CMOS circuit blocks with fuse current density of ~0.5 mA/μm2. Furthermore, the fabrication of the bistable MEMS sleep transistor is critical in the aspect that its design is a play between restoring and adhesion forces. [ABSTRACT FROM AUTHOR]

We investigate the effect of channel layer thickness on effective mobility (μeff) in the sub-10-nm regime of amorphous indium–gallium–zinc–oxide thin-film transistors (α-IGZO TFTs). TFT devices with extremely scaled channel thickness tα-IGZO of 3.6 nm were realized, exhibiting low subthreshold swing (SS) of 74.4 mV/decade and the highest effective mobility μeff of 34 cm2/V ⋅ s at a carrier density NCarrier of ~ 5 × 1012 cm−2 for any kind of α-IGZO TFTs having sub-10-nm tα-IGZO. No significant degradation of μeff is observed as α-IGZO thickness reduced from 6 to 3.6 nm. By scaling down the channel length LCH to 38 nm, high extrinsic transconductance (Gm, max) of 125 μs/μm (at VDS of 1 V) and ON-state current ION of 350 μA/μm at VGS – VT of 3 V with VDS of 2.5 V are achieved. [ABSTRACT FROM AUTHOR]

In this article, a novel planar InAs/GaSb heterojunction face-tunneling FET (HFTFET) is proposed for device performance improvement. As is known in previous studies, the entire tunneling junction of HFTFET can be controlled by gate effectively and uniformly, and therefore, the large effective tunneling area and extremely steep turn on/off switch would be achieved. However, the leakage current between source and drain degrades the OFF-state characteristics and turn on/off switch greatly. Hence, an implanted drain is introduced in the proposed InAs/GaSb HFTFET for reducing the leakage to optimize the performance, which also makes the fabrication process compatible with the standard CMOS process platform. Consequently, large tunneling current, steep subthreshold swing, and small leakage current can be obtained simultaneously, which would further promote the development of tunnel field-effect transistors (TFETs) and their ultralow-power applications. [ABSTRACT FROM AUTHOR]

Highly sensitive and cost-effective flexible piezoresistive sensors are pursued as essential components of electronic skin (e-skin) for a variety of applications such as soft robotics and body prosthesis. A common strategy for achieving high sensitivity of these sensors is to fabricate their electrode material with complex 3-D microstructures, but manufacturing cost-effective micro-structured sensors with high reliability and reproducibility is a challenge. Herein, a robust approach for producing high-reproductive microstructured polydimethylsiloxane (PDMS) films composing the sensors is proposed, based on silicon molds with a honeycomb-like architecture fabricated rapidly and cost-effectively at a standoff distance by femtosecond laser pulses in the self-channeling regime. Single-walled carbon nanotubes (SWNTs) are embedded in the micro-structured PDMS films composing sandwich-structural flexible piezoresistive sensors. The sensing devices exhibit good performance with high sensitivity, fast response time, and excellent stability and are used with success for the detection of hand motion pressure and blood pressure at the wrist, thus showing a great potential as components of e-skin for detection of various human motions. [ABSTRACT FROM AUTHOR]

This article presents a terahertz integrated cavity bandpass filter based on cyclic etched silicon carbon (SiC) via-holes. Solutions are discussed in detail, including design, fabrication, and optimization. The fabrication procedures of the integrated filters are specially optimized, which are fully compatible with that of the common terahertz monolithic integrated circuit. The cyclic via-hole etching technique based on inductively coupled plasma (ICP) is proposed, which achieves via-holes with a controllable inclination on SiC substrate. Measurements show that the insertion loss of the cavity integrated filter is only 1.55 dB at 185 GHz, with a relative bandwidth of 9.7%. Two transmission zeros are introduced by the over-moded technique, achieving the out-of-band suppression of the filter higher than 40 dB. Compared with the traditional terahertz cavity filters, the integrated cavity on SiC substrate provides similar electric performances and better integration but with the one-thousandth of the volume. [ABSTRACT FROM AUTHOR]

In this article, binder-free TiO2 nanofiber-based electrodes have been fabricated via fast, cost-effective, and environmental-friendly electrophoretic deposition (EPD) technique on a graphite substrate for energy storage devices such as supercapacitor for low-power electronic applications. The experimental studies confirm that the surface morphology of the fabricated electrodes is greatly dependent on the EPD voltage, which is one of the key factors, which controls the electrochemical performance of the TiO2 nanofibers-based electrodes. The binder-free, TiO2 nanofiber-based electrode exhibits a specific capacitance of 408 Fg−1 ± 5 Fg−1 at 1 Ag−1current density. The fabricated electrode shows a higher diffusion coefficient ~ 2.81 × 10−10 , which facilitates an easy diffusion of electrolytic ions inside the sample and a very small relaxation time constant (τo = 98 ms), which allows the system to deliver its energy in a quick manner. Moreover, the fabricated electrode retains 85 % of its initial capacitance value after 1000 successive cycles. It can be believed that the reported EPD technique can be used to fabricate the electrodes for energy storage devices for portable low-power electronic applications. [ABSTRACT FROM AUTHOR]

Details of a large-area-compatible sub-600 °C process for the fabrication of high mobility field-effect transistors on single crystalline silicon are presented. It is shown that lift-off and solid-phase-epitaxy (SPE) can be used in conjunction with plasma enhanced chemical vapor deposition (PECVD) to create MOSFET transistors with mobilities comparable to other high-performance techniques. Furthermore, use of an amorphous silicon/silicon oxynitride (SiOxNy) sacrificial bilayer is shown to make the process capable of self-aligned silicidation. The topography of the deposition is studied using cross-sectional scanning electron microscopy (SEM). It is shown that a successful lift-off can be achieved through the proper design of the sacrificial bilayer despite the high degree of step coverage generally exhibited by PECVD films. Cross-sectional transmission electron microscopy (TEM) is used to reveal the microstructure of the epitaxy and silicidation. Current-voltage characteristics of the fabricated transistors are presented and the field effect mobility of electrons on the fabricated devices is reported. The developed process is particularly useful in applications where high mobility transistors need to be built on silicon/nonsilicon hybrid platforms that exclude high processing temperatures. [ABSTRACT FROM AUTHOR]

Here, an ultrafast direct laser patterning technique to fabricate a low-cost microsensor and its application for formaldehyde detection are reported. The patterns of microheater and interdigitated electrodes (IDEs) were realized using laser micromachining techniques by ablation of gold thin film on alumina substrate. The thin film of gold microheater showed good stability up to 300 °C with a fast response time of 80 s and temperature coefficient of resistance (TCR) was calculated as 1.37 × 10−3/°C. Moreover, gold microheater exhibited long-term reliability under self-heating mode with a negligible resistance drift < 0.5% over a period of 330 h at 250 °C through consuming low power with a heating efficiency of 0.23 °C/mW. Thermal imaging camera revealed the uniform temperature distribution with negligible heat gradient profile over the whole microsensor platform. To state-of-the-art gas sensing application of this coplanar sensing platform, a nanostructured SnO2 was deposited on IDE, which exhibited high sensitivity (13.96% ppm−1) to formaldehyde even to detect sub-ppm concentrations with fast response (32 s) and recovery kinetics (72 s). Moreover, the microsensor was also used on-site rapid screening for the detection and quantification of formaldehyde concentration in formalin-treated fish sample. [ABSTRACT FROM AUTHOR]

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. We then performed 400 virtual experiments comprising seven sources of process variation. Using this virtual fabrication technique, we were able to identify a minimum gate-to-source/drain spacer thickness for a high-temperature post-EPI rapid thermal anneal (RTA) anneal process that avoided device subthreshold slope penalties. The model allowed us to determine the optimal Si recess depth target and process window prior to source/drain epitaxy. We obtained these results by reviewing device performance as a function of statistical process sensitivity and highlighting key process parameters requiring variation control. These experiments would have been impractical to perform in an actual fab, due to the time, cost, and equipment requirements of running 400 fab-based process variation experiments for each process parameter. This methodology can be used to avoid wafer-based testing during early technology development. [ABSTRACT FROM AUTHOR]

This article reports the demonstration and fabrication of 400–600 V, 4H-SiC lateral MOSFETs on 6-in, N+ substrates. The P-top was implanted on an N-drift region to create a single reduced surface field (RESURF) structure to alleviate the electric field on the surface. The different layout methodologies (source-centered and drain-centered) for making lateral MOSFETs are discussed. The process and design split, such as rapid thermal anneal (RTA) temperatures (900 °C and 1000 °C), different channel designs [accumulation-mode (ACCU) and inversion-mode (INV)], and channel lengths were varied and experimentally analyzed to optimize the device performance. It was confirmed that channel components (channel design and channel length) and RTA temperature are the key ingredients to improve the forward characteristic of the lateral MOSFETs. With the gate to drain length (Lgd) of 5~μm , the breakdown voltage of 600 V was achieved with a voltage supporting capability of 120 V/μm. On the other hand, a lateral MOSFET with Lgd of 2.5~μm and with a further reduced channel length (Lch = {0.3 μm), a record specific ON-resistance of 7.7 m Ω-cm21 00.21a0nd breakdown voltage of 450 V were achieved. Device design, layout, fabrication, and electrical characteristics of the 400–600 V, 4H-SiC lateral MOSFETs are discussed and reported. [ABSTRACT FROM AUTHOR]