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In this article, the impacts of read operation under transient gate voltage sweep on the memory window (MW) of ferroelectric field-effect transistor (FeFET) are systematically investigated. By taking into consideration the polarization switching dynamics, it reveals a significant dependence on the sweep range and rate of gate voltage. With increasing sweep range, the increase of polarization switching leads to the monotonically increasing MW. However, different from sweep range, the MW of FeFET nonmonotonically varies with the increasing sweep rate, which is caused by the competition between decreased polarization switching and increased voltage drop on ferroelectric (FE) layer during forward sweep. Besides, compared with the MW obtained by pulsed gate voltage, it is found that the MW obtained by swept gate voltage can be the smaller one even without the consideration of charge trapping contribution. Furthermore, the impacts of FE switching time on MW are also discussed, indicating that the MW may not always be a constant even under quasi-static sweeping with low sweep rate, and the relationship between sweep rate of gate voltage and switching speed of FE plays a critical role in MW evaluation. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a one-transistor, dynamic random access memory (1T-DRAM) with a very high retention time (RT), vertical twin gates, and a p+/i/n+ nanowire via well-calibrated TCAD simulations. The 4F2-like cell array of the proposed 1T-DRAM can be achieved by realizing twin gates vertically. This 1T-DRAM has a high read current ratio (106 at 25 °C and 1-ns read duration) of state “1” to state “0,” and, even when a severe word line (WL) and bitline (BL) disturbance is considered, exhibits a RT of ~3 s at 25 °C. The long RT, considering a severe WL/BL disturbance, increases the refresh interval time. A systematic analysis shows that the gate length can be scaled down to 10 nm with an acceptable RT (~3 s) to make the fabrication easier by lowering the height of the silicon nanowire. Based on these results, we believe that our proposed 1T-DRAM will be a strong candidate for future DRAM devices. [ABSTRACT FROM AUTHOR]

This article presents the coupled electrothermal simulation results of single event burnout (SEB) in power diode with field limiting rings termination structure. Two different hardening techniques of low carrier lifetime control and introducing the buffer layer are investigated comparatively in both the radiation tolerance improvement and the electrical performance degradation. Our simulations reveal that a significant reduction in the carrier lifetime is needed for the hardening of the power diode using only the carrier lifetime control method. However, the sharp increases in the forward voltage drop and the leakage current at the lower carrier lifetime make this hardening technique unacceptable. On the contrary, the addition of the buffer layer is able to improve the safe operating area under the heavy ion irradiation even up to the breakdown voltage, while the breakdown characteristics and the leakage current are kept unchanged and the increases in the forward voltage drop and the reverse recovery charge can be well controlled. In conclusion, adding a buffer layer is considered a superior and promising hardening technique. [ABSTRACT FROM AUTHOR]

Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (< 10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source- and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with < 5% error in subthreshold slope over a wide range of parameters versus > $2\times $ error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions. [ABSTRACT FROM AUTHOR]

The field effect diode (FED) is an attractive device to use in various digital and analog applications, but all previously proposed FEDs are based on the silicon-on-insulator (SOI) technology. In this article, a bulk version of FED (BFED) is proposed for the first time. Both SOI-FED and BFED are simulated using TCAD tools as a semiconductor drift-diffusion solver. The proposed bulk FED can operate as well as a regular SOI-FED. Most sensitive parameters in the design of the BFED are doping and thickness of $\text{p}^{+}$ -drain and $\text{n}^{+}$ -source. The effect of these parameters is investigated on the output characteristics of the BFED. [ABSTRACT FROM AUTHOR]

A simplified region-wise potential-based analytical model is established for boron (B) or nitrogen (N) substitution doped graphene field-effect transistor (GFET). The closed-form direct analytical relation between graphene channel potential and applied bias condition is developed by imposing the effective approximation for Fermi–Dirac integral function in various regions of operation. The boundary for distinct GFET operating regime is separated based on the position of Dirac point and Fermi energy level with respect to applied bias condition. The semiclassical drift and diffusive transport model is utilized to obtain the drain current. In addition to that, the drift component, diffusion coefficient, and its corresponding current component for B and N substitution doped GFETs have been modeled individually and their influence on total current is discussed. The proposed region-potential-based analytical model has shown good agreement with numerically solved self-consistent model. Also, the physical insights in device design, such as threshold voltage and saturation drain potential model with respect to various doping/device parameters, have been examined. [ABSTRACT FROM AUTHOR]

Properties of space charge limited current and induced particle reflection with a time-varying current injection are investigated by an efficient grid-free numerical approach. Considering a planar diode with a single-frequency current emitted parallel to the upstream electrode surface, we study the current transmission characteristics between two dc biased electrodes and the influence of current frequency and magnitude on the limiting current first leading to electrons reflection. It is found that on account of the time-varying current injection, the limiting current strongly depends on the current frequency and magnitude, as well as the emission velocity of electrons. For the low-frequency limit, the dc component of the limiting current is approximately equal to half of that obtained from the time-independent model. The limiting current increases monotonically with increasing the frequency, and the dc component has a maximum equal to the limiting current obtained from the time-independent model. [ABSTRACT FROM AUTHOR]

A comprehensive physical model is established to understand the device operation and optimization strategy of the ferroelectric tunnel junction (FTJ). This model is capable of simulating write (switching polarity), read [tunnel electroresistance (TER)], and ac transient operations with a good agreement with experiments. The strategy of optimizing the thickness of the ferroelectric layer and nonpolar interfacial layer is discussed for enlarging TER ratio. We also discussed the possible misinterpretation of the measured TER ratio according to our model. [ABSTRACT FROM AUTHOR]

In this article, a novel p-type trapezoidal gate (PTG) lateral double-diffused MOSFET (LDMOS) is proposed and investigated by the 3-D TCAD simulation. The results reveal that the PTG LDMOS boasts a reduced gate-to-drain charge (${Q}_{\text {GD}}$) while maintaining an acceptable breakdown voltage (BV) and specific ON-resistance (${R}_{ \text{ON},\text {sp}}$). Compared with conventional LDMOS, a better tradeoff between the static figure of merit (FOMS, FOM $_{\text {S}}\,\,=$ BV2/ ${R}_{ \text{ON},\text {sp}}$) and the dynamic figure of merit (FOMD, FOM $_{\text {D}} = {R}_{ \text{ON},\text {sp}} \cdot {Q}_{\text {GD}}$) is realized. In the ON-state, the p-type polysilicon gate embedded in the drift region induces multiple plane majority-carrier accumulation layers, leading to a decrease in ${R}_{ \text{ON},\text {sp}}$. In the OFF-state, the metal–insulator–semiconductor (MIS) capacitor, which is composed of extended trench gate, gradual trapezoidal oxide, and N-drift. assists in depleting the drift region. Therefore, the doping concentration of drift region can be significantly lifted, and the BV is increased. Besides, the p-n junction capacitor composed of p-type and n-type polysilicon isolates the field coupling between gate and drain, and the gate-to-drain capacitor (${C}_{\text {GD}}$) is thus reduced. Compared with multiple-plane electron accumulation layer LDMOS (MAL LDMOS) and split triple-gate LDMOS (STG-LDMOS), ${Q}_{\text {GD}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of our proposed PTG LDMOS are shrunk by 34.3% and 54.4%, respectively. In general, the proposed PTG LDMOS achieves a better tradeoff between the static and switching characteristics. [ABSTRACT FROM AUTHOR]

Conventional planar- and trench-gate silicon carbide insulated-gate bipolar transistors (SiC C-IGBT and T-IGBT) suffer from higher turn- OFF loss (${E}_{\text {off}}$) and ON-state voltage drop [ ${V}_{\text {ce(sat)}}$ ]. An improved hybrid-channel injection enhanced modulation 4H-SiC IGBT (HC-IGBT) is proposed and investigated to overcome these shortcomings in this article. The proposed IGBT structure is considered 3-D because the gate wraps around a raised emitter-to-collector channel, instead of residing on top of the channel in the conventional 2-D planar-gate structure. Therefore, multiple gates are ganged together through the same gate electrode to enable more electrons in the “ON” state and provide more path to remove extra holes in the “OFF” state. Comparing with C-IGBT and T-IGBT structure, HC-IGBT gains an improvement of 108% and 21% in a differential specific ON-resistance as well as a turn- OFF loss reduction of 11% and 16%. The industrial figure of merit (IFOM $= {V}_{\text {ce(sat)}}\,\,\times \,\,{E}_{\text {off}}$) of HC-IGBT is reduced by 21% and 22% compared with C-IGBT and T-IGBT, respectively. Meanwhile, the Baliga’s figure of merit (BFOM $= {V}_{\text {BR}}^{{2}}/{R}_{\text {on,sp}}$) shows about 63% and 15% larger than that of C-IGBT and T-IGBT. These results show that HC-IGBT structure has much superior tradeoff between the ON-state voltage drop and turn- OFF loss, indicating the potential for ultrahigh-voltage power electronic of the future. [ABSTRACT FROM AUTHOR]

A novel reverse-conducting insulated gate bipolar transistor (RC-IGBT) with two different collector trench (DCT) is proposed. One of the collector trenches is filled with heavily doped N-type polysilicon (N-poly) and the other is filled with heavily doped N- and P-poly. An electron accumulation layer is formed along the sidewall of trench owing to built-in potential difference between the N-poly and the N-drift region. The electron accumulation layer and collector trenches block the electric field, which behaves just like the N-buffer layer of the conventional RC-IGBT (Con. RC-IGBT). Similarly, due to potential difference between the P-poly and N-drift region, a high-density hole inversion layer is formed to narrow the electron current path as a high resistance. The DCT RC-IGBT achieves snapback-free in a small cell pitch without additional control. Moreover, the DCT RC-IGBT shows better tradeoff between turn-off loss and ON-state voltage drop than that of con. RC-IGBT. For the same forward voltage drop, the turn-off loss is reduced by 26%. [ABSTRACT FROM AUTHOR]

Pseudospark (PS) discharge-based devices are known as excellent source for the generation of high current density and energetic self-focused electron beam in the hollow cathode (HC) phase. In this article, short pulsed ($\!\!\!< 100$ ns) and high energetic (~20 keV) electron beam has been generated and propagated (up to ~60 mm) in the drift region without using any external guiding magnetic field from the four-gap configuration of PS discharge-based plasma cathode electron (PD-PCE) source. The particle-in-cell (PIC) simulation code OOPIC Pro has been employed, whose results have shown the strong dependence of beam propagation into the drift region on the penetration and distribution of potential lines. The combined experimental and simulation investigations have also been carried for the multigap (four-gap) with wide range of external storage capacitor (40 pF–18 nF) and operating voltages (5–35 kV). The circuit parameter controls the appearance of HC phase for the energetic (50%–70% applied voltage) electron beam and conductive phase for the high current (~10 A to ~0.5 kA) electron beam. The potential distribution has clearly indicated that the electron beam with higher applied voltages can propagate more focused in the drift region. The investigations have evidently shown the generation of low energy and high current to high energy and low current electron beams suitable to cover the potential applications in the field of extreme ultraviolet (EUV)/soft X-ray radiation generation, surface modification, and microwave-terahertz radiation generation. [ABSTRACT FROM AUTHOR]

The purpose of this article is to provide insight into ambipolar transport properties of the CMOS-like pseudo-inverter ($\Psi $ -inverter) in silicon-on-insulator (SOI) substrate. The $\Psi $ -inverter demonstrated in this work simply uses three probes instead of metal contact. The channel is controlled by the bottom gate and shows ambipolar conduction. The ambipolar voltage transfer characteristics (VTC) from the Si thin-film layer of the SOI device is extracted. The $\Psi $ -inverter operates both in the first and third quadrants, achieving remarkable gains as high as 25.8 and 936.1 at drain voltages ${V}_{{\mathrm {DD}}}$ = 3 and 7 V, respectively. Moreover, TCAD simulated results are approximated to the experimental data considering top Si interface traps to reveal the electrostatic potential and carrier concentration profiles. Exceptionally sensitive surface properties and high gain of the $\Psi $ -inverter demonstrated in our work enable it a promising candidate for sensor applications. [ABSTRACT FROM AUTHOR]

Phosphorene is a potential material to replace silicon in next-generation electronic devices. However, the material is not favorable for device applications due to its gradual degradation when exposed to ambient environmental conditions. The degradation process is mainly initiated by oxygen molecules, which attacks the lone pair of phosphorus atoms. We show that in the case of phosphorene-based field-effect transistors (FETs), the channel degradation due to oxygen molecules is also influenced by the presence of channel inversion or excess (inversion) carriers. Our study reveals a unique reliability issue related to phosphorene FETs. Here, we investigate the role of channel excess holes (due to inversion) in the phosphorene degradation using the first-principles molecular dynamics computations and electrical and Raman characterization. The results show that phosphorene degrades faster under negative gate bias (excess hole) than pristine conditions (unbiased). The rapid degradation is mainly due to the enhanced chemical interaction of oxygen with the available hole in the channel. Using electrical and Raman characterization, the computational findings are experimentally verified over phosphorene FETs. The devices show a faster change in drain current and fast decay of Raman peaks in the ambient environment under negative gate bias compared to no gate bias condition. Therefore, phosphorene has an additional ambient reliability issue once exposed with negative biased during its FETs applications. [ABSTRACT FROM AUTHOR]

The operation of a capacitorless (1T) dynamic random access memory (DRAM) can be compromised if the storage region is located near metal–semiconductor junction in a reconfigurable field-effect transistor (RFET). Through subtle modifications, without affecting current drive, capacitance, and reconfigurable features, the present work showcases feasible 1T-DRAM operation in a RFET with an intentionally misaligned polarity gate. Analysis based on device physics and operation, highlights 1T-DRAM for standalone and embedded applications with impressive performance indicators: sense margin $\ge 6~\mu \text{A}/\mu \text{m}$ , retention time ≥16 ms (for embedded), and ≥64 ms (for standalone) at 85 °C, current ratio of ~104 along with a low write (~ 1 ns) and read (~ 2 ns) time. Guidelines in terms of scalability of total length and biases for implementing 1T-DRAM cell are presented. [ABSTRACT FROM AUTHOR]

The rise of graphene as an innovative electronic material promoted the study and development of new 2-D materials. Among them, reduced graphene oxide (rGO) appears like an easy and cost-effective solution for the fabrication of thin-film transistors (TFTs). To understand the limits and possible application fields of rGO-based TFTs, a proper estimation of the device parameters is of extreme importance. In this work, liquid-gated ambipolar rGO-TFTs are characterized and a description of their working principle is given. Particular attention is paid toward the importance of the transistors’ OFF-state conductivity that was modeled as a resistance connected in parallel with the TFT. Thanks to this model, the main transistor parameters were extrapolated from rGO-TFTs with different levels of electrochemical reduction. The extracted parameters allowed understanding that rGO-TFTs have similar holes and electrons mobilities, and the more pronounced p-type behavior of the devices is due to a positive shift in the p-type and n-type threshold voltages. [ABSTRACT FROM AUTHOR]

A partial silicon on insulator (PSOI) is a widely recognized technology suitable for high-voltage (HV) architectures for power integrated circuits (PICs). Despite the added process complexity compared with SOI reduced surface field (RESURF), this technology offers a wider range of voltage ratings due to the action of the depletion layer in the handle wafer (HW), reduced parasitic capacitances due to the extra volume of the depletion region in the HW, and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-D designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of HV integrated circuits (HVICs) where low ON-state resistance and reduced self-heating are essential requirements. This work presents a PSOI technology platform with the voltage ratings ranging from 45 to 400 V while providing low ON-state resistance, good hot carrier injection stability, as well as electrostatic discharge (ESD) capability of the HV devices. For example, for a 375-V rated laterally diffused MOSFET (LDMOSFET),this technology achieves an ON-state resistance of 1435 $\text{m}\Omega $ mm2, an over 50% improvement compared with the state-of-the-art SOI technologies while maintaining competitive reliability. [ABSTRACT FROM AUTHOR]

Hafnia-based ferroelectric field-effect transistors (FeFETs) with low power, scalability, and nonvolatile switching can overcome the performance limitations of conventional von Neumann computing technology. However, achieving a large memory window and excellent endurance in FeFET devices composed of two capacitors, such as ferroelectric and interfacial insulator capacitors, remains a challenge due to the strong electric field applied to the insulator, which accounts for the low permittivity (${k}$) of interfacial insulator. In addition, write disturb (WD) is considered to be a hurdle in the practical array operation of 1T-type FeFET devices. In this study, we propose a core process in which the dielectric constant and grain size of hafnia ferroelectric are adjusted by the ramping/cooling process, achieving high speed (20 ns), high reliability (1010), and negligible disturb (0 V in 1/ $3{V}_{dd}$ operation) FeFET. This results from effective voltage drop and switching across a relatively low- ${k}$ ferroelectric capacitor that is connected with an interfacial insulator. Intriguingly, using low- ${k}$ HfZrO as a gate, the proposed 3-D structure FeFET exhibits an improved memory window and robustness in WD in the array operation. These results suggest an informative way to design a high memory performance of FeFETs for future applications. [ABSTRACT FROM AUTHOR]

A 320 $\times $ 240 indirect time-of-flight (i-ToF) image sensor with a 5.6- $\mu \text{m}$ two-tap 1.5-V pump gate modulation pixel has been designed. Novel characteristics, such as the optimized pinned layer doping and potential buffer region (PBR) structure with pump gate modulator (PGM), are proposed to achieve a maximum lateral modulation electric field of 1500 V/cm under the front-side illumination (FSI) process. As a result, the proposed time-of-flight (ToF) sensor shows 200-mW power consumption and 54% demodulation contrast (DC) at 50-MHz modulation frequency, depth noise less than 1% with 940-nm illuminator from 0.3 to 3 m. [ABSTRACT FROM AUTHOR]

The external quantum efficiency (EQE) for InGaN/GaN micro-light-emitting diodes ($\mu $ LEDs) is strongly affected by surface recombination at mesa sidewall. In this work, we propose fabricating a Ta2O5 buried insulator in the periphery for the $\mu $ LED mesa to suppress the surface recombination. The Ta2O5 buried insulator with a large relative dielectric constant of 26 can significantly reduce the voltage drop in the insulator so that the lateral energy band below the p-type contact can be bent in the way of generating energy barriers for holes in the mesa edge. This further suppresses the current diffusion to the defected mesa edges for $\mu $ LEDs. Thus, when compared with the reference $\mu $ LED, the proposed $\mu $ LED with $40\times 40\,\,\mu \text{m}^{{2}}$ chip area increases the EQE by 34.6%, and the ON/ OFF current ratio is increased to $10^{{8}}$. A reduced ideality factor of 6.8 is also obtained when compared with other devices. [ABSTRACT FROM AUTHOR]

Planar microstrip line slow wave structures (PML-SWSs) have great prospects in the millimeter and terahertz wave fields. However, the development of the devices employing PML-SWSs is severely limited due to the focusing difficulties. Compared with the conventional sheet electron beam (SEB) SWS, the asymmetric boundary condition of PML-SWS and high local electric field further increase the instabilities of the SEB transport in PML-SWS. A new approach, named the uniform magnetic focusing system with the matching electric field (UMFS-MEF), is presented in this article, which can effectively solve these issues. The simulation results illustrate that the expansion rate of the SEB in UMFS-MEF is significantly lower than that in the conventional uniform magnetic focusing system (CUMFS) with the same magnetic field strength ${B}_{z}$. Moreover, the present calculation results show that the UMFS-MEF requires only 10.6% of the magnetic field strength of CUMFS for maintaining the same expansion rate. This means that the UMFS-MEF can effectively suppress the instabilities, and employ a very low magnetic field to maintain the stabilities of the SEB transport. Finally, we give several other schemes to realize the method. [ABSTRACT FROM AUTHOR]

This article studies a reliability mechanism for field-plate-assisted reduced surface field (RESURF) effect 225-V NDMOS devices based on anode hole oxide injection for carriers that are in thermal equilibrium with the surrounding lattice. The injection mechanism is facilitated by a unique combination of layout and application biases that result in electric field vectors pulling low-energy minority hole carriers into oxide traps that overlap the drain potential. The effect of this positive charge trapping along the field oxide is to inhibit the RESURF mechanism, while also weakening the gate oxide where it overlaps the drain that ultimately results in a rupture. To quantify the process, a new accelerated aging technique is described that uses the parasitic n-p-n bipolar parallel of the nMOS channel to significantly increase the number of holes while still maintaining the MOS application voltages needed to enable the mechanism. This provides a cost-effective way to accurately accelerate this reliability mechanism with significantly smaller lead times relative to using higher biases and temperatures. This technique is then used with technical computer-aided design (TCAD) analysis to determine the impact of different manufacturing variables, where process controls are introduced for targeted manufacturing limits that can eliminate this mechanism from occurring. [ABSTRACT FROM AUTHOR]

We propose a storage memory device that enables bit densities of >1 Tbit/mm2 based on the electro- deposition and electrodissolution of multilayered metal stacks in deep nanometer-sized wells. This device addresses the challenge of bit density scaling slowdown expected for 3-D NAND flash beyond 2030. We describe in detail the operating principles and discuss the response time, bandwidth, retention, and cycling endurance requirements for the device to be viable. As a proof-of-principle, we provide a first demonstration of the write/read (W/R) mechanism on millimeter- and micrometer-sized electrodes and show the device’s potential for reaching very high bit densities. To evaluate how the response time scales for the envisioned nanometer-sized electrodes, we derive simple analytical expressions based on finite element simulations that relate the well depth, radius, and electrolyte composition to the deposition/dissolution rate. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) super junction (SJ) JFETs fabricated by sidewall implantation with different mesa-widths (MWs) and termination designs are characterized in this article. The device with an MW of $1.8 \mu \text{m}$ and active area of 0.104 mm2 achieves a breakdown voltage of 1086 V and a specific ON-resistance of 0.98 $\text{m}\Omega \,\cdot $ cm2. The first-quadrant output and transfer characteristics are presented, from which the ON-resistance and pinch-off voltage are extracted and analyzed. The pinch-off voltage shows great stability against the variation of temperature. The forward blocking characteristics under different gate voltages and with different terminations are presented. The gate needs to be negatively biased below the hold-off voltage to prevent the premature breakdown caused by drain-induced barrier-lowering (DIBL) effect. The termination with narrow mesas in the ${x}$ -direction and trapezoidal mesas in the ${y}$ -direction is found to have the highest breakdown voltage, due to its optimized net charge distribution. The third-quadrant output characteristics are presented. Under forward-off gate voltage, the third-quadrant turn-on voltage is found to be determined by the difference of hold-off and pinch-off voltages, and there is a tradeoff between the absolute third-quadrant voltage drop ($\vert {V}_{\text{on}}\vert $) and the maximum current before gate junction turn-on (${J}_{\text{umax}}$). The third-quadrant performance can be improved by using forward-on gate voltage, a $\vert {V}_{\text{on}}\vert $ lower than 0.2 V (at 100 A/cm2) and a ${J}_{\text{umax}}$ larger than 500 A/cm2 are achieved. Finally, the whole output characteristics are modeled to facilitate the device design in different applications. [ABSTRACT FROM AUTHOR]

We have developed models for three different short-channel effects [subthreshold-swing degradation, threshold-voltage roll-off, and drain-induced barrier lowering (DIBL)] in coplanar organic thin-film transistors (TFTs) and verified them against the measured current–voltage characteristics of TFTs having channel lengths as small as $0.5 \mu \text{m}$. To derive the models, the Schwarz–Christoffel transformation was applied to obtain a complex mapping function that links the coplanar device geometry to an equivalent geometry in a different coordinate system in order to solve Laplace’s equation of the 2-D potential problem. The solution to this potential problem serves as the basis for the definition of the short-channel models, which can be incorporated into any compact dc models for coplanar TFTs that use the TFTs’ threshold voltage and subthreshold swing as input parameters. To verify the model, the channel-length-dependent effects were extracted from technology computer-aided design (TCAD) simulations (transfer characteristics and surface-potential profile) and from measurements performed on organic p-channel TFTs fabricated using high-resolution stencil lithography. [ABSTRACT FROM AUTHOR]

DC performances of a depletion-mode 100-nm In0.53Ga0.47As/InP composite channel InP-based high-electron-mobility transistor (HEMT) is investigated by using numerical simulation. The transfer, output, and breakdown characteristics of different doped InP subchannel thickness In0.53Ga0.47As/InP composite channel HEMT are compared. Decreasing the thickness of the doped InP subchannel from 10 to 5 nm results in a decline of the output current. However, the threshold voltage is increased from −0.77 to −0.6 V and the breakdown voltage is improved from 1.99 to 5.69 V at bias of ${V}_{{\mathrm {gs}}}-{V}_{{\mathrm {t}}} = -0.5$ V. To enhance the breakdown characteristic of In0.53Ga0.47As/InP composite channel HEMT, we minimize the thickness of the doped InP layer and replace the doped InP layer with the delta-doped layer. The structure is compared with the conventional double delta-doped structure in the performance of transfer, output, and breakdown characteristics. At ON-state, the electrons of two kinds of structure concentrate in the InGaAs channel. The output current and the threshold voltage of the composite channel structure are at the same level compared with the conventional double delta-doped structure. However, at OFF-state, because of the transfer of electrons into the InP subchannel, part of electric potential will not be concentrated at the drain side of the gate region but distributed in other area of the channel. A higher drain voltage is required to achieve electric field strength enough to breakdown and the breakdown voltage is improved obviously. [ABSTRACT FROM AUTHOR]

The traveling wave tube (TWT) has been a reliable conventional vacuum electron device (CVED) since the 1940s. Researchers, beginning in the late 1980s, extended the TWT to the relativistic electron beam regime to generate 100- $\text{s}\cdot $ MW power in the ${X}$ -band. Since the mid-1990s, there has been little advancement in the field. Recently, the linear theory of a multistream TWT was published, which showed superexponential amplification properties. This article describes a novel technique for producing multiple electron beams with an energy difference of about 6%–27% with comparable currents from a single cathode at a single potential for a multistream TWT. We present a new model of two nested cathodes where two annular electron beams are generated and propagated in a smooth cylindrical pipe that emerged into a strong magnetic field. The two nested cathodes are magnetically insulated coaxial diodes (MICDs). The simulation results are obtained using the MAGIC particle-in-cell (PIC) code for the experimental vacuum diode geometry of the SINUS-6 high-current electron beam accelerator at The University of New Mexico. Results are obtained, which are then: 1) compared with earlier experimental results for a single beam; 2) study the current–voltage (${I}$ – ${V}$) characteristics of two electron beams powered by a single cathode at a single potential immersed in a strong magnetic field; and 3) show 6%–27% energy differences with comparable currents between two beams. This technique is viable for pulsed power-driven, relativistic electron beams for a relativistic multistream TWT. [ABSTRACT FROM AUTHOR]

In this article, we present an analytical model for the surface potential ($\psi _{s}$) for metal–ferroelectric–insulator–semiconductor (MFIS) negative capacitance field-effect transistors (NCFETs) as a function of the gate voltage, by first developing the models regionwise (weak and strong inversion) and then merging them together in the moderate-inversion region by using a smoothing function. This model for $\psi _{s}$ is used subsequently to obtain the charge and capacitance behavior and eventually to the development of the current–voltage model. It considers various important technology parameters, i.e., substrate doping, ferroelectric (FE) and oxide thicknesses, remnant polarization, and coercive field. All the model results showed an excellent match with those obtained from TCAD simulations. It has also been observed that capacitance matching, and thus, gate control, improves with an increase in the FE thickness and the ratio of the coercive field to remnant polarization, which can be utilized effectively in device and circuit designs for low-power applications. The small-signal parameters, extracted from the current–voltage characteristics, show the first-order continuity, thus making the model suitable for circuit simulation. [ABSTRACT FROM AUTHOR]

An analytical drain current model is developed for a short-channel, dual-gate, monolayer 2-D transition metal dichalcogenide (TMD), lateral tunnel field-effect transistor (TFET) by considering 2-D ${p}^{+}-{n}$ and ${n}-{n}^{+}$ junction at source–channel and channel–drain junction, respectively. This work includes the effect of both front- and back-gate dielectric fringing field effects and 2-D source and drain depletion charges. A unified piecewise surface potential model is developed by capturing the fringing field effects in the channel and 2-D junction behavior at the source–channel and channel–drain junction by ensuring continuity of electric field at the junction regions. A tangent-line approximation method is employed for accurate numerical evaluation of the tunneling current. The proposed model is validated with simulation results obtained using nonequilibrium Green’s function (NEGF)-based simulator for different 2-D layered materials and a close agreement is observed. The veracity of the proposed model is tested with data in reported studies for different bias conditions and excellent matching is observed. The applicability of the model is demonstrated for any 2-D layered material-based TFET from ultrashort channel to a channel length of 50 nm. The proposed model will be extremely useful for further exploration of 2-D TMD material TFET-based very large-scale integration (VLSI) circuits. [ABSTRACT FROM AUTHOR]

2-D Janus materials are easy to produce strong piezoelectric properties due to the lack of mirror symmetry. In this article, we have performed the first-principles study on the piezoelectric properties of Janus BiTe ${X}$ (${X} =$ Cl, Br, I) monolayers. The electronic properties are calculated to analyze the causes of piezoelectric properties. Based on the density functional perturbation theory (DFPT), the piezoelectric tensor of Janus BiTe ${X}$ monolayer is calculated, and the piezoelectric coefficient is further calculated. The in-plane piezoelectric coefficient ${d}_{{11}}$ of BiTeI monolayer reaches 7.79 pm/V and the out-of-plane piezoelectric coefficient ${d}_{{31}}$ reaches 0.62 pm/V. Based on nonequilibrium Green’s function, the ${I}$ – ${V}$ response is calculated to analyze the piezoelectric response of the material in the device. In addition, these materials have suitable carrier mobility. Our research work shows that Janus BiTeI monolayer has potential applications in piezoelectric electronic devices, which provides a theoretical basis for further exploration of more 2-D Janus piezoelectric materials. [ABSTRACT FROM AUTHOR]

A novel complete accumulation lateral double-diffused MOSFET with floating buried layers (CA-FBL LDMOS) is proposed to reduce the ${R}_{ \mathrm{\scriptscriptstyle ON}, \text {SP}}$ and improve the breakdown voltage (BV) synchronously. The CA-FBL LDMOS is characterized by n-type floating buried layers (FBLs) and a gate semiconductor layer consisting of two p-n junctions. For CA-FBL LDMOS, the conduction of current completely relies on the accumulated electrons, instead of the doping concentration of the drift region. The conduction mechanism of CA-FBL LDMOS is to change the potential distribution of the gate semiconductor layer and then form an electron channel under the oxide layer. Not only does the density of electrons in the channel increase greatly, but also the channel extends from the source to drain electrodes, and the effective gate length increases. Therefore, the ${R}_{ \mathrm{\scriptscriptstyle ON}, \text {SP}}$ decreases sharply. Thanks to the n-type floating layers, the bulk electric field distribution of the device is also optimized. The electric field crowing at the edge of the drain diffusion region is relieved. The speed that the BV runs to saturation slows down. Moreover, the BV can be further improved by increasing the number of n-type FBLs. The simulation results indicate that the BV of CA-FBL LDMOS is 898 V with the drift region length of 50 $\mu \text{m}$ and the ${R}_{ \mathrm{\scriptscriptstyle ON}, \text {SP}}$ is only 33.8 $\text{m}\Omega \cdot $ cm2, which is reduced by 73% compared with FBL lateral double-diffused MOSFET (LDMOS) without accumulation effect. However, affected by the built-in potential of p-n junction in the gate semiconductor layer, the threshold voltage of CA-FBL LDMOS (3 V) is slightly higher than that of FBL LDMOS (1.5 V). At the same time, due to the higher dielectric coefficient of the gate semiconductor layer and the increase of effective gate length, the turn-off time of CA-FBL LDMOS also increases slightly. But compared with the rapidly decreased conduction loss, the switching loss is acceptable. [ABSTRACT FROM AUTHOR]

In this article, we demonstrate the impact of nanowire geometry of GaAs1–xSbx transistor. Circular, square, and triangular gate-all-around (GAA) geometries are taken to investigate the characteristics of the GaAs1–xSbx nanowire using a well-calibrated TCAD setup. This work analyzes: 1) the potential and field profiles; 2) the effect of channel mobility on the transfer characteristics (${I} _{D}$ – ${V} _{G}$) of all three geometries; 3) trend of the total gate capacitance (C–V); 4) impact of interface trap charges; 5) analysis of noise spectral density for each geometrical nanowire; and 6) impact of temperature (down to cryogenic range) on the performance metrics. We found that the equivalent distance from the center-to-surface of the nanowire is relatively small in triangular nanowire (TNW), resulting in a superior subthreshold slope (SS), DIBL, and OFF current. TNW shows ~8.9% (8.7%) and ~76.4% (75%) reduction in SS and DIBL with ~ $61.67\times $ ($20.1\times $) improvement in ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ ratio as compared to circular (rectangular) nanowires. We have also analyzed the PSD of 1/f noise and noise figure (NF) of each geometrical nanowire and found that TNW has ~5.97% (~10.1%) higher NF than CNW (RNW). Furthermore, we investigated the impact of temperature down to the cryogenic range over the device metrics such as threshold voltage (${V} _{th}$), ${I} _{on}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ , transconductance ($\text{g}_{m}$), and so on. Hence, a nanowire geometry can be optimized through the obtained design explorations and could be used for high-performance applications. [ABSTRACT FROM AUTHOR]

The tradeoff between breakdown voltage (BV) and specific ON-resistance (${R}_{{\mathrm{\scriptscriptstyle ON},\text {sp}}}$) has always been the most crucial designing indicator to power devices. In this article, based on the effective concentration profile (ECP) concept, a novel field plate-adaptive doping (FAD) technique is proposed. Therefore, the benefits of the field plate (FP) structure and variation in lateral doping (VLD) technique are obtained simultaneously, while avoiding the inherent disadvantages of VLD and FP techniques. The new devices feature the gate FPs covering the part drift region with the FAD doping profile. The analytical model is therefore proposed to theoretically explore the breakdown mechanism. The good agreement between modeled and simulated results verifies the effectiveness of the FAD technique. The FAD achieves the advantages of low on-resistance and high BV by allowing a higher drift region doping concentration and suppressing the peak field at the FP side. Thus, compared with the FP and VLD, a better tradeoff between BV and ${R}_{{\mathrm{\scriptscriptstyle ON},\text {sp}}}$ can be obtained in the FAD lateral double-diffused metal–oxide–semiconductor (LDMOS). [ABSTRACT FROM AUTHOR]

In this work, a physics-based compact model for channel charges and drain current in nanosheet FETs is presented. The model follows the bottom-up approach. The channel charges are calculated using the 1-D density of states (DOS), which seamlessly scales up for devices with 2-D or 3-D DOS as the confinement reduces in a particular direction. The model uses full Fermi–Dirac (FD) statistics and requires only two additional fitting parameters. The accuracy of the model is confirmed by comparing it with data from in-house 2-D coupled Poisson–Schrödinger (PS) solver and Technology Computer Aided Tool (TCAD) simulations. The proposed model accurately predicts the subband energies, inversion charges, channel potential, and drain current for nanosheet FETs (NsFETs) with different dimensions and applied biases. [ABSTRACT FROM AUTHOR]

We present an analytical approach for the calculation of direct source-to-drain tunneling (DSDT) probability of electrons in gate-all-around (GAA) silicon nanosheet (SiNS) MOSFETs. The used method is based on the wavelet transform and leads to a quasi-compact model (QCM) for the DSDT current of ultrashort-channel devices. Among them, we introduce a four-piece parabolic approximation method for the conduction band edge and present analytical expressions for the tunneling distances of electrons with different energy levels. The development of a QCM is achieved by limiting the number of interpolation points for the tunneling current density to seven specific electron energies, distributed around the energy level that makes the largest contribution to the tunneling current. A further simplification is achieved by the Gaussian approximation of the tunneling current density in transverse direction so that only the center and surface potentials ($\Phi _ {\text {C}}$ and $\Phi _ {\text {S}}$) at the barrier are of interest for the modeling. For comparison, all those approximations are also implemented in the Wentzel–Kramer–Brillouin (WKB) approximation. Furthermore, the approach is verified by nonequilibrium Green’s function (NEGF) simulation. [ABSTRACT FROM AUTHOR]

Designers of integrated circuits aim to reduce the bias supply voltage (${V}_{\text {DD}}$) of devices to make them suitable for low-power applications. Nanoscale field-effect diodes (FEDs) that have been presented so far have some advantages, such as a larger ON/OFF current (${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$) ratio and smaller energy-delay product (EDP) compared to silicon-on-insulator (SoI)-MOSFETs with the same dimensions. However, nanoscale FEDs have ${V}_{\text {DD}}$ values greater than 1 V, which have to be reduced to make them appropriate for low-power applications. This study proposes a junctionless carbon nanotube FED (JL-CNT-FED) structure in which CNT is used as the source–channel–drain material. To turn on the proposed JL-CNT-FED, drain contact has to be extended over the oxide by 10 nm. Additionally, suitable work functions for the auxiliary and control gates significantly reduce ${V}_{\text {DD}}$ in the proposed JL-CNT-FED. The digital performance in terms of ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio, intrinsic gate delay ($\tau $), and EDP of the proposed device are investigated through simulation. The design of JL-CNT-FED with ${V}_{\text {DD}} = {0.5}$ V achieves an excellent ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio compared to FEDs that have been introduced so far. Simulation results show that the values of ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio and subthreshold power dissipation (SPD) of the proposed JL-CNT-FED with a channel length of 42 nm are, respectively, 1E3 times larger and 196E3 times smaller than those of a regular JL-FED with the same dimensions. The proposed JL-CNT-FED with $V_{\text {DD}} = {0.5}$ V can undergo channel length scaling down to 10 nm, so this device can be reasonable for low-power digital applications. [ABSTRACT FROM AUTHOR]

The article reports a comprehensive study optimizing the OFF- and ON-state characteristics of 3.3 kV junction barrier Schottky (JBS) diodes made using nickel, titanium, and molybdenum contact metals. In this design, the same implants used in the optimized termination region are used to form the P-regions in the JBS active area. The width and spacing of the P-regions are varied to optimize both the ON- and OFF-state of the device. All the diodes tested displayed high blocking voltages and ideal turn-on characteristics up to the rated current of 2 A. However, the leakage current and the Schottky barrier height (SBH) were found to scale with the ratio of Schottky to p+regions. Full Schottkys, without p+regions, and those with very wide Schottky regions had the lowest SBH (1.61 eV for Ni, 1.11 eV for Mo, and 0.87 eV for Ti) and the highest leakage. Those diodes with the lowest Schottky openings of $2 ~\mu \text{m}$ had the lowest OFF-state leakage, but they suffered severe pinching from the surrounding p+regions, increasing their SBH. The best performing JBS diodes were Ni and Mo devices with the narrowest pitch, with the p+implants/Schottky regions both $2 ~\mu \text{m}$ wide. These offered the best balanced device design, with excellent OFF-state performance, while the Schottky ratio guaranteed a relatively low forward voltage drop. [ABSTRACT FROM AUTHOR]

This work highlights the work-function-fluctuation (WKF) of the strained Si0.6Ge0.4p-n-p-n tunneling field-effect transistor (TFET) using nanosheet geometry at sub-3 nm technology nodes. The reported work exploits 3000 samples to signify the key results of several dc factors such as ON- and OFF-state currents (${I}_{ \mathrm{\scriptscriptstyle ON}}$ and ${I}_{ \mathrm{\scriptscriptstyle OFF}}$), threshold voltage (${V}_{\text {th}}$), and the subthreshold swing (SS). Fewer WKFs are identified for higher metal grain number (MGN) due to the shaped low grain size. Collective average energy reduction of 10–15 meV as low with high MGN and 40–60 meV as high with low MGN for a group of metal-grains closer to the tunneling junction is observed. This huge impact of energy reduction proportionally affects electron transport due to reduction in tunneling length. High variability in ${V}_{\text {th}}$ ($\geq {15}$ %) is identified at progressively diminished MGN due to parabolic behavior of variation. Furthermore, marginal variation in SS, ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , and ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ are observed because of the WKF dependability over the subthreshold region of operation. [ABSTRACT FROM AUTHOR]

In this study, we present programming speed enhancement in amorphous oxide semiconductor memory thin-film transistor (TFT). We developed a nonvolatile memory transistor based on InZnSnO back-channel-etch TFT with InGaZnO charge storage layer inserted between gate insulators. We proposed double-gate (DG) and body-contacted (BC) memory structure to improve memory erase speed, which is the most important issue in oxide memory TFTs. DG memory did not show sufficient improvement due to large voltage drop in second gate insulator. BC memory, which can control back-channel potential directly, showed significant improvement on memory program/erase speed. [ABSTRACT FROM AUTHOR]

Vertical field effect transistors (VFETs) based on conductive network electrodes feature high current density and compatibility in printing processes. Here, the device structures of VFETs are designed and optimized toward good current saturation and a better ON–OFF ratio. Among the three different structures, a simple structure stands out as the best: a semiconducting layer is inserted below the source electrode to increase the injected area of carriers and to enhance L-type channels (the channels along the semiconductor–dielectric interface and then to the drain), whereas an insulating layer is added on the top and two sides of the source electrode to generate a depletion region and to suppress I-type channels (the channels from the top of the source to the drain). The introduction of moderate Schottky barriers to the source electrodes further benefits the current saturation and gate tuning. The 2D-technology computer-aided design (TCAD) simulations are performed to analyze the physical mechanisms by quantifying the distribution of potentials, carrier concentrations, and current densities. The simulated current–voltage relations show a differential output resistance over 105 $\Omega \cdot $ cm and an ON–OFF ratio over 105, indicating that the problems of current saturation and the ON–OFF ratio in short-channel VFETs have been theoretically solved to some extent. [ABSTRACT FROM AUTHOR]

The nanowire gate-all-around structure with the ultimate channel electrostatic integrity exhibits the best immunity to short channel effects and improved scaling capability compared with other multigate structures. In this article, both the tunneling current and capacitance models are developed simultaneously for nanowire tunneling field-effect transistors (FETs). Based on the same surface potential model, the developed current model and capacitance model share the common parameters and therefore can be easily integrated as a complete model for circuit-level simulations. Moreover, there is no iterative process involved during the model derivation indicating the models would be efficient for circuit simulations. The proposed models are also implemented into a circuit simulator with SPICE net-list to simulate the inverter, NAND, and NOR gates. Correct circuit behaviors obtained validate the model compatibility with the SPICE platform and usefulness for the further investigation of nanowire-based tunnel FET (TFET) circuits. [ABSTRACT FROM AUTHOR]

This article presents a self-consistent model to study the space charge limited (SCL) bipolar flow for the 2-D nonuniform and uniform currents injection. This model can simultaneously determine the unknown current densities and the potential distribution. By considering a planar diode with a gap spacing ${D}$ and a finite-width beam ${W}$ , the enhancement over the 2-D unipolar flow model is investigated as a function of ${W}/{D}$. Due to the edge effect, the nonuniform current density profiles for both the electron and ion are observed. We also found that the 2-D total SCL electron current is universally given by ${F} \times {I}_{\mathrm {2D\_{}unipolar}}$ , where ${F}$ and ${I}_{\mathrm {2D\_{}unipolar}} $ , respectively, denote the 2-D enhancement factor due to the influence of the geometry and ions, and 2-D total SCL electron current in the absence of ions. The enhancement factor ${F}$ follows a ${W}/{D}$ scaling and gradually converges to the 1-D enhancement factor ${\Gamma }$ with the increasing of the ratio ${W}/{D}$. [ABSTRACT FROM AUTHOR]

In this article, we proposed a new program operation scheme to overcome the degradation of program window in scaling down of 3-D NAND flash memory. First, we investigated natural ${V}_{\text {th}}$ shift (NVS) effect in scaled-down structure and confirmed that this effect occurs due to an increase in fringe field by adjacent read voltage. Second, we investigated programmed and erased ${V}_{\text {th}}$ window with scaling down and confirmed that programmed and erased ${V}_{\text {th}}$ is decreased significantly due to the NVS effect. To overcome this scaling effect, we proposed a new program operation scheme using negative bias. The proposed scheme not only improves the program window margin but also achieves voltage scaling. In addition, the proposed scheme enables multistring operation through improved self-boosting, which is a compatible scheme in full array level. [ABSTRACT FROM AUTHOR]

While analytic equations for space-charge limited current density (SCLCD) have been derived for planar and nonplanar geometries, the SCLCD for emission from a sharp tip has not been derived. In this article, we use variational calculus (VC) to derive an exact analytic equation for SCLCD for a 1-D tip-to-tip geometry, represented by hyperboloids in the prolate spheroidal coordinates, and recover the SCLCD for a tip-to-plate geometry as a special case. We then consider circles in the extended Poincaré disk, which is the stereographic projection of hyperboloids onto a plane, as conformal transformations to derive the SCLCD for a misaligned tip-to-tip geometry, where the axes of rotation of the hyperboloids are displaced by a small distance. This mapping technique is also applied to study the effect of a small angle tilt in a tilted tip-to-tip geometry, where the axes of rotation of the hyperboloids meet at an angle. [ABSTRACT FROM AUTHOR]

We propose device and circuit assist techniques to lower the ferroelectric–metal field-effect transistor (FeMFET) write voltage while lowering the effect of depolarizing field. A bipolar threshold selector (TS) is connected between the intermediate node of a FeMFET and ${V}_{\text {SS}}$ , which provides a low-impedance bypass path by triggering an insulator to metallic transition during a write operation. This lowers the voltage drop across MOSFET and reduces the write voltage to ~1.7 V. For further reduction in write voltage, the MOSFET in the FeMFET is utilized as a circuit assist by repurposing it as a capacitive coupling device. It reduces the write voltage to ~1.4 V. During the read mode, TS is in insulating state and does not alter the capacitive voltage divider action. Read is followed by a data-dependent write-back stage to bring the polarization close to retention polarization. During the retention mode, TS acts as a weak bleeder resistor, reducing noise coupling and depolarizing field. TS parameter sensitivity for write voltage reduction along with row hammer effect of the proposed read- and write-back operation is also presented. [ABSTRACT FROM AUTHOR]

Gap-type amorphous silicon (a-Si) thin-film transistor (TFT) can provide high photo current in simple device structure, which makes it suitable for large-area-sensing applications. The reason why the photo current is much higher when the device is operated in the on-region than that in the off-region is not well studied. In this article, we propose the mechanism to explain this special phenomenon for the gap-type a-Si TFT. The feature of potential well is supported by TCAD simulation. The mechanism is further verified from the perspective of temperature effect and time response. [ABSTRACT FROM AUTHOR]

The popular Tung model for Schottky barrier inhomogeneity considers how low-barrier patches (embedded in a high barrier background) impact the diode current. However, Tung’s model fails to account for the image-force effect. We analyze how the image force alters the current through an inhomogeneous barrier and find that, in some circumstances, it will smooth the barrier, such that the current will effectively be that of a homogeneous diode. We also show that for a distribution of defect barriers and/or sizes, the diode current can be intermediate between that of a homogeneous diode and a diode dominated by the low-barrier patches. We calculate the parameter values associated with this transitional region. A survey of existing literature applications of Tung’s model shows that many diodes are actually operating in this transition region, where Tung’s equations are in error. We provide the corrected equations for this case and demonstrate their ability to model practical diode characteristics. [ABSTRACT FROM AUTHOR]

A novel LDMOS featuring bulk full gate (BFG) with bulk channel and electron accumulation effect, named BFG-LDMOS, is proposed and investigated. The BFG includes bulk gate oxide (BGO) that is inserted in the ${N}$ -drift and the full gate (FG) that is formed by the wide open base transistor (P-body/ ${N}$ -drift/P+). The gate potential is extended in the gate- ${N}$ -drift-drain (GND) region, and thus, the bulk channel of the P-body and electron accumulation effect of the ${N}$ -drift in the source- ${N}$ -drift-drain (SND) region is achieved, which significantly reduces the specific ON-resistance (${R}_{\text {ON,sp}}$). In addition, the P-body, ${N}$ -drift, and N+ drain are divided by the BGO, and the P-body/ ${N}$ -drift junction (PN1) sustains the breakdown electric field for both sides, which guarantees the breakdown voltage (BV) like conventional LDMOS. The 3-D simulation results indicate that the BV and ${R}_{\text {ON,sp}}$ are 249 V and 2.93 $\text{m}\Omega \cdot $ cm2 for the proposed BFG-LDMOS, respectively, and the Baliga’s figure of merit (FoM) is high up to 21 MW/cm2, which breaks through the silicon limit of the reduced surface field (RESURF). [ABSTRACT FROM AUTHOR]

In this article, the single-event-transient (SET) in reconfigurable field-effect transistor (RFET) is evaluated by 3-D technology computer-aided design (TCAD) simulation for the first time. The effects of linear energy transfer (LET) values, electrical bias, strike location, and angle are investigated in detail. For heavy ion with LET of 10 MeV $\cdot $ cm2/mg and characteristic radius of 1 nm, the peak value of drain SET current is up to 0.237 mA for n-type program, which is much higher than the saturated conduction current of $2.22~\mu \text{A}/\mu \text{m}$. The peak SET current increases from 0.18 to 0.36 mA as ${V}_{\text {DS}}$ ranges from 0.8 to 1.4 V. The drain voltage (${V}_{\text {DS}}$) has a great impact on SET response and a higher lateral electric field will worsen the SET effects. The most sensitive position is confirmed to be not only related to the electric field distribution, but also the distance away from drain terminal. A serious SET effect is observed with a smaller angle. Furthermore, the impact of SET effect on NAND2/NOR2 multifunctional logic gates circuit based on RFETs is also evaluated. When striking the end of the changing edge of the input signal, the rise and fall relative propagation delays of NAND2 logic gates circuit are up to 34.49% and 35.04% respectively, with LET of 6 MeV $\cdot $ cm2/mg. This work provides guidelines for RFET radiation-hardened technology in future extreme environment electronics applications. [ABSTRACT FROM AUTHOR]