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Greater than 190 °C continuous wave (CW) lasing is achieved from 905 nm high-efficiency vertical cavity surface-emitting lasers (VCSELs). The maximum power conversion efficiency (PCE) of 46.3% for ${4}~\mu \text{m}$ VCSELs was demonstrated under the ambient temperature of 30 °C. The maximum PCE decreases only 10% of its value from 30 °C to 90 °C, showing stable high-temperature characteristics. The thermal resistances and active region temperatures of the device versus ambient temperature are determined experimentally. Besides, size-dependent thermal characteristics are also analyzed by characterizing the spectral and spatial properties of devices with various apertures. It is found that the higher the ambient temperature is, the less the number of high-order modes is, and single fundamental mode operation can be realized in ${4}~\mu \text{m}$ VCSELs even at a relatively high temperature of 190 °C. The design and characterization of these high-temperature VCSEL devices might present the basis for future laser radar application.

The output characteristics of vertical cavity surface emitting lasers (VCSELs) arrays are largely influenced by temperature. We systematically studied thermal properties in 20-element oxide-confined VCSEL arrays via both theory and experiment. The output power, conversion efficiency, and threshold current dependent on ambient temperatures were measured. According to the relationship of wavelength shift and dissipated power, the device thermal resistance dependent on ambient temperature was obtained. The actual temperature in active region was successfully extracted. A 3-D heat diffusion model was established to simulate temperature distribution accurately.

The fabrication of sub-0.1-/spl mu/m CMOS devices and ring oscillator circuits has been successfully explored. The key technologies include: lateral local super-steep-retrograde (SSR) channel doping with heavy ion implantation, 40-nm ultrashallow source/drain (S/D) extension, 3-nm nitrided gate oxide, dual p/sup +//n/sup +/ poly-Si gate electrode, double sidewall scheme, e-beam lithography and RIE etching for sub-0.1-/spl mu/m poly-Si gate pattern, thin and low sheet resistance SALICIDE process, etc. By these innovations in the technologies, high-performance sub-0.1-/spl mu/m CMOS devices with excellent short-channel effects (SCEs) and good driving ability have been fabricated successfully; the shortest channel length is 70 nm. 57 stage unloaded 0.1-/spl mu/m CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V, respectively, are achieved.