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The characteristics of a two-bit-per-cell charge-trapping nonvolatile memory (NVM) device are presented using gate-to-drain nonoverlapped implanted (NOI) n-MOSFETs. The stability and reliability characteristics such as retention, disturbance and cycling are also evaluated.

An analysis of the temporal read noise on the signal path of a complementary metal-oxide semiconductor image sensor was conducted in order to investigate the effectiveness of high-gain column amplifiers in enhancing sensor sensitivity. The analysis showed that by increasing the column amplifier gain the direct noise components can be greatly reduced which indicates that an extremely low-noise readout circuit could be achieved through the development of a double-stage noise-canceling architecture.

It is demonstrated that carrier activation in polysilicon shifts the flatband voltage as does boron penetration. The formation of polysilicon with small grains will become a key technology for fabricating high-performance CMOSFETs.

The design of a loadless CMOS four-transistor (4T) cell for high density embedded SRAM applications is presented. The results of static-noise-margin (SNM) in the CMOS transistor cell are discussed.