Search

A study was conducted to examine the program and retention transients of silicon nitride-based (SONOS/TANOS) nonvolatile memories using a new characterization technique and an improved model for charge injection and transport through ONO gate stacks. Results reveal that the carrier transport in the SiN layer affects the spatial distribution of the trapped charge and various aspects of program and retention transients.

An analytical model is used for organic thin-film transistors that has accounted for the affect of trap states on the current voltage characteristics. The subthreshold regime has reacted to the presence of traps and hence it is used for extracting approximate trap parameters from experimental transistor data.

A modeling technique that uses charge transport equations to calculate channel current in organic field effect transistors (OFETs) by numerical solution in the SPICE simulation program is reported. The modeling technique is a bridge between physical models of charge transport and a SPICE model useful in circuit simulation without requiring a closed-form drain-current equation.

The electrical performance and programming/erasing (P/E) mechanism of dual charge storage layer (DCSL) and Flash memories using a [Si.sub.3][N.sub.4] (NROM)-type multilevel-cells (MLCs) are examined. DCSL MLCs have shown negligible threshold-voltage ([V.sub.th])-level offsets that are maintained throughout the [10.sup.5] P/E cycles, which has shown improved endurance reliability compared to NROM-type MLCs.

A junction termination extension avalanche photodiode (APD) is evaluated for x-ray detection. Findings reveal that the structure posses the potential to make very low-noise detectors with high reliability after optimization of the implanted charge.

The development, operation, and characterization of charge-coupled devices (CCDs) that feature an electrode structure that allows the transfer of charge both horizontally and vertically through the image area is described. The ability of both two dimensional transfer CCDs (2DT CCD) transfer electrode schemes to successfully transfer charge in both horizontal and vertical directions in the image section of the devices is proven, opening up potential new applications for 2DT CCD use.

A modified charge control approach accurately simulates the excess phase shift in the AC common-emitter current gain of bipolar transistors. Generalized expressions for arbitrary base impurity profiles and transport parameters provide estimates of the excess phase shift using transistor structure and process data. The method accounts for the high-frequency phase response.

The charge-injection into the opposite gate takes place by operating one channel of a silicon on isolator metal oxide semiconductor field effect transistor in avalanche while maintaining its opposite in accumulated. Three experiments which display opposite-channel-based charge injection are described. The PISCES simulations support the experimental results.

A circuit model used for alternating current thin film electroluminescent devices of different sulfide and fluoride phosphor and multilayer materials synthesized with Atomic Layer Deposition, depicts that the symmetric fluorides have inferior breakdown properties compared to sulfides. The transferred charge, device current and internal voltage across the phosphor layer are calculated using the sinusoidal excitation voltage. Strontium sulfide is highly asymmetric because of its nonuniform defect distribution.

Two-dimensional numerical simulations of the gate lag effect in GaAs MESFETs revealed that slow transient charge transfers of surface states present in the ungated FET access area cause the gate lag effect in the MESFETs. The 'hole-trap-like' DLTS signals correspond to regeneration of trapped holes during the positive filling pulse. Lag time and percentage vary directly with total surface state density, indicating that MESFETs with minimum state density and narrow N(+)-gate spacing have reduced gate lag effect.

A new two-dimensional orthogonal-transfer CCD (OTCCD) structure, implemented as a four-phase device, transfers charge packets in all four directions. The OTCCD structure is resistant to intralevel shorts and is applicable to large-area devices. Application of the OTCCD structure to a 64 by 64-pixel prototype device helps demonstrate its validity for high level outputs.