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In this article, we report the first experimental results of a novel 4H-silicon carbide (SiC) p-i-n photodetector based on a vertical nanocone array (NCA). It is fabricated by electron beam lithography and inductively coupled plasma (ICP) etching technology. The performance of static and dynamic behavior was studied systematically. It shows the responsivity of ~41.9 mA/W under 360 nm at a bias voltage of -0.5 V and has a linear response to the ultraviolet (UV) light in a wide light intensity range of 0.1-10⁴ mW/cm². The response time decreased as the light intensity rose from 3 mW/cm² to 5 W/cm² and then leveled off at higher light intensity (>100 mW/cm²), which is about 0.25 ms. The photodetector -3-dB cutoff is ~3400 Hz at λ = 360 nm and light intensity = 100 mW/cm². Besides, the detector can respond to the UV light from 260 to 360 nm and the peak responsivity is ~78 mA/W at 320 nm. The analysis results have reference values for the development of an innovative 4H-SiC UV photodetector to some extent.

In this article, the single-event-transient (SET) in reconfigurable field-effect transistor (RFET) is evaluated by 3-D technology computer-aided design (TCAD) simulation for the first time. The effects of linear energy transfer (LET) values, electrical bias, strike location, and angle are investigated in detail. For heavy ion with LET of 10 MeV·cm²/mg and characteristic radius of 1 nm, the peak value of drain SET current is up to 0.237 mA for n-type program, which is much higher than the saturated conduction current of 2.22 μA/μm. The peak SET current increases from 0.18 to 0.36 mA as $V_{DS}$ ranges from 0.8 to 1.4 V. The drain voltage ( $V_{DS}$ ) has a great impact on SET response and a higher lateral electric field will worsen the SET effects. The most sensitive position is confirmed to be not only related to the electric field distribution, but also the distance away from drain terminal. A serious SET effect is observed with a smaller angle. Furthermore, the impact of SET effect on NAND2/NOR2 multifunctional logic gates circuit based on RFETs is also evaluated. When striking the end of the changing edge of the input signal, the rise and fall relative propagation delays of NAND2 logic gates circuit are up to 34.49% and 35.04% respectively, with LET of 6 MeV·cm²/mg. This work provides guidelines for RFET radiation-hardened technology in future extreme environment electronics applications.

In this work, a novel n-In x Ga1- x N/N-gallium nitride (GaN) homotype heterostructure is proposed instead of P-GaN/N-GaN homostructure to produce impact-ionization-avalanche-transit-time (IMPATT) diode. Conventional GaN IMPATT device will lose its working ability due to the immature p-type GaN, so this work predicts that the n-In x Ga1- x N/N-GaN IMPATT diode can be an alternative to the GaN p-n IMPATT diode; thus, the difficulty of the p-type doping process is avoided. The dc and RF large-signal output characteristics with different compositions are investigated in detail. The simulation results show that the power and efficiency of the novel structure device increase when the In composition increases. When the In composition is greater than 0.4, the performance of the homotype heterojunction IMPATT is better than that of p-n IMPATT. Moreover, homotype heterojunction IMPATT is better in frequency bandwidth, and it can hold greater bias current density than p-n IMPATT. Meanwhile, the performance of homotype heterojunction IMPATT does not depend on the thickness of the InGaN layer, but it decreases as the thickness of the p-type region in p-n IMPATT increases. As it has greater potential in the application, this work brings a reference for the design and manufacture of IMPATT devices based on wide bandgap semiconductor materials, especially GaN materials.

This work explores the fabrication and characterization of an ionic liquid channel field effect transistor (FET) incorporated within the trench structure on SiO2. The trench structure allows any liquid to be accommodated, thereby eliminating the mold creation on the device or the requirement for an intricate architecture to store liquid. For the fabrication of the trench, we followed a standard photolithography process with the help of selective etching of aluminum and SiO2. The fabricated trench surface is characterized using atomic force microscopy (AFM) and contact angle analysis. The electrical characterization of the proposed FET structure is also performed with 0.01-mM potassium chloride (KCl) solution as an ionic channel. We tested both the n-FET and p-FET type characteristics which can be controlled by the back gate biasing condition. The dc characterization shows a high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of 105 for both the n-FET and p-FET. The device further shows an improvement in K+ mobility and Cl− mobility of $2.24 \times 10^{-4} {\mathrm {m}}^{2}/{\mathrm {Vs}}$ and $4.96 \times 10^{-4} {\mathrm {m}}^{2}/{\mathrm {Vs}}$ , respectively. We also carried out the FET structure modeling to estimate the effective ${C}_{{\mathrm {ox}}}$ for the trench SiO2 structure. It is observed that the total capacitance after the inclusion of Debye length is $1.29 \times 10^{-4} {\mathrm {F/m}}^{2}$ . Furthermore, the number of ions is also calculated from the electrical characteristics, and it is almost comparable with the number of ions in the molar solution. Overall, the proposed fabricated structure, although simple, enables to accommodate any liquid as a channel and provides an easy way to develop electrolyte-based sensors.

Straintronic magnetic random access memory (MRAM) devices based on magnetoelectric heterostructures are gaining much attention because of their ability to perform energy-efficient, nonvolatile magnetization switching. However, practical applications of such devices are often restricted by the requirement of biasing magnetic field to provide the initial magnetization state. This work reports the self-biased, in-plane 180° magnetization switching of FeGaB nanomagnets on PMN-PT piezoelectric substrate. By varying the thickness of the nanomagnets with different aspect ratio, the self-biased operation is obtained for a particular range where the lower limit is imposed by the thermal stability and the upper limit is given by the shape anisotropy energy. We also demonstrate that in-plane 180° magnetization switching for larger aspect ratio nanomagnets is also limited because of the maximum achievable stress from the piezoelectric layer. The underlying physics, including the relationship between the critical switching time and energy, is delineated using finite difference method (FDM) micromagnetic model coupled with elastodynamic and electrostatic conditions.

In this study, we investigate the threshold voltage ( ${V} _{{{ \text {th}}}}$ ) instability of p-gate GaN HEMTs induced by gate bias. Experimental results are acquired by a custom pulse setup for two commercially available devices with an ohmic gate and a Schottky gate. A transient drain current change is observed, which corresponds to a shift of ${V} _{{{ \text {th}}}}$ . A negative ${V} _{{{ \text {th}}}}$ instability is identified for the ohmic gate, a mostly positive for the Schottky gate that can also become negative depending on the gate bias voltage and duration. The impact of the gate-bias-induced ${V} _{{{ \text {th}}}}$ instability on the Schottky-gate device is significantly higher compared to the ohmic-gate device, but clearly noticeable at the nominal rated ON-state gate voltage for both devices. Electron depletion and trapping as well as hole accumulation and trapping are identified to cause this transient ${V} _{{{ \text {th}}}}$ instability.

Direct X-ray detection plays an indispensable role in medical and industrial development. However, developing a stable, low-cost, and sensitive direct X-ray detector is highly desired for future commercial application. In this work, a direct X-ray detector using a straightforward digital printing fabrication process based on nontoxic micropyramid triclinic bismuth oxide ( $\omega $ -Bi{2}O{3}}{) ink is reported. The printed device exhibits a low detection limit of 56.95 $\mu $ Gy $_{\text {air}}\,\,\text{s}^{-{1}}$ with a sensitivity of $3.077~\mu \text{C}$ Gy $_{\text {air}}^{-{1}}$ cm $^{-{2}}$ at 20 V bias voltage, which is better than most of the metal oxide-based direct X-ray detectors reported so far. Furthermore, the $\omega $ -Bi2O3 based X-ray detector shows excellent stability without packaging for eight months and exposure to a dose of 5120 mGyair equivalent to 25 000 chest X-ray scans. The applicability of our array device printed in a direct patterning method as an X-ray imaging detector is shown. Our findings inform a qualified competitor in the medical and industrial fields in the future.

In this work, a method was investigated to extract trench sidewall and trench bottom capacitances of a SiC trench metal–oxide–semiconductor (MOS) structure. Five groups of 4H-SiC trench MOS capacitors were designed and fabricated, with various trench bottom widths and trench mesa widths. High-frequency capacitance–voltage (HFCV) measurements at 100 kHz were performed on these trench MOS structures. The relationships between trench MOS capacitances and the widths of trench bottom as well as trench mesa were studied. As expected, under the same bias voltage, the measured trench MOS capacitances were proportional to the trench bottom widths and trench mesa widths. Based on this, the contributions of capacitances from the bottom, mesa, and sidewall of trench in trench MOS structure were studied systematically. The oxide thicknesses at different locations in trench were extracted. The ${C}$ – ${V}$ characteristics of the MOS capacitors from trench sidewall and trench bottom could also be deduced, from which the flat-band voltage and the charges in oxide of these two MOS capacitors could be subsequently calculated and analyzed. This method provides a convenient and precise technology to monitor process control in SiC trench MOSFETs manufacturing.

In this article, in addition to two commonly known noise parameters—dark count rate (DCR) and afterpulsing (AP)—we explore another interesting phenomenon–random telegraph signal (RTS) noise—during the transitional phase of the avalanching process. We present the properties of the RTS noise and their dependence on the biasing voltage and temperature. An analytical model is used to extract the dimension of the defects in the depletion region from the variation of the RTS noise current amplitude with biasing voltage. By comparing the DCR and AP of single-photon avalanche diode (SPAD) samples with different defect dimensions derived from the RTS noise properties, a trend that the SPAD with a larger defect dimension shows a higher DCR and AP is found.

We analyzed the low-frequency noise (LFN) of dual-gated field-effect transistor (DG-FET) biosensors with Schottky contacts. We found the flicker noise at the sensing insulator–semiconductor interface to be the major noise source while employing Schottky contacts to have minimal noise contribution with a sufficiently large back-gate bias voltage. The measured noise dependence on transconductance further indicated the presence of a nonuniform energy distribution of interface trap density at the said sensing interface. Based on these findings, we argued that the DG structure is advantageous over its single-gated (SG) counterpart; although they possess the same intrinsic lower limit of detection (LLOD), the former could offer a larger signal gain at the optimum LLOD thanks to sufficient channel carrier supply through back-gating instead of biasing the sensing interface toward band edge with higher trap density.

With the increase in frequency, IGBT can generate serious electromagnetic interference (EMI) when it is turned on and off quickly. The variations in voltage and current produced by switching devices in the transient process are the main sources of high-frequency EMI. The ultrafast switching characteristics of IGBT (i.e., high du/dt or di/dt) will cause serious switching oscillation, EMI noise, and additional power loss. The speed of voltage and current variations in transient process is determined by the interelectrode capacitances of the semiconductor switch. Due to the structural characteristics of IGBT, the interelectrode capacitances will change based on the difference in external voltage. This article introduces an improved method to measure the parasitic inductance and resistance of IGBT. This method perfectly avoids the interference of ${Z}_{\text {ground}}$ which refers to the floating terminal impedance to the ground. The parasitic parameters of IGBT can be obtained by fitting the impedance of IGBT with genetic algorithm. The article also introduces a method to measure the parasitic parameters of IGBT on bias voltage with impedance analyzer and dc source. In the experiment, the capacitance is used to protect the impedance analyzer to avoid the dc current from the dc source. Finally, a double-pulse test circuit is used to verify the parasitic parameter model of IGBT measured in this article. By comparing the current and voltage waveforms when IGBT is turned on and off and the voltage frequency domain waveforms in multiple cycles, it is proved that the parasitic parameter model of IGBT is applicable to the circuit.

Current mirrors (CMs) are essential building blocks for biasing electronic circuits. The present work demonstrates that errors in mirroring ratios increase at cryogenic temperatures, for all types of SiGe HBT and CMOS CMs. The sources of errors are attributed to the mismatch in operating conditions and a combination of process variations and layout effects. In particular, the effects of layout on device current are found to increase significantly at low temperatures, which can potentially contribute more to the CM error than process variations. Among all investigated CM configurations, the simple CM based on large geometry SiGe HBTs is the most versatile option with small errors, a large operational range, and a simple layout.

A novel photodetector for imaging in the visible–near infrared range is investigated. Unlike currently used detectors, the proposed device does not require thin-film filters for spectral discrimination. Instead, the discrimination relies on the wavelength-dependent absorption property of semiconductor materials. The detector consists of a window exposing the silicon substrate to the electromagnetic signal. Besides the window, multiple collectors separated by polysilicon gates are laid out. Proper voltage biasing establishes a different spectral response for each collector, thus creating a detection color space. Experimental results demonstrate the color detection capability of a three-collector imaging pixel from sensitivity metamerism index calculations. The sensor is fabricated in a standard 0.35- $\mu \text{m}$ CMOS process and presents a peak combined collectors’ responsivity of 0.35 A/W.

We investigate the temperature dependence of field-effect mobility ( $\mu _{eff}$ ) on amorphous indium–gallium–zinc oxide ( $\alpha $ -IGZO) thin-film transistors (TFTs) having 10-nm-thick HfO2. Thanks for the downscaling of the equivalent oxide thickness (EOT), we observe, for the first time, a temperature-independent $\mu _{eff}$ at a high field or high carrier concentration ( ${N}_{carrier}$ ) regime and a strong temperature-dependent $\mu _{eff}$ at a low field or low ${N}_{carrier}$ regime. The observation highlights the importance of EOT downscaling to enhance ${N}_{carrier}$ and facilitate the Fermi level ( ${E}_{F}$ ) to approach and even exceed the potential barriers’ peak ( ${E}_{M}$ ), leading to a high and temperature-independent $\mu _{eff}$ at high ${N}_{carrier}$ . ${N}_{carrier}$ at which ${E}_{\textbf {F}} = {E}_{M}$ is extracted to be $\sim 6\times 10^{12}$ cm−2. A detailed study of the relationship between EOT scaling and the gate bias voltage ( ${V}_{GS}$ ) at which ${E}_{F}$ equals to ${E}_{M}$ is performed. $\alpha $ -IGZO TFTs with an ultrascaled gate dielectric are capable of alleviating the negative effects from the potential barriers at low ${V}_{GS}$ and could enable low-power applications with high performance. Besides, a weak temperature-dependent subthreshold swing (SS) of $\alpha $ -IGZO TFT was observed and explained.

In this article, a 3-D electrothermal numerical model is used to perform the signal and thermal integrity analysis of 3-D stacked Resistive-switching random access memory (RRAM) arrays. Two main issues are found: voltage drop along the interconnects and thermal crosstalk between the memory cells. Possible solutions to these issues are here thoroughly investigated, based either on new biasing schemes or new materials. Especially, conventional nickel bars are replaced by interconnects made by copper (Cu) and carbon nanotubes (CNTs), whose electrical and thermal parameters are here described using physically based models. The analysis is performed on a $5\times 5\times5$ array, under a real case of a RESET switching, which is the worst case scenario from the electrothermal point of view. Simulation results show that the use of CNTs reduces the voltage drop in both word and bitline (BL) interconnects, thermal crosstalk, and the maximum working temperature; hence, it mitigates many of the crucial issues in the roadmap for the large-scale monolithic 3-D RRAM integration.

In this article, a metal/carbon-doped GaN (GaN:C)/Si-doped GaN (GaN:Si) structure was used to investigate the defect characteristics and carrier transport mechanisms in GaN:C layers with different carbon doping concentration. Capacitance-voltage, current–voltage, and deep-level transient spectroscopy measurements were performed at different temperatures. At forward bias, a pinning effect was found at the interface of the GaN:C/GaN:Si layer, due to the defects capturing electrons. The forward currents of the samples with high carbon doping concentration ( ${N}_{C}> {1} \times 10^{{19}}$ cm−3) increase gradually with increasing forward bias voltage. Ohm’s law, space-charge-limited current, and variable-range-hopping mechanisms may dominate the forward current. For the samples with low carbon doping concentration ( ${N}_{C} cm−3), a device turning on behavior was observed, which is attributed to the carriers overcoming a potential barrier. In addition, the DLTS spectra reveal that only electron trapping happens at forward bias for the samples with high carbon doping concentration, while, in addition, hole trapping was observed for the samples with low carbon doping concentration. The process of the carrier capture by defects was demonstrated.

Integration of body-diode-based back-gate control in AlGaN/GaN high-electron mobility transistors (HEMTs) was recently demonstrated by the authors to enable dynamic control of the device characteristics. Here, we present an experimental study of drain-voltage-induced secondary effects in AlGaN/GaN HEMTs with integrated body-diode. Both the three-terminal and four-terminal device characteristics are studied to understand the secondary effects in this configuration. The results show that the voltage at the drain terminal plays a crucial role in biasing the body-diode under dynamic operation. Drain-voltage-induced dynamic biasing of the body-diode is observed both under the biased and floating back-gate conditions. The kink-effect in the saturation channel current and light emission at the source terminal are observed at higher drain voltages. Our results show that a combination of high resistivity of the p-GaN layer and the direct bandgap nature of III-nitride (III-N) material prevents the parasitic bipolar junction transistor (BJT)-triggered latch-up mechanism in this device structure.

In this article, the physical design and performance of stacked layers of MoO3/Mg/MoO3 (MMM) is investigated by means of X-ray diffraction and biasing-dependent impedance spectroscopy techniques. The amorphous MMM films which are coated onto Au thin-film substrates in a vacuum media of 10−5 mbar are observed to exhibit metal oxide semiconductor (MOS) characteristics. The pMOS and nMOS inversion channels are initiated at biasing voltages of −2.0 and +2.0 V, respectively. In addition, the biasing-dependent spectral analysis of the device has shown that the negativity of the capacitance could be linearly increased or decreased based on the MOS mode and applied voltage value. The engineering of the negative capacitance effect in the device makes it preferable to use as voltage controlled linear oscillators which can be employed for noise reducing and parasitic capacitance cancellation. In addition, the analyses of biasing-dependent reflection coefficient spectra in the frequency domain of 0.01–1.80 GHz have shown that the MMM device exhibits features of bandpass/stop features below and above 1.40 GHz, respectively. The degree of wave transmission can be attenuated by the biasing voltage in the respective channel.

The recently proposed stacked nanosheet-field-effect transistor (SNSH-FET) is considered as a promising candidate for continued scaling with silicon. While using punchthrough-stopper-doped (or) ground-plane-doped silicon substrate (PTS-Si substrate) in which the top part of the substrate is doped heavily with the p-type (for nMOS) impurity to avoid punchthrough leakage between the source and the drain. The heavily doped p–n junction formed at the drain–substrate junction acts as a reverse-biased tunnel diode during ${V}_{{\text {DS}}}$ biasing, which leads to large substrate leakage current. We presented SuperSteep-Retrograde silicon substrate (SSR-Si substrate) configuration which reduces the tunneling current by increasing the tunnel barrier width and diminishing the peak electric field at the drain–substrate junction. The SSR-Si substrate is achieved by growing a lightly doped or undoped layer of silicon (SSR-buffer layer) on the PTS-doped substrate. The impact of SSR-buffer layer thickness is studied and the optimal thickness (12 nm) is presented. The vertically stacked channels’ configuration leads to position-dependent current densities in different channels due to position-dependent series resistance. Herein, we present nanosheet width optimization as a solution to achieve homogeneous current ratio between all the channels thereby resulting in better linearity performance. The self-heating and RF performance of the presented SSR-Si substrate is compared with the silicon-on-insulator (SOI) substrate. The results show that SSR-Si substrate can be a better substrate for SNSH-FET because of better self-heating performance.

In this article, the single-event response of the 1.2-kV silicon-carbide (SiC) power MOSFETs with varied buffer layer designs is investigated by the 2-D numerical simulations. The structural parameters of the buffer layers are compared and analyzed to understand the transient response after the heavy ion strike and the related physical mechanisms comprehensively. Simulation results reveal that an optimized single buffer structure can be acquired by using a relatively thicker buffer layer (T $\mu \text{m}$ ) and a moderate doping concentration (D cm−3). It demonstrates that the single-event-burnout (SEB) performance can be improved significantly under the worst case bias conditions [a drain bias voltage of 1.2 kV and a linear energy transfer (LET) of 1 pC/ $\mu \text{m}$ ]. In addition, the optimized structural combinations adopted in the dual or triple buffer layers can strengthen the SEB performance further. The simulation results show that a step electric field distribution is established inside the optimized dual or triple buffers, where the electric field peak is mitigated from 3 to 2.2 MV/cm. Moreover, the excess carrier generation is suppressed and the local temperature rise is weakened during the transient electrothermal process. Consequently, the structure with the optimal buffer layer designs can enlarge the SEB safe operating area (SOA) from 30%–50% to 100% rated breakdown voltage at high LET bias, which makes the SiC power MOSFETs used in aerospace and aviation power electronic systems become possible.

This brief presents a fabricated and characterized 3-terminal (3T) nanoelectromechanical switch (NEMS) featuring for the first time a sub-50-mV pull-in voltage operation without body biasing. The proposed NEMS demonstrates a low hysteresis ( ${V}/{ {\mu } {\text {m}}}$ and a sub-50-mV swing providing an ultralow active power consumption.

In this article, the atmospheric pressure plasma (APP) treatment method is proposed to solve the instability problem under a long-term electrical bias stress through the semiconductor surface treatment without degrading the excellent electrical characteristics of oxide thin-film transistors (TFTs). The high-energy oxygen radicals produced by the APP without a vacuum system affect the electrical properties by quickly and easily changing the chemical state of the oxygen-related bonds in the semiconductor. Consequently, the amorphous indium gallium zinc oxide TFTs with suitable APP treatment showed excellent bias stress stability and electrical characteristics in comparison with the APP-untreated oxide TFTs. The threshold voltage shift after the negative gate bias stress and positive gate bias stress duration of 1 h significantly reduced from −9.9 to −0.7 V and from +6.7 to +0.5 V, respectively. In addition, the average field-effect mobility remarkably enhanced from 10.8 to 14.8 cm2/Vs and the hysteresis behavior reduced from 0.31 to 0.12 V while maintaining the key parameters of TFTs such as subthreshold swing, ON/OFF ratio, and ${V}_{ \mathrm{\scriptscriptstyle ON}}$ .

In this article, we investigate defect nucleation leading to device degradation in $\beta $ -Ga2O3 Schottky barrier diodes by operating them inside a transmission electron microscope. Such in situ approach allows simultaneous visualization and quantitative device characterization, not possible with the current art of postmortem microscopy. High current density and associated mechanical and thermal fields are shown to induce different types of crystal defects, from vacancy cluster and stacking fault to microcrack generation prior to failure. These structural defects can act as traps for carrier and cause device failure at high biasing voltage. Fundamental insights on nucleation of these defects and their evolution are important from materials reliability and device design perspectives.

This article proposes a nanoscale complementary metal–oxide–semiconductor (CMOS) current reference design for low power analog and digital devices. A self-biased circuit is developed within the current reference. The current reference can compensate for temperature changes and voltage fluctuations. Simulation results showed a low current around 12 nA. The design is capable of working in a broad range of power supply voltages. In the interface with $0.35~\mu m$ fabrication process, a bias voltage is generated with currents in the nanoampere range. The present current reference is qualified to be used in digital-analog circuits, such as operational amplifiers or oscillators, and is designed to be suitable for energy harvesting interfaces, because of the high efficiency and low power consumption.

A CdTe/PbTe heterojunction (HJ) yields two-dimensional electron gas (2DEG) with a high electron density and mobility. Ultrahigh-speed and room-temperature operating mid-infrared photodetectors are developed with the 2DEG. The photoresponse of the detectors originates from the intrinsic response of PbTe by virtue of the conduction-band and valence-band alignment of the HJ. The extremely short rise and decay photoresponse time demonstrate a major advantage of the 2DEG. At $ \lambda = {3.0}\,\, \mu \text{m}$ and a bias voltage of 100 mV, the responsivity and detectivity reach 0.94 A/W and ${2} \times {10}^{{10}}$ Jones, respectively. The excellent performance of the detectors renders promising applications in novel mid-infrared frequency detection systems.

A new and simple kind of all-carbon junction nanodevice, which is free of metal electrodes, is constructed by carbon chains seamlessly connected to two graphyne nanoribbons (GYNRs) electrodes. The electron transport properties of the constructed nanodevices are systematically investigated using self-consistent charge density-functional tight-binding combined with nonequilibrium Green’s function (NEGF) formalism. The effects of contact type and contact position on the electron transport properties of these devices are discussed. The calculated results show that the electron transport properties can be well modulated by the contact geometry of the carbon chain. In GYNRs connected by both horizontal and tilted single-carbon chain, an evident even–odd behavior of conductivity is observed. In addition, the linear, monotonous currents in a wide bias voltage range show good Ohmic contact. The negative differential resistance also appears under both positive and reverse bias voltages, indicating applications in bidirectional tunnel diodes. Comprehensive analyses of the physical mechanisms for the odd–even behavior are given. Remarkably, in GYNRs connected by double-carbon chains, a noticeable current stabilizer behavior occurs, suggesting that the graphyne nanodevices contacted with double-carbon chains can be used as a current stabilizer in circuits. This article provides valuable insight into all-carbon functional nanodevices.

Ferroelectric-doped HfO2-based ferroelectric field-effect transistors (FeFETs) are being actively explored as emerging nonvolatile memory devices with the potential for in-memory computing. In this two-part article, we explore the feasibility of FeFET-based 3-D NAND architecture for both in situ training and inference. To address the challenge of erase-by-block in NAND-like structure, we propose and experimentally demonstrate the drain–erase scheme to enable the individual cell’s program/erase/inhibition, which is necessary for individual weight update in in situ training. We describe the device characterization of different drain–erase conditions and results in this article. The experimental conditions are characterized on 22-nm fully depleted silicon-on-insulator (FDSOI) and 28-nm high- ${k}$ metal gate (HKMG) FeFET devices from GLOBALFOUNDRIES. With appropriate biasing, up to 104 ON/OFF ratio could be achieved by drain–erase. The 3-D NAND array architecture design and verification for in-memory computing will be described in Part II of this article.

A 2-D electrothermal model of delta-doped b eta-gallium oxide ( $\beta $ -Ga2O3) metal–semiconductor field-effect transistor (MESFET) is developed by using TCAD Sentaurus to investigate its electrical and thermal characteristics. The temperature and electric field-dependent electron mobility model is incorporated to predict I – V characteristics of the FET, which are in good agreement with the measured I – V characteristics. We investigated the effect of bias voltages on an electric field, a current path, a volumetric heat generation profile, and a peak temperature at a given total heat dissipation. The peak temperature is observed to be significantly different at the same power dissipation but different bias conditions, e.g., the peak temperature is ~9 K higher when the drain-to-source voltage ( V ds) = 25 V and the gate-to-source voltage ( V gs) = −6 V compared with V ds = 8.3 V and V gs = 2 V at the total power dissipation of 1.16 W/mm. This difference is attributed to the change in the electron Joule heating profile with the applied bias voltage. The effects of the location of the delta-doping layer, the gate–drain spacing, and the source–drain spacing are investigated to guide a future device fabrication. The variation in these parameters mainly affects electrical characteristics such as ON-resistance, saturation current, threshold voltage, and so on. The thermal characteristics, such as peak temperature, temperature profile, and so on, are not significantly affected at a low-power dissipation.

We report high-speed large-area silicon photodetectors (PDs) that were fabricated on silicon-on-insulator (SOI) substrates. These coplanar interdigital PDs were fabricated with finger spacing in the 0.5– $5~\mu \text{m}$ range. One of the detectors, which had an area of $2300~\mu \text{m}^{{2}}$ , achieved a bandwidth as high as 14.1 GHz under a bias voltage of −10 V at a wavelength of 850 nm. Meanwhile, the device with the maximum area of $4300~\mu \text{m}^{{2}}$ also achieved a 7.9-GHz bandwidth, suggesting our detectors are highly suitable for high-speed 850-nm optical receiver and, especially, for large area receiving applications. We established a new transition time and resistor–capacitor ( RC ) equivalent circuit model to analyze and calculate the 3-dB frequency of the coplanar interdigital PD; the model results were well-matched with the measurement results.

Micro-light-emitting diodes ( $\mu $ LEDs) are semiconductor devices that have been shown to have higher luminous efficacy, higher contrast ratio, and higher energy efficiency than existing mainstream technologies based on liquid crystals or organic LEDs (OLEDs). Portable display applications such as wearable devices and head-up display are some of the interesting applications of $\mu $ LED displays. However, this technology has not yet been mass-produced for commercial devices due to process yields, costs, and manufacturability issues. This article presents a novel technology for the heterogeneous integration of a $\mu $ LED matrix display with bipolar complementary metal–oxide–semiconductor (CMOS) DMOS (BCD) circuits that could improve manufacturability by eliminating the need for a dedicated bond stack in the bump-bonding process. To validate the concept, custom high-performance, 2-D arrays of parallel-addressed GaN blue $\mu $ LEDs matrices were fabricated. The individual $\mu $ LED pixel diameters are 20 and 50 $\mu \text{m}$ , respectively, and the overall dimension of the array is $650~\mu \text{m}^{2}$ . In addition, a $\mu $ LED display driver-integrated circuit (IC) with a compact size of $3\times 4.4$ mm2 has been designed, implemented, and verified experimentally for the $\mu $ LED matrices. Measured output optical power-forward bias current-forward bias voltage ( ${P}$ – ${I}$ – ${V}$ ) curves of the individual $\mu $ LED pixel are shown. The $4\times 4\,\,\mu $ LED matrix has also been successfully driven using active-matrix driving and display pictures to demonstrate the function of active-matrix driving are presented.

In this article, we study the ion-sensitive gated bipolar transistor (ISBiT) by forward biasing the source-body diode of the ion-sensitive field-effect transistor (ISFET). Based on theory, extensive TCAD device simulations, and experiments, it is shown that the ISBiT operates at lower gate-voltages with a higher transconductance ( ${g}_{m}$ ) than the ISFET both in subthreshold and near-threshold modes. In addition, overall maximum $g_{m}$ ’s have been obtained for the former when operating in saturation mode. However, in the linear superthreshold operation mode, the ISBiT shows lower $g_{m}$ ’s because of the field-induced mobility reduction. The same trends have been obtained for the pH-sensitivity expressed as $\partial {I}_{\text {D}}/\partial {\text {pH}}$ , since it is linearly dependent on the ${g}_{m}$ , as predicted by the theory. Basically, the ISBiT offers more tunability, hence, freedom in the sensor system.

The impact of scaling of the base layer on the noise performance, spectral responsivity, and frequency response of Ge/Ge1– x Sn x /Ge p-n-p heterojunction phototransistor (HPT) is presented and evaluated by simulation. The proposed structure consists of Ge1– x Sn x alloy in the base layer, allowing extension of the photodetection to the mid-infrared (MIR) region, enabling photodetection over a wide range. This paper also includes the effect of Sn concentration and base bias voltage on the frequency performance of the HPT. In addition, various noise components and signal-to-noise ratio (SNR) are estimated as a function of base layer thickness and base resistance. The simulated results show that cutoff frequency ( ${f}_{T}$ ) and maximum frequency ( ${f}_{\text {max}}$ ) are not only strongly dependent on the base layer thickness but also on the Sn composition in the base layer and applied base-bias voltage. The results show that the proposed HPT provides higher ${f}_{T} >45$ GHz and SNR of >70 dB for the base layer thickness of 50 nm (with Sn = 9%) can be achieved. Therefore, the GeSn p-n-p HPT is promising for future fiber-optic telecommunication and MIR applications.

In this paper, AlGaN/GaN high-electron mobility transistors (HEMTs) with different fin configurations are fabricated and analyzed. Through S-parameter measurements and modeling of the designed devices, a detailed RF investigation on small-signal model parameters is performed under different biasing conditions. Good agreements between measured and simulated scattering parameters up to 40 GHz illustrate the validity and accuracy of the model. The influence of different fin structures on model parameters and linearity improvement is examined, and this can help to improve the frequency characteristics of fin structure by optimizing the fin length, fin width, and trench width. The significant linearity of Fin-HEMTs is confirmed by the analysis of the model parameters, which is the first time to study the small-signal characteristic of AlGaN/GaN Fin-HEMTs in detail.

In this paper, single crystals (SCs) of the Cs2AgBiBr6 double perovskite were grown using the method of crystallization from a supersaturated solution. It was shown that the natural crystal growth surface of the perovskite with perfect crystal quality is along the (111) plane by X-ray diffraction (XRD) and high-resolution transmission electron microscope (HRTEM) analyses. The fabricated high-sensitivity X-ray detector based on the Cs2AgBiBr6 SCs with vertical structure achieved detection sensitivity up to $316~\mu $ CGyair−1 cm−2 under bias voltage of 18 V. Furthermore, the frequency noise characteristics of the device under different posttreatment processes were systematically analyzed, which indicated that the combination of thermal annealing and isopropanol rinsing can suppress field-driven ion migration and surface conduction channel, thereby increasing the resistivity of the perovskite material and reducing the noise current of the device. Our results revealed that the Cs2AgBiBr6 SCs-based X-ray detector with high sensitivity and low cost has a great potential for application in manufacturing lead-free and stable radiation detection electronics in the future.

A recessed barrier layer (RBL) structure is proposed in themicrometer-sized AlGaN/GaN high-electron mobility transistor (HEMT) for terahertz applications. It is found by using numerical simulation that the properly designed RBL structure can trigger the formation and propagation of electron domains in the 2-D electron gas (2-DEG) channel. As a result, the fundamental frequency can be extended even up to terahertz regime, and also it can be tuned in a certain range by the bias voltage of Schottky contact gate that acts as a hot-electron injector just like the notch-dopedGunn diode. Our simulations showthat the 0.3- $\mu \text{m}$ -gate HEMT with the RBL structure having the depth of 10–15 nm and the length of 200–400 nm can generate the stable and tunable oscillations in the range of around 0.8–1.6 THz under the normally gate bias of −0.2–0.4 V, as well as the ratio of RF-to-dc current component ranging from 3.04% to 7.2%. These available characteristics come from the redistribution of electric field in the 2-DEG channel. Compared with the ungated and the top-gated planar Gunn diodes ever reported, the proposed RBL structural AlGaN/GaN HEMT can be easily fabricated and operated under normal conditions, demonstrating a great potential application in terahertz radiation sources.

Thermionic electron emitter, a critical component in vacuum electronic devices, usually suffers from bulky size, difficulty to integrate, and slow temporal response. Here, to overcome these problems, we fabricate and test a new miniature electron emitter: on-chip thermionic electron emitter arrays based on horizontally aligned single-walled carbon nanotubes. The devices are fabricated and integrated on a Si chip with microfabrication technologies, providing compactness as well as fast temporal response. Emitter arrays with a packing density of up to $\sim \textsf {0.4}\times 10^{7}$ emitters/cm2 and an emission density of 1.73 mA/cm2 at a bias voltage of 2.64 V are realized. The turn-on/off response times of the devices are measured to be ~150/500 ns, which are 5 orders of magnitude faster than those of their bulky counterparts. The advantages of on-chip nature, high degree of integration, and fast temporal response make the thermionic emitter arrays promising in miniature vacuum electronic devices.

A novel ultrafast and low-loss lateral injection-enhanced gate transistor (LIEGT) is proposed and investigated by simulation. The device features a MOS-controlled shorted anode (MCSA) and a bias voltage ( ${V}_{{AG}}$ ) applied between the anode trench gate (ATG) and the anode electrode. The n+ anode is shorted to the N-buffer through the MOS channel around the ATG when the MCSA is activated with ${V}_{{AG}} > {V}_{{th}}$ during turn-off and blocking states, and thus the p+ anode/N-buffer junction is unactivated. The MCSA LIEGT turns off as fast as a unipolar device by optimizing the time gap to activate the MCSA before turning off the cathode trench gate (CTG). The activated MCSA would deactivate hole injection from the anode side and synchronously quickly extract the electrons from the N-drift, which improves the switching speed and dramatically decreases the turn-off energy loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ). In the blocking state, the MCSA LIEGT achieves a MOS breakdown mode instead of an open base p-n-p bipolar breakdown mode. Thus, the breakdown voltage (BV) is not only improved but also independent of the p+ anode doping concentration. In the forward conduction state with ${V}_{{AG}} = {0}$ , the MCSA is unactivated and hence the MCSA LIEGT operates like a conventional LIEGT without deteriorating the on-state voltage drop ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ). Compared with the conventional LIEGT, the proposed device decreases ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ by 88% and improves the BV by 13% at the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$ . Importantly, ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ is almost independent of ${V}_{ \mathrm{\scriptscriptstyle ON}}$ .

Several optical and electrical methods have been developed to thermally characterize GaN high-electron mobility transistors (HEMTs) under DC operation. Gate resistance thermometry (GRT) has proven to be an inexpensive and reliable method to estimate the peak temperature. The complex Joule heating profile of a HEMT, however, is highly bias dependent, and its temperature profile under RF conditions may vary compared to the profile generated under DC operation. Evaluating the thermal performance of HEMTs under RF operation is thus necessary to quantify any differences between these two modes of operation. Implementing a differential probe, this paper highlights the capability of using GRT to measure accurately the temperature of GaN/Si HEMTs under RF operation. A larger gate-to-gate spacing is shown to decrease the overall temperature rise, while a linear correlation is found between the power-added efficiency and the junction temperature. The effect of the baseplate temperature on the device’s thermal performance both under steady-state and RF operations is presented. Overall, at a given power density and baseplate temperature, the RF temperature rise is shown to appear lower than its equivalent temperature under DC biasing.

A simple electrical method to extract device channel thermal resistance in transistors is presented here. The method compares the dc to discrete-pulsed characteristics and estimates the effective increase in channel temperature under dc biasing conditions. Using the discrete-pulsed $I$ versus $t$ method, the self-heating of the device is effectively eliminated, which helps avoiding the underestimation of the device channel thermal resistance, therefore, making it possible to perform thermal measurements at the high power operation. This technique was applied to lateral GaN HEMTs with three different substrates as well as vertical GaN current aperture vertical electron transistor (CAVET) on sapphire, which proved its sensitivity and validity for different device structures and geometries.

We analyze the augmentation of spin-transfer torque (STT) MRAM with electrically driven selective phase transition of a threshold switch (TS) to enhance the read operation. This paper provides a comprehensive discussion on necessary design considerations for TS augmented (TSA) MRAMs. We deduce constraints for read and write biasing that yields improved read operation of TSA MRAMs. We explain the dependence of read/write performance metrics on read/write biases and the properties (resistance and critical currents for transitions) of the TS. With proper device-circuit optimization, TSA MRAM shows up to 70% larger sense margin, ~27% higher data stability with ~40% less power for read operation compared to STT MRAM (in nominal condition). We evaluate the impact of variation on TSA MRAM through Monte Carlo simulations. We report that even with variation induced spread in the distribution of bit-line voltages, TSA MRAM provides $\sim 1.7\times $ larger voltage differential between parallel and antiparallel states. For the write operation, the TSA MRAM consumes ~10% less average power and demands only ~5% more write time extension than the STT MRAM to achieve the same level of variation tolerance.

In this paper, a universal analytical current model for a double-gate Si-based tunnel field-effect transistor (TFET) is presented considering the effects of charges in source depletion region and channel. An accurate surface potential model is developed first by solving the pseudo-2-D Poisson equations in the depletion regions, and then is used to calculate the drain tunneling current. The modeling results match well with that obtained from the Technology computer-aided design simulations under various biasing conditions, which indicate that the analytical current model would be very helpful for the further TFET-based circuits design. Furthermore, the influence of the source depletion is also studied, and the presented model with considering the source depletion region and the channel inversion charges is proved to be much more accurate than that ignoring the source depletion.

We study the noncoherent transport due to electron–phonon (e-ph) interaction in graphene nanoribbon (GNR) field-effect transistors (GNRFETs) using nonequilibrium Green’s function method in mode space. Phonon dispersion calculations in conjunction with the e-ph interaction computations show that in an armchair GNR, only a small number of phonon modes are coupled to the carriers. Our simulation shows that under a threshold gate voltage, the drain–source current is diminished by the low-energy phonons such as acoustic phonon modes and radial-breathing-like phonon modes, while at great biases of the gate, the current drop is essentially due to high-energy optical phonon modes. The effect of drain voltage on scattering process is discussed, which shows that at higher drain voltages, the ballisticity decreases. We also explore the phonon scattering dependence on the dimensions of GNRFET channel. In larger width ribbon, the impact of phonon scattering decreases. The channel with a length of 30 nm is ballistic up to 90%, and only when its length is increased to approximately 180 nm, transport becomes semiballistic, which infers to an effective mean free path of ~200 nm.

A nonvacuum thin-film deposition technology called ultrasonic spray pyrolysis deposition method is used to deposit fluorine-doped tin oxide, Al2O3, and TiO2 thin films, both of which are further applied on the anatase TiO2-based thin-film phototransistors (PTs). The material characteristics of the anatase TiO2 such as selected area electron diffraction, X-ray photoelectron spectroscopy, photoluminescence spectrum, and deep-level transient spectroscopy are investigated. The anatase TiO2-based thin-film PTs have a maximum output current of 4.56 mA/mm, subthreshold swing of 171 mV/dec, and threshold voltage of 0.7 V. The photoresponse characteristics of the anatase TiO2-based thin-film PTs at different quiescent-points are measured and investigated. It is found that the present anatase TiO2-based thin-film PTs can be operated in three different modes depending on the $\text{V}_{\text {DS}}$ and $\text{V}_{\text {GS}}$ biasing. In high-responsivity mode, the responsivity is 32.06 A/W; in high detectivity mode, the detectivity is $1.98 \times 10^{10}$ Jones; and in high ultraviolet (UV)-to-visible rejection ratio mode, the UV-to-visible rejection ratio is 1600.

L3 Electron Devices has developed a high-power multibeam inductive output tube (MBIOT) for the European Spallation Source. In July 2014, L3 was awarded a contract for the design, manufacture, and test of a 1.2 MW, 704.42 MHz, pulsed power MBIOT. In October 2016, factory acceptance testing of the L6200 1.2-MW MBIOT was completed at L3 Electron Devices. In October 2017, site acceptance testing was successfully completed at the European Organization for Nuclear Research (CERN). The ten-beam, permanent magnet-focused device meets the maximum 1.2-MW output power specification with a dc-to-RF efficiency of 70%; efficiency is maintained above 60% down to 650 kW. Factory testing at L3 was limited to a cathode voltage of 43.6 kV and a maximum pulsewidth of $200~\mu \text{s}$ . The CERN MBIOT test stand enabled operation at the preferred cathode voltage of 45 kV and at the full pulsewidth of 4 ms. The CERN test stand also offered the ability to individually adjust the filament voltage and bias voltage to each gun, which was not possible with the L3 test configuration. The CERN test stand and MBIOT are currently being prepared to demonstrate long-duration operation.

The development of steady-state thermal characterization techniques for AlGaN/GaN high-electron mobility transistors (HEMTs) has been used to measure the device’s peak temperature under DC conditions. Despite these methods enabling the accurate quantification of the device’s effective thermal resistance and power density dependence, transient thermometry techniques are necessary to understand the nanoscale thermal transport within the active GaN layer where the highly localized joule heating occurs. One technique that has shown the ability to achieve this is transient thermoreflectance imaging (TTI). The accuracy of TTI is based on using the correct thermoreflectance coefficient. In the past, alternative techniques have been used to adjust the thermoreflectance coefficient to match the correct temperature rise in the device. This paper provides a new method to accurately determine the thermoreflectance coefficient of a given surface and is validated via an electrical method: gate resistance thermometry (GRT). Close agreement is shown between the temperature rise of the passivated gate metal measured by TTI and the averaged gate temperature monitored by GRT. Overall, TTI can now be used to thermally map GaN HEMTs under pulsed conditions providing simultaneously a submicrosecond temporal resolution and a submicrometer spatial resolution.

In this paper, we fabricated In0.53Ga0.47As-on insulator (OI) MOSFETs on Si substrates with different doping types to mimic ground plane doping using direct wafer bonding and epitaxial lift-off (ELO) techniques. We investigated the impact of doping types on the ground plane and the backgate biasing, which are important and preferable components in monolithic 3-D (M3D) integration, on the electrical properties of MOSFETs, such as the threshold voltage ( ${V} _{T}$ ) and the effective mobility ( $\mu _{\textsf {eff}}$ ). It was found that ${V} _{T}$ and $\mu _{\textsf {eff}}$ were significantly modulated by the backsubstrate doping and the backbiasing. These observations were explained by the change of carrier distributions, which were confirmed by technology computer-aided design simulation. Furthermore, we investigated the reusability of InP donor substrates for sequential epitaxial growth after ELO process toward a cost-effective M3D integration with the In0.53Ga0.47As channel.

A new hybrid method for estimating channel temperature and extracting the AlGaN/GaN high electron mobility transistors (HEMTs) model parameters is proposed in this paper. The method studies the temperature-dependent feature of access resistances and estimates the channel temperature of tested device by using a novel scanning channel temperature optimization approach. For the first time, the relationship between thermal resistance ( ${R}_{\mathsf {th}}$ ) and bias voltage is used to ensure the accuracy of the HEMT device model. The estimated channel temperatures are experimentally verified by using the Raman spectroscopy method. For different sizes of the AlGaN/GaN HEMT device, the simulation results based on the proposed model are compared with the conventional model as well as the commercial model, a better agreement with the measurement data for the proposed method is achieved.

An extensive investigation of fabricated AlGaN/GaN fin-shaped metal-insulator-semiconductor high-electron-mobility transistors (Fin-MISHEMTs) with Al2O3 dielectric is presented in this paper. Based on the pulsed I–V measurements and numerical simulation, the dynamic characteristics of GaN-based Fin-MISHEMTs were carried out under various quiescent bias conditions and temperatures. Moreover, the physical mechanisms of current collapse and dynamic on-resistance increase induced by trapping effects were analyzed. The results show that the observed nonmonotonic variation of current collapse with the gate quiescent bias voltage is resulted from the combination of gate leakage injection-related and hot-electron injection-related trapping effects. Compared with the conventional planar MISHEMTs, the current collapse of AlGaN/GaN Fin-MISHEMTs is smaller due to lower gate leakage and smaller threshold voltage shift, which is benefited from its enhanced gate controllability. The current collapse and dynamic on-resistance increase of Fin-MISHEMTs can be further suppressed by optimizing the device structure, such as designing the fin channels only under the gate.

In the double-drain multistate electrostatically formed nanowire transistor (MSET), the electrostatically formed conduction channel shifts laterally by properly biasing the two side gates that enclose the bulk area. This current switching mechanism enhances functionality within a single device and sets the stage for a family of integrated-circuit building blocks that facilitate the implementation of ultralow-power Internet-of-Things applications. This paper establishes a conceptual framework for the MSET-based nand gate whose speed and power consumption are analyzed via TCAD simulations.

In this paper, both planar and mesa homojunction p-i-n HgCdTe electron-avalanche photodiodes (e-APDs) are fabricated and investigated to better understand the dark current transport and electron-avalanche mechanisms of the devices and optimize the structures. The experiment results are agreed well by simulated ${I}$ – ${V}$ characteristics based on established numerical models. Our results show that the multiplication region fabrication process leads to enormous characteristic difference between planar and mesa diodes. Shockley–Read–Hall and trap-assisted tunneling current are the main components of dark current for the planar/mesa junction under low bias voltage, and dark current is mainly influenced by band-to-band tunneling and avalanche current when higher reverse bias is added. In addition, we found that the difference between the uniformity of the electric field distributions in multiplication regions is the primary reason for the differences of the dark current. It was also proved that the dark current of planar e-APDs is dramatically affected by the junction corners, and mesa e-APDs dark current is found to be greatly dependent on the multiplication region thickness. Our work provides a great deal of theoretical basis for dark current formation and the avalanche mechanism of HgCdTe e-APDs.