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Several miniaturized viscometers, or microviscometers, have been developed exploiting numerous rapid prototyping techniques. Among them, paper microstrips, famously known as microfluidic paper-based analytical devices ( $\mu $ PADs), have become popular due to their cost-efficacy, simple fabrication, fast response, and easily disposable. Many fabrication methods are existing to develop paper microstrips. Herein, an alternative fabrication method is proposed where fused deposition modeling (FDM)-based 3-D printer (3DP) has been employed using polycaprolactone (PCL) filament. F, image processing has been utilized to measure viscosity in such microfluidic domain. Viscosity was calculated by measuring the time taken by the fluid to cover a fixed length between two spots in the microchannel based on the programed and color-coded regions-of-interest. The image processing program was developed considering the change in the gray scale in the virtual region of interests (ROIs) in the microchannel during the fluid flow in the paper microstrips. A 3-D printed handheld platform, containing raspberry pi with on-board camera and display, was developed to execute the image processing and automate the entire work flow. In the proposed device, the accuracy was measured to be >92%.

Oxide-based thin-film transistors (TFTs) with a lateral in-plane electrode are self-assembled on paper substrates, and the electrical modulation effect of the in-plane electrode is investigated. A SiO2-based solid-electrolyte film with high specific capacitance is used as the gate dielectric, and the operation voltage is reduced to less than 2.0 V. The threshold voltage (Vth) of such paper TFTs is tuned from -0.98 to 0.94 V by different voltage biases on the in-plane electrode. The threshold voltage shift (ΔVth) can be described by ΔVth = -(CG2/CG1)VG2, where CG2 and CG1 are the in-plane electrode and bottom-gate specific capacitance values. High electrical performance with a current on/off ratio of 6 ×105 ~ 106, a subthreshold swing of 0.14 ~ 0.19 V/dec, and a mobility of 8.64 ~ 9.45 cm2/V·s is obtained at different in-plane electrode voltage biases. Such low-voltage paper TFTs are promising for low-cost and portable electronics.

The electrophoretic display (EPD) is the main solution to electronic papers, but most of them can display the image or text in black and white particles only. The users may prefer the EPD showing multiple colors rather than the black/white content only. In this paper, we introduce the driving system for a color EPD, which is composed of three kinds of particles. The system aims at optimizing the visual quality based on a new driving waveform by equipping with an optimization method for color and tone reproduction. The experimental result shows that the proposed EPD driving system can display three-color pictures with promising visual quality.

In this paper, a fully controlled photocatalytic reduction of graphene oxide (GO) sheets is presented in which electrical bias is applied in combination with UV illumination. It is proved that this controllability allows higher conductivities and lower UV illumination times for the achieved reduced graphene oxide (rGO) sheets, which are not allowed without gate voltage. We attribute the observed enhancement mechanism in photocatalytic reduction to electron accumulation at the ZnO/GO interface and decrement of recombination of photogenerated carriers. Then, we applied ZnO nanowires to reduce the GO sheets locally and realize rGO ribbons. The optoelectric response of the fabricated photodetector based on the realized rGO ribbon shows that by controlling the photocatalytic reduction, we can achieve a tunable/selective photodetector ( $\lambda _{\mathrm {incident}} = 520$ , 595, and 633 nm have been investigated). These functionalities allow tuning the output sensitivity of the device in response to different incident wavelengths along the fabrication process or even after the fabrication process. We believe that the presented approach introduces a new generation of tunable devices suitable for different application fields, including optoelectronics.

A single atomic layer of graphene, integrated onto an undoped bulk substrate in a back-gated transistor configuration, demonstrates surprising strong photoconduction, and yet, the physical origin of the photoresponse is not fully understood. Here, we use a detailed computational model to demonstrate that the photoconductivity arises from the electrostatic doping of graphene, induced by the surface accumulation of photogenerated carriers at the graphene/substrate interface. The accumulated charge density depends strongly on the rate of charge transfer between the substrate and the graphene; the suppression of the transfer rate below that of carrier’s thermal velocity is an essential prerequisite for a substantial photoinduced doping in the graphene channel under this mechanism. The contact-to-graphene coupling (defined by the ratio of graphene–metal contact capacitance to graphene’s quantum capacitance) determines the magnitude of photoinduced doping in graphene at the source/drain contacts. High-performance graphene phototransistors would, therefore, require careful engineering of the graphene–substrate interface and optimization of graphene–metal contacts.

We present a computational study on hybrid nanomaterial-insulator-silicon solar cells where single-walled carbon nanotube or graphene forms the emitter as well as top conducting electrode on n-type crystalline silicon having a thin interfacial tunnel oxide. The effects of nanomaterial doping and tunnel oxide thickness on cell characteristics are modeled. Similar to bulk emitters, cell efficiency could be increased by chemical doping (p-type) of the nanomaterial. Unlike bulk, nanomaterial could get electrostatically doped (n-type) due to its low quantum capacitance, by the surface charge density in silicon. For chemically undoped graphene on lightly ( $10^{{16}}$ /cm $^{{3}}$ ) doped silicon, efficiency loss due to the electrostatic doping effect is $\sim 11$ %. A moderate p-type chemical doping (0.2 eV shift in Fermi level) of graphene reduces the aforementioned loss to $\sim 2$ %. The electrostatic doping effect in carbon nanotube-based cells is relatively small and independent to nanotube’s chemical doping. For tunnel oxide thickness $\ge 2$ nm, photogenerated carrier accumulation at silicon/oxide interface considerably enhances the electrostatic doping effect. The effect of tunnel oxide thickness variation on fill factor and open circuit voltage is shown to be qualitatively similar to standard bulk metal–insulator–silicon solar cells. Our model predicts an optimal oxide thickness of $\sim 1$ nm which confirms the experimental reports.

An electrophoretic display (EPD) cell with a triple-layered microcavity structure was fabricated using a convenient dry film resist. The inherent structural advantage arising from the function of the middle channel layer as a background colored state enabled the EPD to operate with two different-colored states by using a single type of electronic-ink particles, thereby eliminating the possible agglomeration of oppositely charged ink particles and supporting the potential application of the proposed structure to color the electronic paper. The preliminary operation of this new EPD structure was demonstrated as white and blue display states on a rigid glass exhibiting a contrast ratio of 1.5 : 1 with saturation voltages of + 30 and -30 V, respectively. Successful demonstrations on both the indium-tin-oxide-patterned glass and flexible polyethylene substrates are also provided.

A high-resolution active-matrix microencapsulated electrophoretic display (EPD) driven by polycrystalline-silicon thin-film transistors (poly-Si TFTs) with integrated drivers has been developed for the first feasibility study of electronic paper. The poly-Si TFTs were fabricated with a low temperature process below 425/spl deg/C. Microencapsulated electrophoretic material was coated on the TFT backplane, which was driven at 18 V. The resolution of the display is quarter VGA (video graphics array), and pixel pitch is 131 ppi (pixels per inch). As a result, this display offers a wide viewing angle, high contrast ratio and nonvolatilization of data. In addition, four-level grayscale images were also achieved by using an area ratio grayscale (ARG) driving method.

We propose a new kind of cathode-ray tube, namely, the thermal-transmission cathode-ray tube (TTCRT). In the TTCRT the electron beam focused to a small spot is called upon to heat in sequence small elements of a matrix that constitutes the faceplate of the tube. A heat-sensitive or thermal paper passed across the screen and maintained in contact with it, and outside the tube, will record characters and dot patterns generated through suitable two-dimensional deflection of the electron beam. We give a description of the main parameters regulating the performance of the TTCRT.

We report in this paper the design and fabrication of single-chip alternating current-LEDs (AC-LEDs) by monolithically integrating, for the first time, high-breakdown Schottky barrier diodes (SBDs) and micro-LED arrays using III-nitride LED epi-wafers of standard specs for volume production. A technique of cyclic mixed-etching has been introduced to restore the surface of inductively coupled-plasma (ICP) etching processed gallium nitride to device quality for fabricating high-breakdown Schottky junctions. Proof-of-concept single-chip AC-LED devices and a prototype driver-free white AC-LED lamp were demonstrated, showing high-efficiency LED emission, high chip area utilization efficiency, low power loss of the on-chip SBD bridge rectifier, and good luminous efficacy of the prototype AC-LED lamp. This paper paves the way toward mass-producing reliable and low-cost driver-free AC-LED lamps for solid-state lighting with existing LED manufacturing infrastructures.

This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 °C–500 °C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation.

Quantum dot (QD) white light-emitting diodes (LEDs) are promising devices in illumination and display applications, and the low thermal stability of QDs is one of the biggest problems limiting their practical use. In this paper, we proposed a metal-based inverted packaging (MIP) structure to enhance the thermal performance and stability of QD white LEDs. The results indicate that the thermal power of LED chips can greatly increase the surface temperature of QD white LEDs, especially that of the color-converted layer and the base. Therefore, the LED chip was separated from the QD layer and isolated with low thermal conductivity layers of air and glass using the MIP structure. This successfully reduces the base temperature and constrains the thermal power of the LED chip on the upper phosphor layer, thus enhancing the thermal performance for the QD layer. Consequently, MIP-QD white LEDs have a small deviation of 57.3 K in their correlated color temperature (CCT) and a deviation of 0.29 in their color rendering index (CRI) at injection power values in a wide range of 0.08–1.3 W, with mean values of 4382 K and 90.3, respectively. Moreover, these devices have negligible reduction in their electroluminescence intensity, and CCT and CRI values after aging for 10 h under severe conditions at an injection power of 0.9 W. Consequently, this paper can provide a general guide to enhance the thermal performance and stability of QD white LEDs by separating the thermal power of the LED chip from the QD layer.

Photodetectors (PDs) based on organic–inorganic hybrid materials such as graphene and perovskites have recently emerged at the forefront of the research in optoelectronic devices. Despite the remarkable progress in the performance of optoelectronic devices based on hybrid materials, some aspects such as stability have so far not been thoroughly addressed. This paper serves to demonstrate a fully inkjet-printed PD fabricated by hybrid perovskite (CH3NH3PbClx-3I3) layer between the two graphene electrodes as graphene/perovskite/graphene (GPG) heterostructure. The fully inkjet-printed GPG PD is found to be effective for the visible light region, which can be attributed by the high uniformity and low defects of the printed materials. Thus, the GPG PD achieves a high responsivity of 0.53 A/W. Fully inkjet-printed hybrid perovskite PD demonstrated in this paper unveils the facile, potentially large-scale and cost-effective methods for fabrication of hybrid perovskites-based optoelectronic devices, including PDs and solar cells.

In this paper, we propose a novel reconfigurable ferroelectric FET (R-FEFET), which can reconfigure its operation between volatile and nonvolatile modes during run-time by dynamically modulating its hysteresis. The R-FEFET comprises of two gates with ferroelectric (FE) in both the gate stacks. One of these terminals serves as a regular gate, while the other is used as a control to introduce reconfigurability. Employing Landau–Khalatnikov equation-based FEFET model, we extensively analyze the device characteristics in both FinFET and planar technologies. We show that by changing the control voltage between 0 and 1 V, the hysteresis width (HW) can be modulated between 1.1 and 0.3 V. In addition, we show the device characteristics and advantages that R-FEFETs possess to overcome the drawbacks encountered with gate leakage in standard FEFETs. The hold margins in the nonvolatile mode of R-FEFETs increase by ~ $10\times $ with respect to standard FEFETs, and the drive current strengths in the volatile mode show 13% improvements when compared to standard FETs. Using the proposed R-FEFETs, we examine a low-power nonvolatile memory design in Part II of this paper.

International audience; Abstract:This paper details an extraction procedure to fully model the transient self-heating of transistors from a GaN HEMT technology. Frequency-resolved gate resistance thermometry (f-GRT) is used to extract the thermal impedance of HEMTs with various gate widths. A fully scalable analytical model is developed from the experimental results. In the second stage, transient thermoreflectance imaging (TTI) is used to bring deeper insights into the HEMTs' temperature distribution by individually extracting the transient self-heating of each finger. TTI results are further used to successfully validate the f-GRT results and the modeling of the thermal impedance. Overall, f-GRT is demonstrated to be a fast and robust method for characterizing the transient thermal characteristics of a GaN HEMT. For the first time to the authors' knowledge, a scalable model of the thermal impedance is extracted fully from experimental results.

In the domain of printed electronics (PE), field-effect transistors (FETs) with an oxide semiconductor channel are very promising. In particular, the use of high gate-capacitance of the composite solid polymer electrolytes (CSPEs) as a gate-insulator ensures extremely low voltage requirements. Besides high gate capacitance, such CSPEs are proven to be easily printable, stable in air over wide temperature ranges, and possess high ion conductivity. These CSPEs can be sensitive to moisture, especially for high surface-to-volume ratio printed thin films. In this paper, we provide a comprehensive experimental study on the effect of humidity on CSPE-gated single transistors. At the circuit level, the performance of ring oscillators (ROs) has been compared for various humidity conditions. The experimental results of the electrolyte-gated FETs (EGFETs) demonstrate rather comparable currents between 30%–90% humidity levels. However, the shifted transistor parameters lead to a significant performance change of the RO frequency behavior. The study in this paper shows the need of an impermeable encapsulation for the CSPE-gated FETs to ensure identical performance at all humidity conditions.

In this paper, a novel vertical phototransistor was reported and compared with planar phototransistors for the first time. As compared with the planar phototransistors, the vertical ones exhibited much better photoelectric performance, which is attributed to an ultrashort photo-generated holes transfer distance and a stronger excitons dissociating electrical field due to their ultrashort channel length (tens of nanometers). Moreover, in order to examine the transport and trapping of different carrier charges separately, the impact of [6,6]-phenyl C61-butyric acid methyl ester (PCBM) dopant on the performance of planar and vertical phototransistors was investigated. The vertical devices exhibited an ultrahigh responsivity (~6600 A/W) as well as an excellent detectivity ( $\sim 7\times 10^{15}~\text{Jones}$ ) and a fast photoresponse (rise time of 0.28 s), whereas slight changes were observed in the planar ones with doping of PCBM. The high performance of the blend vertical phototransistors is due to the trapping of the photo-generated electrons with PCBM and the effective transport of holes due to the ultrashort channel length. This paper provided a promising pathway for low-cost, high-performance phototransistors.

The instability of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under ultraviolet (UV) light was thoroughly investigated in this paper. Unlike in a darkened state, an off-state leakage current can be found in the dual-sweep I–V transfer curve of a-IGZO TFTs under UV light illumination. Furthermore, despite the same UV light condition, the forward sweep and reverse sweep show different I–V curves, representing two different physical mechanisms. First, the subthreshold swing degradation and threshold voltage shift to the negative direction in the forward sweep are due to the total channel barrier lowering and can be confirmed by changing the light exposure region. Second, in the reverse sweep, the suggested back-channel leakage current can be controlled by dual-gate TFTs. UV light exposure of the metal–insulator–semiconductor–metal structure verifies that the off-state leakage current passes through the back channel in a reverse sweep. Finally, the physical mechanism links between forward and reverse sweeps have comprehensive interpretation in this paper.

In this paper, we have developed a physics-based analytical model for the electrical characteristics of passivated silicon carrier-selective contact (CSC) solar cells and validated it with numerical simulations. The model comprises analytical solutions of: 1) the Poisson equation, accurately capturing the level of inversion and accumulation at the crystalline silicon (c-Si) layer interfaces, and 2) the recombination current capturing the various recombination mechanisms at work in the solar cell. The calculations establish that CSC solar cells have the potential to achieve an efficiency greater than 26% even when both c-Si interfaces have realistic SRV values of 100 cm/s. The model helps illustrate the physics underlying the performance of CSC solar cells for variation in key device parameters such as surface recombination velocities, bulk lifetime, contact layer doping, and amorphous silicon (a-Si) thickness amongst others. By circumventing the need for resource-intensive numerical simulations, the analytical model described in this paper can assist in the design and development of high-performance CSC solar cells.

In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, the basic memory operations and write disturbances of the unit cell are investigated through the mixed-mode technology computer-aided design simulations. The unit cell exhibits the superior SRAM characteristics including a write speed of 0.6 ns, a fast read-out speed of ~0.1 ns, and a retention time of 3600 s. Furthermore, the unit cell design exhibits advantages in density, with a small cell area of 8F2, and in the power consumption; the standby power consumption is 0.24 nW/bit for holding “1” and negligible for holding “0.” Moreover, our SRAM array shows reliable ${3} \times {3}$ array operations without any disturbances. This paper demonstrates the promising potential of the FBFET SRAM for high-performance, high-density, and low-power memory applications.

In this paper, the threshold voltage characteristics of silicon nanowire metal–oxide–semiconductor field-effect transistor (MOSFET) with a double-layer gate structure are presented. This type of device is considered to be the most promising application of nanodevice in ultralarge-scale integration, due to several advantages such as similar operation principle as the junctionless nanowire transistor, the screening effect of the upper gate (UG) to shield the lower gate MOSFETs from external electromagnetic disturbance, the tradeoff between the short channel and the thick-gate oxide layer, and the compatible fabrication process with the conventional MOS technology. In this paper, the relations of threshold voltage versus the gate length, the UG bias, the substrate bias, the drain bias, and the temperature are measured and analyzed. Moreover, the penetration effect of the UG electric field is proposed to interpret the short-channel characteristics of the device, and a piecewise curve model is presented to reveal the underlying physics of the relation of the threshold voltage versus the drain bias. The double-layer gate structure technology enables the design of many devices, such as small-signal analog circuit units, single-electron devices, and quantum bit cells.

We demonstrate, for the first time, resistive RAM (RRAM) arrays where each cell can store 3 bits. Such full array-level demonstration is possible through special techniques (e.g., that exploit RRAM-specific characteristics of variations in cell resistances), presented in this paper, which efficiently allocate resistance range corresponding to each bit combination (required for proper write operation) while maintaining appropriate sensing margin (required for proper read operation). Our techniques are not restricted to 3 bits-per-cell only (and, in this paper, we demonstrate 2 bits-per-cell at the array level as well). Our measured results are based on multiple 4 Kbit arrays of 1T1R HfOx-based RRAM integrated in the back end of the line of 130-nm silicon CMOS technology. We achieve 3 bits-per-cell (2 bits-per-cell) RRAM with 11 (3) programing iterations on average.

The application of capacitive deep trench isolation (CDTI) as a shared vertical transfer gate (VTG) in a back-side-illuminated CMOS image sensor pixel is investigated using 3-D device-level simulations. The parasitic capacitance existence between CDTI and deeply buried pinned photodiode (BPD), and also between CDTI and floating diffusion (FD) region, makes the charge transfer process more difficult. In order to design a lag-free pixel and obtain complete charge transfer from BPD to FD, various considerations regarding the device-level design should be taken into account which is discussed in this paper. A CDTI neighboring two pixels can be functionalized as a shared VTG. Using CDTI as shared VTG facilitates pixel miniaturization and can result in more circuit integration at the pixel surface. This paper proposes a ${2}\,\,\mu \text{m} \times {2}\,\,\mu \text{m}$ pixel with CDTI as shared VTG, an equilibrium full-well capacity of 4605 e−, and a complete charge transfer from BPD to FD.

This paper analyzes the performance of mosaic nonimaging passive infrared (PIR) sensors fabricated by the CMOS–SOI–MEMS technology. The elementary sensor, forming a subpixel, is a thermally isolated nanomachined CMOS transistor, dubbed TMOS, operating at subthreshold. The mosaic uncooled PIR sensors are composed of several TMOS subpixels, which are electrically connected, either in parallel or in series as well as a combination of both options. These mosaic sensors, which are manufactured by nanofabrication methods, exhibit enhanced performance and robust manufacturing on wafer level. The overall figures of merit of these sensors, which are modeled in this paper, indicate why they are most suitable for consumer electronics, including smart homes, wearables, Internet of Things as well as mobile applications.

This paper demonstrates a high-performance black phosphorus nanoribbons field-effect transistor (BPNR-FET) and systematically investigates methods for enhancing its anisotropic carrier transport. The BPNR-FET shows a strong dependence on crystal orientation in which the best mobility performance is achieved in armchair-oriented nanoribbons. A downscaling of nanoribbon width is shown to improve the short-channel effect owing to a better electrostatic gate control. Furthermore, hydrogenation is employed to effectively passivate the dangling bonds and heal the nanoribbon edge defects, leading to nearly hysteresis-free transfer properties. By virtue of bandgap and contact-metal workfunction engineering, n-type BPNR-FET is successfully demonstrated, which enables complementary inverter circuits to be simultaneously realized. This paper unravels the superior performance underscores a conceptually new BPNR-FET, paving the way toward the development of non-planar devices and integrated circuits based on 2-D materials platform.

In this paper, we report on the assessment of self-amplified silicon–oxide–nitride–oxide–silicon (SONOS) memory device architecture for sub-50-nm gate length ( ${L}_{g}$ ) through calibrated simulations. Self-amplification (SA) effect in tunnel field-effect transistor-based SONOS (T-SONOS) memory device has been analyzed. Results show that memory window ( $\Delta {W}$ ) in T-SONOS cell increases as buried oxide thickness increases due to capacitive coupling between the front and back gates. Although the enhanced $\Delta {W}$ can also be achieved in inversion-mode SONOS (I-SONOS) device, its performance is deteriorated when the gate length is scaled down. We have compared the performance of I-SONOS and T-SONOS memory devices for ${L}_{g}$ varying from 100 to 25 nm. Results highlight that I-SONOS device cannot be programmed at ${L}_{g} ={25}$ nm and thus deteriorate the memory operation. However, SA T-SONOS at ${L}_{g} = {25}$ nm achieves ${W} \sim {6}$ V. In addition, the effect of underlap on the performance of T-SONOS cell has been analyzed, and it is shown that memory operation of 25-nm T-SONOS device can further improved with a drain side underlap of 20 nm. This paper provides new opportunities to design SA T-SONOS memory device for the next-generation nonvolatile memories.

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications.

Most thin-film transistor (TFT) gate drivers integrated on the display panel use the carry signals between the stages. In our previous works, we found that these carry-type gate drivers are subject to the reliability problem in a flexible display, since the errors of the stressed stages are accumulated through the carry signals. This problem possibly leads to the failure of image refresh of the display device. Therefore, the carry-free gate driver can resolve the error accumulation problem since it does not use the carry signals and instead, each unit stage operates independently. In this paper, we propose an advanced carry-free gate driver circuit to remove the drawbacks of the previous version, while keeping the advantages. More importantly, this paper is the first report to experimentally show that the error accumulation phenomenon of the carry-type gate driver and the problem is removed in the carry-free gate driver. The proposed carry-free gate driver and the carry-type gate driver are fabricated with amorphous indium-gallium-zinc-oxide TFTs on a flexible substrate for comparison purpose. The proposed gate driver shows a very high reliability since no voltage fluctuation occurs at the outputs after 10 000 cycles bending test with 2-mm bending radius.

Quantum dots (QDs) show a great potential for light-emitting diodes (LEDs) packaging, which still face great challenges compared with the matured phosphor downconversion materials. These are probably caused by the unique scattering and absorption properties of QDs, which are extremely different to the traditional phosphor due to their several nanometers size, while their effect on QDs-converted LEDs (QCLEDs) is barely studied. In this paper, we have experimentally and theoretically investigated the effect of scattering and absorption of CdSe/ZnS QDs on the optical performance for QCLEDs by comparing with the traditional yttrium aluminum garnet phosphor. Results indicate that the strong absorption (reabsorption) of QDs causes low radiant efficacy and stability for QCLEDs; their weak scattering also leads to a low color uniformity. It demonstrates that their unique scattering and absorption properties are key factors leading to low optical performance of QCLEDs compared with the traditional phosphor-converted LEDs. For purpose of gaining the white LED with high efficiency and stability, it is highly suggested to use a low QD concentration to reduce the reabsorption loss and the total internal reflection loss. We believe that this paper can provide a better understanding of improving the optical performance for QCLEDs from the prospective of scattering and absorption. In the future, it is important to use low QD concentration to gain high-performance white LEDs with high downconversion efficiency by optimizing packaging structures.

With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation. The anisotropic thermal conductivity of nanosheets with the dependence of silicon thickness and temperature is implemented in the FEM simulator to evaluate thermal behavior accurately. The impact of layout design on thermal properties is investigated comprehensively from single device to device arrays with implication on electrical performance. The results indicate that the width of nanosheet is the key parameter to make the tradeoffs between self-heating and electrical characteristic. Meanwhile, the optimizations of layout design are given to suppress the thermal effects, including self-heating, nonuniformity of temperature, and thermal crosstalk at device level. This paper will provide guidelines for layout design, thermal management, device performance, and thermal-aware reliability prediction in the GAA-stacked structure.

In this paper, a ZnO-based semiconductor thin film memristor (300 nm in thickness) device is fabricated using metallic top and bottom electrodes by direct-current reactive magnetron sputter. The memristive characteristics of the device were completed by time-dependent current–voltage ( ${I}$ – ${V}$ - ${t}$ ) measurements, and the typical pinched hysteresis ${I}$ – ${V}$ loops of the memristor were observed. This paper is continued with the designing memristor emulator circuit, which has only four MOS transistors. The proposed circuit is suitable both for emulating the fabricated memristor and for using general memristor-based applications. Any circuit blocks such as a multiplier or active element are not used in the circuit to obtain memristive characteristics. All results of the proposed memristor emulator circuit are compatible with general characteristics of the fabricated semiconductor device. The MOSFET-based proposed memristor emulator circuit is laid out in the Analog Design Environment of Cadence Software using 180-nm TSMC CMOS process parameters and its layout area is 366 $\mu \text{m}^{\textsf {2}}$ . So as to show its performance, the dependences of the operating frequency and process corner as well as effects of radical temperature changes have been investigated in the simulation results section.

An innovative complementary electric split-ring resonator metamaterial (MTM) structure applied as the slow-wave circuit for a cascade backward-wave oscillator (CBWO) operating in C-band is studied in this paper. The idea of a drift tube in a multiresonant cavity extended interaction klystron is borrowed to design a novel backward-wave oscillator (BWO). The construction of this device features two BWOs separated by a short cutoff waveguide for permitting the flow of the electron beam and stopping the electromagnetic wave. The high-frequency characteristics are analyzed and optimized by using a high-frequency structure simulator and computer simulation technology (CST). Meanwhile, the S-parameter retrieval approach is used to retrieve the effective permittivity and permeability. In addition, the CST code is adopted to investigate the performance of the MTM-based CBWO. The particle-in-cell simulation results show that the novel CBWO is capable of achieving over 51.77% electronic efficiency from 4.8344 to 4.8687 GHz. Meanwhile, the maximum electronic efficiency can reach 82.44%, corresponding to a peak output power of 14.51 MW at 4.8466 GHz. These results indicate that the MTM-based CBWO proposed in this paper has the characteristic of miniaturization, manufacturability, and high electronic efficiency.

In this paper, we investigate the impact of gate–source/drain underlap on short-channel behavior of junctionless (JL) transistor through a quasi-analytical model and 2-D numerical simulations. The proposed five-region model for potential is developed for the symmetric mode operation of double-gate (DG) JL MOSFET in the subthreshold regime, to predict and minimize short-channel effects (SCEs) using the optimum design of underlap regions. The five-region model can be transformed into four or three regions to incorporate the possible dependence of biases, doping, and gate workfunction with the underlap length. The parameters indicating SCEs can also be extracted using an analytical approximation for subthreshold drain current. The results from the proposed model are in reasonable agreement with simulation data. Analyses show that underlap length is a critical parameter to restrict the lateral extension of depletion region into the ungated portion. With increasing the underlap length, SCEs improve prominently for moderate doping concentration ( $10^{18}$ cm $^{-3}$ ). The improvement in SCEs ceases once the device achieves the maximum lateral extension of the depletion region. This paper provides the physical insights into the optimal use of underlap region in nanoscale JL devices for suppressing SCEs.

Graphene provides a new opportunity for thermoelectric study based on its unique heat transfer behavior controllable by a gate voltage. In this paper, an effective thermal conductivity model of graphene for thermoelectric cooling is proposed. The model is based on a double-voltage-control mechanism. According to the law of Fourier heat conduction, an effective thermal conductivity model of the proposed thermoelectric cooling device is derived taking a tunable external voltage into account. Then, a gate voltage is used which can change graphene’s thermoelectric characteristics. To verify the correctness and effectiveness of the proposed model, a circuit simulation model using HSPICE is built based on the thermoelectric duality. The simulation results from HSPICE and the calculated results from the mathematic model show good agreements with each other. This paper provides a novel precisely controlling method for thermoelectric cooling.

Although oxide thin-film transistors (TFTs) have drawn great interests in flexible displays, a key obstacle is the requirement of high-temperature annealing to realized mobility>10 cm $^{2}/\text {V}\cdot \text {s}$ . In this paper, a fully room-temperature strategy, involving the deposition of ~10 nm In–Ga–Zn–O (IGZO) channel layer and ~4 nm Al2O3 passivation layer, is introduced. The as-prepared flexible TFT on polymide substrate exhibits a saturation mobility of 15.3 cm $^{2}/\text {V}\cdot \text {s}$ , $V_{{\text {th}}}$ of 3.08 V, and on/off current ratio of $2.3\times 10^{{\text {7}}}$ . Thickness-dependent analysis indicates that the interface between Al2O3 and IGZO is composed of negative O-rich layer, which impel the energy band bending inside the IGZO layers and release of electrons from traps. This paper opens up a route to achieve fully room-temperature fabrication of high-performance flexible TFT.

With the development of novel device applications, e.g., in the field of Internet of Things or point-of-care personalized diagnostic systems, came an increased demand for MESFETs for fast and low-power consumption integrated circuits and active-matrix displays. In this paper, we present fabrication and characterization of transparent Ru–Si–O/In–Ga–Zn–O MESFETs on flexible substrates. The use of transparent conducting oxide, namely, Ru–Si–O, as Schottky gate electrode, allows for processing the devices at room temperature, enabling the utilization of such low-temperature substrates as polyethylene terephthalate foil and paper. It was shown that tuning the device geometry allows realization of transistors providing on-current up to 2 mA, while the highest on-to-off current ratio equals $2\times 10^{\mathrm { {5}}}$ , with off-current below 1 nA, carrier mobility in the channel exceeds 9 cm $^{\mathrm { {2}}}\cdot \text{V}^{\mathrm { {-1}}}\cdot \text{s}^{\mathrm { {-1}}}$ , and subthreshold swing is below 250 mV $\cdot $ decade $^{\mathrm { {-1}}}$ .

The p-n junction is the fundamental building block for electronics and photonics applications. In a conventional p-n junction, the performance parameters cannot be tuned due to the fixed doping level after ion implantation. In this paper, reconfigurable p-n or n-p junctions were built based on the ambipolar black phosphorus (BP) and other 2-D materials, namely, graphene and hexagonal boron nitride (h-BN). High-quality graphene/h-BN/BP/h-BN sandwich device was created by the dry transfer method in an inert environment. Graphene serves as the local back gate, which can tune BP partially into either n-type or p-type material. The rest of the BP channel can be controlled by the back gate. The BP encapsulated device can enable the high performance of the ideality factor down to 1.08 (p-n junction) and 1.18 (n-p junction). The device developed in this paper has a more balanced ideality factor than previously reported reconfigurable WSe2 and BP devices. By tuning the back gate and graphene gate, the BP device can be tuned into four operational quadrants, namely, n-n, n-p, p-n, and p-p junctions. Moreover, the hole mobility of BP is up to 404 cm2/ $\text {V}\cdot \text {s}$ at room temperature. Our work shows that the BP heterostructure is very promising for high-speed reconfigurable logic functions and circuits.

This paper demonstrates the influence of nonuniform doping on the electrostatics of symmetric double-gate junctionless transistor using empirical modeling scheme. To present the clear insight into the device electrostatics of nonuniform doped channel, the peak of the doping concentration has been varied from Si/SiO2 interface of front gate to the back gate. The parameters explored in this paper are surface potential, electric field, drain current, threshold voltage, subthreshold slope, and drain-induced barrier lowering for different straggle factors and channel lengths. By properly optimizing the straggle value and peak of the doping concentration, device performance can be tuned accordingly.

With lots of interest in negative capacitance field-effect transistors for ultralow-power complementary metal–oxide–semiconductor technology, negative capacitance thin-film transistors (NCTFTs) have also received much attention. Although previous studies on NCTFTs were done, the NC effect in organic-based TFTs was not studied yet. In this paper, P(VDF-TrFE) ferroelectric-gated P3HT semiconductor channel TFTs are experimentally demonstrated with solution-based fabrication process. Especially, this paper shed light on the NC effect in the organic-based TFTs. The step-up current-voltage characteristics are repeatedly and reliably observed in diverse TFTs, and then, with the results, transconductance ( $g_{m}$ ) amplification implemented by the negative capacitance was delved. Moreover, with the aid of ferroelectric polarization switching, super steep-switching characteristic of the organic-based TFT was experimentally confirmed. These experimental results and discussion would be helpful in understanding NC effects in TFTs.

With the emergence of a multichip Light-emitting diodes (LEDs) device based on different chip arrays, a new modeling for a multichip LED device with different array becomes urgent. This paper presents a compact thermal model (CTM) for the multichip LED device with different chip array for nonuniform thermal properties. Based on a general 3-D CTM, LED chips can be arranged in various array forms according to the multichip LED construction design. By linking the thermal matrix to junction temperature prediction, the proposed CTM provides accurate predictions of temperature distribution of the multichip LED device, compared to the practical physical model and infrared radiation measurement. The modeling technique has been successfully demonstrated and verified. Based on the proposed method, this paper presents the multichip LED device with a staggered array to optimize the LED positions so that heat concentration of the LED array can be reduced.

In contrast to the conventional planar p-i-n photodiode and a metal-semiconductor–metal photodetector, the 3-D dual-gate photosensitive thin-film transistor (TFT) architectures presented here attain excellent photoresponse characteristics. Operating the device in the subthreshold regime further boosts the photoconductive gain as a result of light-induced decrease in the threshold voltage. This paper presents design considerations along with a performance comparison between 3-D photosensitive TFTs that have $\pi $ - and FIN-shaped channels and conventional TFT with a planar channel. Our paper shows that the $\pi $ -shaped structure tends to have a higher sensitivity while the FIN-shaped counterpart is more responsive with wider dynamic range. For both structures, a measured photoconductive gain of $10^{\textsf {4}} \sim 10^{\textsf {6}}$ % is obtained with spectral responsivity ranging from near UV to near IR, and the photoresponse time in the range of tens of milliseconds. The 3-D dual-gate photosensitive TFT architecture appears to be very promising for large-area, low-level UV, visible, and IR detection applications.

In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III–V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor charges by considering the wave function penetration into the gate insulator, effective mass discontinuity at the semiconductor–oxide interface, 2-D confinement in the NW, and Fermi–Dirac statistics. The semiconductor charge expression proposed in this paper is completely explicit in terms of applied gate voltage, therefore, making it highly suitable for large circuit simulations. The model is also compared with the results from self-consistent Schrodinger–Poisson solver for different NW sizes and materials and found to be accurate over a wide range of gate voltages.

This paper presents using ultrasonic spray pyrolysis deposition method to grow MgO nanorod arrays on the top surface and the sidewall of the GaN-based ultraviolet light-emitting diodes. It is found that when the thickness of the MgO film is over 60 nm, the self-assembled MgO nanorod arrays are obtained. Transmission electron microscopy, scanning electron microscopy, X-ray diffraction, X-ray photoelectron spectroscopy, refractive index, extinction coefficient, and photoluminescence spectrum are used to analyze the structural, chemical, and optical characteristics of the MgO nanorod arrays. The LED chip with the MgO nanorod arrays shows slightly degraded electrical characteristics for it requires a higher forward voltage to provide 0.35-A forward current and higher series resistance. However, the LED chip with the MgO nanorod arrays has great improvement in electroluminescence and efficiency. Compared to the LED chip with a standard SiO2 passivation layer, the LED chip with the MgO nanorod arrays shows improvement of 14.1% in light output power (LOP), 12% in external quantum efficiency and wall plug efficiency. The uniformity of the LED performance like forward voltage, LOP, and wall-plug efficiency is investigated in this paper.

The physical mechanisms involved in the trapping and de-trapping processes associated with surface donor traps in gallium nitride (GaN) transistors are discussed in this paper. The paper challenges the conventional transient techniques adopted for extrapolating the trap energy level via experiments and TCAD simulations. Transient TCAD simulations were employed to reproduce the time-dependent electrical behavior of a metal-on-insulator field-effect transistor and explain the influence of the electric field and energy barrier on the transient time associated with the trapping and de-trapping mechanisms of surface traps. The comparison between three test structures and the relative variation of the trapping and de-trapping times with the bias and trap parameters leads to the suggestion of a proposed test structure and bias configuration to accurately extrapolate the energy level of surface traps in GaN transistors.

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip.

As the transparent contact in radial p-n junction core-shell nanowire array solar cells can be either planar or conformal, the characteristics of these two types of device structure would be very different since conformal contact gives rise to severe band bending. Although radial p-n junction GaAs core-shell nanowire array solar cell with conformal transparent contact has been briefly inferred to have an inferior performance compared to the same nanowire array solar cell with planar transparent contact, the characteristics of these two types of radial p-n junction core-shell nanowire array solar cells are not known. Furthermore, it is unknown how the performance of these two types of solar cell compares with each other when the nanowire design parameters are optimized according to device physics of these two types of solar cell. In this paper, it is shown that radial p-n junction GaAs core-shell nanowire array solar cells with planar transparent contact are prone to carrier avalanche breakdown, and hence have a limited range of doping density. On the other hand, carrier diffusion in radial p-n junction GaAs core-shell nanowire array solar cells with conformal transparent contact is poor and hence requires a high doping to the core in order to increase the output voltage. All in all, this paper reveals that either type of transparent contact structure yields essentially the same energy conversion efficiency as long as the radial p-n junction GaAs core-shell nanowires are designed to suit the device physics of the type of transparent contact.

Wafer-scale, CMOS compatible graphene transfer has been established for device fabrication and can be integrated into a conventional CMOS process flow back end of the line. In Part I of this paper, statistical analysis of graphene FET (GFET) devices fabricated on wafer scale is presented. Device yield is approximately 75% (for 4500 devices) measured in terms of the quality of the top gate, oxide layer, and graphene channel. Statistical evaluation of the device yield reveals that device failure occurs primarily during the graphene transfer step. In Part II of this paper, device statistics are further examined to reveal the primary mechanism behind device failure. The analysis from Part II suggests that significant improvements to device yield, variability, and performance can be achieved through mitigation of compressive strain introduced in the graphene layer during the graphene transfer process. The combined analyses from Parts I and II present an overview of mechanisms influencing GFET behavior as well as device yield. These mechanisms include residues on the graphene surface, tears, cracks, contact resistance at the graphene/metal interface, gate leakage as well as the effects of postprocessing.