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Oxide-based thin-film transistors (TFTs) with a lateral in-plane electrode are self-assembled on paper substrates, and the electrical modulation effect of the in-plane electrode is investigated. A \SiO2-based solid-electrolyte film with high specific capacitance is used as the gate dielectric, and the operation voltage is reduced to less than 2.0 V. The threshold voltage (Vth) of such paper TFTs is tuned from -0.98 to 0.94 V by different voltage biases on the in-plane electrode. The threshold voltage shift (\Delta Vth) can be described by \Delta Vth = -(CG2/CG1)VG2, where CG2 and CG1 are the in-plane electrode and bottom-gate specific capacitance values. High electrical performance with a current on/off ratio of \6 \times \10^5 \sim \10^6, a subthreshold swing of 0.14 \sim 0.19 V/dec, and a mobility of \8.64 \sim \9.45\ \cm^2/\V\cdot \s is obtained at different in-plane electrode voltage biases. Such low-voltage paper TFTs are promising for low-cost and portable electronics. [ABSTRACT FROM PUBLISHER]

This paper provides an industry perspective on the present state of compact models for MOS transistors. It highlights the complexity of layout-dependent effects in modern transistors, reviews some common misunderstandings of MOS transistor capacitances, and introduces a new, structurally symmetric, “gate-as-input” equivalent network for these capacitances. Areas of focus for the future model developments are also proposed. [ABSTRACT FROM AUTHOR]

Microporous SiO2 can provide large electric-doublelayer (EDL) capacitance and negligible leakage current, owing to lack of electron carrier and limited mobility of mobile ions. The impedance spectroscopy (ionic-conductivity--frequency and capacitance--voltage characteristics) and Fourier-transformed infrared spectroscopy of microporous SiO2 are characterized, which demonstrated that such dielectric is actually a solid-electrolyte dielectric. InGaZnO4 thin-film transistors (TFTs) on paper substrates gated by microporous-SiO2 solid electrolyte are fabricated at roomtemperature.The largeEDL-specific capacitance (1.36 µF/ cm²) results in the paper TFTs operate at a battery-drivable low voltage of 1.0 V. Both depletion-mode (Vth = .0.45 V) and enhancement-mode (Vth = 0.25 V) operations are realized by rationally controlling the oxygen concentration in argon ambient during InGaZnO4 channel deposition. Electrical characteristics with an equivalent field-effect mobility of ~21 cm²/V ⋅ s, a current ON/OFF ratio of greater than 105, and a subthreshold swing of ~80 mV/dec are demonstrated at low frequencies, which are promising for portable paper electronics. [ABSTRACT FROM AUTHOR]

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

Thin-film transistors were fabricated using 45-nm thick ZnO deposited by pulsed laser deposition and 15-nm thick Al2O3 gate insulator deposited by atomic layer deposition. A 1-D model with a constant density of interface states above and below the conduction band edge is used to explain the current-voltage characteristic. This model does not create distortion of transconductance versus gate voltage at low gate voltage that can be created by exponential tail or Gaussian distributions of interface states. The “subthreshold” regime is at the top ZnO surface away from the bottom gate, but subthreshold swing is controlled by interface states at the ZnO/Al2O3 bottom interface. The observed increase in mobility with gate voltage is delayed by filling of the interface states above the conduction band edge. Interface state filling and a rapid increase in mobility with increased gate voltage produce an apparent large threshold voltage as extrapolated from a linear fit to current measured at large gate voltage. The difference between threshold voltage and turn-off voltage is an important figure of merit (FOM) that should be kept as small as possible. In this paper, FOM is 2.5 and 1.8 V for 0.1 and 6 V drain voltage, respectively. [ABSTRACT FROM PUBLISHER]

The physical mechanisms involved in the trapping and de-trapping processes associated with surface donor traps in gallium nitride (GaN) transistors are discussed in this paper. The paper challenges the conventional transient techniques adopted for extrapolating the trap energy level via experiments and TCAD simulations. Transient TCAD simulations were employed to reproduce the time-dependent electrical behavior of a metal-on-insulator field-effect transistor and explain the influence of the electric field and energy barrier on the transient time associated with the trapping and de-trapping mechanisms of surface traps. The comparison between three test structures and the relative variation of the trapping and de-trapping times with the bias and trap parameters leads to the suggestion of a proposed test structure and bias configuration to accurately extrapolate the energy level of surface traps in GaN transistors. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, the record high-performance top-gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top-gate as well as back-gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step-by-step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top-gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness. [ABSTRACT FROM AUTHOR]

Because of charge trapping in GaN HEMTs, dc characteristics of these devices are not representative of high-frequency operation. The advanced spice model GaN model presented in Part I of this paper is combined with a Shockley–Reed–Hall-based trap model, yielding a comprehensive FET model for GaN HEMTs which can accurately model GaN devices exhibiting trapping-related dispersion effects. Measurement results of the dc and pulsed output and transfer characteristics of a commercially available GaN HEMT are presented, trapping in the device is modeled, and excellent fit to the measured data is shown. This paper presents an accurate model of trapping which is validated for eight different quiescent bias points of pulse measurements, with quiescent drain voltage ranging from 5 to 20 V and quiescent gate voltage ranging from −2.8 to −3.8 V, and a large range of gate and drain voltages to which the device was pulsed in the pulse measurements and at which the device was measured in the dc measurements, with gate voltage ranging from −4 to 0.4 V and drain voltage ranging from 0 to 40 V. This paper also presents high-frequency (10 GHz) large-signal RF validation of the model for optimal complex load condition. [ABSTRACT FROM AUTHOR]

In this paper, we present a detailed investigation of the impact of fin width (${w}_{\text {fin}}$) on tri-gate AlGaN/GaN metal–oxide–semiconductor high electron mobility transistors (MOSHEMTs). As ${w}_{\text {fin}}$ is reduced, the threshold voltage (${V}_{\text {TH}}$) increases, which is due to the enhanced gate control (especially for ${w}_{\text {fin}} < {200}$ nm) thanks to the 3-D geometry of the tri-gate, and the reduced carrier concentration (${N}_{\text {s}}$) caused by a more pronounced strain relaxation and sidewall depletion, as explored using Hall and capacitance–voltage (${C}$ – ${V}$) measurements. Normally- OFF operation was achieved for ${w}_{\text {fin}}$ close to the sidewall depletion width (${w}_{\text {dep}}$) of 19.5 nm, since the fin is depleted from its two sidewalls. The impact of ${w}_{\text {fin}}$ on ON-resistance (${R} _{{{ {6{8} {\text {ON}}}}}}$) and current capability (${I} _{\text {D},\text {max}}$) was also investigated, along with the influence of the effective source injection, the trench conduction and the filling factor (FF) on these key characteristics. The degradation caused by the tri-gate fin etching could be fully recovered by increasing the FF. Finally, we show that the tri-gate can reduce gate capacitance (${C}_{\text {G}}$) and charge (${Q}_{\text {G}}$) in normally- ON MOSHEMTs, depending on the design of the tri-gate and the gate voltage (${V}_{\text {G}}$), leading to a smaller ${R}_{{{ {6{8} {\text {ON}}}}}} \cdot {Q}_{\text {G}}$ product that is beneficial for high-frequency switching applications. The results in this paper offer insights into important phenomena in tri-gate GaN devices and are fundamental for the further advance of this technology. [ABSTRACT FROM AUTHOR]

A novel plasma Charge Accumulative Model (pCAM) by calculating time-integrated Fowler–Nordheim (FN) tunneling charges and field of the gate dielectric in plasma processes is proposed in this paper. Our prior studies have developed and presented a quantitative FinFET plasma recording device by an effective fin-shaped field effect transistor (FinFET) contact-to-metal coupling structure to record and quantify plasma ion charges created in FinFET backend processes. In this paper, a precise analytical model is proposed to model the magnitude of plasma ion charges, time-integrated stressing field, and the criteria of the plasma process for optimum FinFET process technology. The new pCAM is highly matching with the measurement result of 16- and 7-nm FinFET wafers. The model can be adapted to practically estimate the plasma damage with different charge types, process parameters, and ion distribution; it can optimize the FinFET process and further understand the plasma damage mechanism in charging processes of 7-nm FinFET and beyond. [ABSTRACT FROM AUTHOR]

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

This paper clarifies the correct transmission mechanism, misattributed in the previous research, of a hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) device. Complete drain current–gate voltage (${I}_{\text {D}}$ – ${V}_{\text {G}}$) transfer characteristics including the forward and backward gate sweeps (gate voltage carried out in the OFF-state $\to $ on-state and the ON-state $\to $ OFF-state) are performed, and the physics models of an energy-band schematic are clearly explained. This paper reveals that the ${I}_{\text {D}}$ – ${V}_{\text {G}}$ curve stretch-out behavior of the subthreshold region is due to the leakage of the Poole–Frenkel region. At the Poole–Frenkel regions, electrons transfer to the drain terminal, and holes remain in the valance band of the a-Si:H bulk. The remaining holes represent the positive voltage and cause the electron barrier height lowering. This causes an increase in subthreshold current of the subthreshold region. Finally, three experiments are performed to prove the correctness of these models, and the a-Si TFTs device improvement methods will be proposed to enhance the stability and performance of product of the a-Si TFTs. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel reconfigurable ferroelectric FET (R-FEFET), which can reconfigure its operation between volatile and nonvolatile modes during run-time by dynamically modulating its hysteresis. The R-FEFET comprises of two gates with ferroelectric (FE) in both the gate stacks. One of these terminals serves as a regular gate, while the other is used as a control to introduce reconfigurability. Employing Landau–Khalatnikov equation-based FEFET model, we extensively analyze the device characteristics in both FinFET and planar technologies. We show that by changing the control voltage between 0 and 1 V, the hysteresis width (HW) can be modulated between 1.1 and 0.3 V. In addition, we show the device characteristics and advantages that R-FEFETs possess to overcome the drawbacks encountered with gate leakage in standard FEFETs. The hold margins in the nonvolatile mode of R-FEFETs increase by ~ $10\times $ with respect to standard FEFETs, and the drive current strengths in the volatile mode show 13% improvements when compared to standard FETs. Using the proposed R-FEFETs, we examine a low-power nonvolatile memory design in Part II of this paper. [ABSTRACT FROM AUTHOR]

In this response, we show that the paper by Kim et al. by our group has a different research purpose and uses different modeling processes, which was not described in the previous work by Ortiz-Conde et al. The comments issued by Ortiz-Conde et al., who claim that our paper corresponds to a particular case of their previous work, are in our opinion overgeneralized. Differences compared to Ortiz-Conde’s previous work are discussed in detail. We also explain how the problem on threshold voltage pointed out by Ortiz-Conde et al. can be solved through a semiempirical method from measured data. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

In this paper, a p-channel vertical 4H-silicon carbide (SiC) MOSFET (SiC p-MOSFET) has been fabricated successfully for the first time as a potential candidate for the complementary inverter application. The static characteristics and the robustness, including short circuit and avalanche capabilities of the p-MOSFET, are experimentally tested. Moreover, the comparison between the p-MOSFET and similar rating n-MOSFET is carried out. The short-circuit capability is 15% higher than that of the n-channel MOSFET. Furthermore, this paper also provides the physical insights into the failure mechanism during the short-circuit transient of the p- and n-MOSFET. Meanwhile, an electro-thermal analytical model is proposed to explain the thermal distribution during this transient. Last, the avalanche withstand time of the fabricated SiC p-MOSFET is experimentally demonstrated to be 27% higher than that of the n-channel one. It is concluded that the SiC p-MOSFET could be a competitive power switch applicable for high-frequency complementary inverters. [ABSTRACT FROM PUBLISHER]

Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed while keeping only performance targets for a given application in mind. In this paper, for the first time, performance and reliability codesign approach using 3-D TCAD has been presented for various superjunction (SJ) type DeMOS devices. In this context, how to effectively utilize the SJ concept in a DeMOS device for System on Chip applications, which often has stringent switching and RF performance targets, is explored in detail in this paper. Moreover, design and reliability tradeoffs for switching and RF applications are discussed, while considering two unique sets, one with fixed breakdown voltage and other with fixed ON-resistance. Finally, hot carrier generation, safe operating area concerns, and electrostatic discharge physics are explored and compared using 3-D TCAD simulations. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of quantum capacitance on the intrinsic inversion-capacitance ( C\mathrm{ inv}) characteristics of high-mobility multigate III–V-on-insulator nMOSFETs through a numerical simulation corroborated by the theoretical calculation. Nonmonotonic C\mathrm{ inv} characteristics stemming from the energy dependence of 1-D density-of-states and significant C\mathrm{ inv} degradation due to quantum capacitance have been found in trigate In0.53Ga0.47As and InAs devices based on the ITRS 2018–2024 technology nodes. This paper indicates that, to compensate the excess inversion-charge ( Q\mathrm{ inv} ) loss due to quantum capacitance, the needed mobility gain of the trigate InGaAs and InAs devices (against the Si counterparts) should be at least $\sim 3\times $ and $\sim 4\times $ , respectively. This paper also suggests that the quantum-capacitance-induced Q\mathrm{ inv} loss can be mitigated by raising the fin aspect ratio of the III–V multigate device. [ABSTRACT FROM AUTHOR]

The instability of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under ultraviolet (UV) light was thoroughly investigated in this paper. Unlike in a darkened state, an off-state leakage current can be found in the dual-sweep I–V transfer curve of a-IGZO TFTs under UV light illumination. Furthermore, despite the same UV light condition, the forward sweep and reverse sweep show different I–V curves, representing two different physical mechanisms. First, the subthreshold swing degradation and threshold voltage shift to the negative direction in the forward sweep are due to the total channel barrier lowering and can be confirmed by changing the light exposure region. Second, in the reverse sweep, the suggested back-channel leakage current can be controlled by dual-gate TFTs. UV light exposure of the metal–insulator–semiconductor–metal structure verifies that the off-state leakage current passes through the back channel in a reverse sweep. Finally, the physical mechanism links between forward and reverse sweeps have comprehensive interpretation in this paper. [ABSTRACT FROM AUTHOR]

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness (${T}_{\textsf {core}}$), shell doping (${N}_{\textsf {d}}$), gate length (${L}_{\textsf {g}}$), and gate (${V}_{\textsf {gs}}$) and drain (${V}_{\textsf {ds}}$) biases in subthreshold regime. The threshold voltage (${V}_{\textsf {th}}$), drain-induced barrier lowering and subthreshold swing (${S}$), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications. [ABSTRACT FROM AUTHOR]

In this paper, the threshold voltage characteristics of silicon nanowire metal–oxide–semiconductor field-effect transistor (MOSFET) with a double-layer gate structure are presented. This type of device is considered to be the most promising application of nanodevice in ultralarge-scale integration, due to several advantages such as similar operation principle as the junctionless nanowire transistor, the screening effect of the upper gate (UG) to shield the lower gate MOSFETs from external electromagnetic disturbance, the tradeoff between the short channel and the thick-gate oxide layer, and the compatible fabrication process with the conventional MOS technology. In this paper, the relations of threshold voltage versus the gate length, the UG bias, the substrate bias, the drain bias, and the temperature are measured and analyzed. Moreover, the penetration effect of the UG electric field is proposed to interpret the short-channel characteristics of the device, and a piecewise curve model is presented to reveal the underlying physics of the relation of the threshold voltage versus the drain bias. The double-layer gate structure technology enables the design of many devices, such as small-signal analog circuit units, single-electron devices, and quantum bit cells. [ABSTRACT FROM AUTHOR]

The p-n junction is the fundamental building block for electronics and photonics applications. In a conventional p-n junction, the performance parameters cannot be tuned due to the fixed doping level after ion implantation. In this paper, reconfigurable p-n or n-p junctions were built based on the ambipolar black phosphorus (BP) and other 2-D materials, namely, graphene and hexagonal boron nitride (h-BN). High-quality graphene/h-BN/BP/h-BN sandwich device was created by the dry transfer method in an inert environment. Graphene serves as the local back gate, which can tune BP partially into either n-type or p-type material. The rest of the BP channel can be controlled by the back gate. The BP encapsulated device can enable the high performance of the ideality factor down to 1.08 (p-n junction) and 1.18 (n-p junction). The device developed in this paper has a more balanced ideality factor than previously reported reconfigurable WSe2 and BP devices. By tuning the back gate and graphene gate, the BP device can be tuned into four operational quadrants, namely, n-n, n-p, p-n, and p-p junctions. Moreover, the hole mobility of BP is up to 404 cm2/ $\text {V}\cdot \text {s}$ at room temperature. Our work shows that the BP heterostructure is very promising for high-speed reconfigurable logic functions and circuits. [ABSTRACT FROM AUTHOR]

This paper demonstrates a novel nanofabrication technology for producing high-density gated molybdenum (Mo) field-emitter array (FEA) based on modified nanosphere lithography (NSL). The arc-shaped side wall of gate apertures introduced by the conventional NSL process put obstacles in the formation of sharp cone-type emitters. In this paper, a two-method solution was employed to facilitate the realization of gate apertures with sharper cutting side wall which are beneficial for the formation of sharper gated Mo emitters. One method was softening nanosphere to enlarge the contact area between nanosphere and substrate. The other was optimizing gate film deposition conditions to dramatically reduce the diffraction effects. Due to the improvements in the geometrical shape of gated Mo emitters, a low-voltage working high-density gated Mo FEA was demonstrated in this paper. This is the first observation of remarkable electron emission from high-density gated Mo FEA fabricated using such as low-cost, high-throughput, and high-efficiency technique which is expected to substantially overcome the challenges in the traditional fabrication process and promotes the low-cost and large-area application of high-density gated field-emitter devices. In addition, the novel nanofabricating method is expected to offer a simple and scalable route which allows fabrication of many gated field-emission devices. [ABSTRACT FROM AUTHOR]

This paper demonstrates a high-performance black phosphorus nanoribbons field-effect transistor (BPNR-FET) and systematically investigates methods for enhancing its anisotropic carrier transport. The BPNR-FET shows a strong dependence on crystal orientation in which the best mobility performance is achieved in armchair-oriented nanoribbons. A downscaling of nanoribbon width is shown to improve the short-channel effect owing to a better electrostatic gate control. Furthermore, hydrogenation is employed to effectively passivate the dangling bonds and heal the nanoribbon edge defects, leading to nearly hysteresis-free transfer properties. By virtue of bandgap and contact-metal workfunction engineering, n-type BPNR-FET is successfully demonstrated, which enables complementary inverter circuits to be simultaneously realized. This paper unravels the superior performance underscores a conceptually new BPNR-FET, paving the way toward the development of non-planar devices and integrated circuits based on 2-D materials platform. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

Most thin-film transistor (TFT) gate drivers integrated on the display panel use the carry signals between the stages. In our previous works, we found that these carry-type gate drivers are subject to the reliability problem in a flexible display, since the errors of the stressed stages are accumulated through the carry signals. This problem possibly leads to the failure of image refresh of the display device. Therefore, the carry-free gate driver can resolve the error accumulation problem since it does not use the carry signals and instead, each unit stage operates independently. In this paper, we propose an advanced carry-free gate driver circuit to remove the drawbacks of the previous version, while keeping the advantages. More importantly, this paper is the first report to experimentally show that the error accumulation phenomenon of the carry-type gate driver and the problem is removed in the carry-free gate driver. The proposed carry-free gate driver and the carry-type gate driver are fabricated with amorphous indium-gallium-zinc-oxide TFTs on a flexible substrate for comparison purpose. The proposed gate driver shows a very high reliability since no voltage fluctuation occurs at the outputs after 10 000 cycles bending test with 2-mm bending radius. [ABSTRACT FROM AUTHOR]

A systematic analytical investigation of the charge distribution and gate control of the normally-off GaN double-channel MOS-HEMT (DC-MOS-HEMT) is presented in this paper. Compared to conventional GaN MOS-HEMT, the DC-MOS-HEMT features a thin AlN insertion layer (AlN-ISL) below the original two dimensional electron gas (2DEG) channel, thus forming a second channel at the interface between AlN-ISL and the underlying GaN. This paper reveals the impact of the AlN-ISL on the 2DEG distribution and the gate control of the channels. The sensitivity of ${V}_{\text {th}}$ against the recess depth is also analytically studied and is found to be nearly independent of the recess depth as long as the recess is terminated in the upper channel layer. The analytical results are well supported by numerical device simulations, and the physical mechanisms behind these findings are explained along with the analytical investigations. [ABSTRACT FROM AUTHOR]

This paper reports on the design optimization of double gate (DG) tunnel FET (TFET) for dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral spacing ( L_ \text gap) between the gates, and an underlap region ( L\text {un}) between drain and back gate reduces state “0” degradation, which along with optimal biases, results in an improved Retention Time (RT) at 85 °C. The systematic design optimization increases RT from ~80 to ~300 ms with the use of L\text {gap} at 85 °C, which can be further improved to ~600 ms with the introduction of L\text {un} . The careful investigation shows the back gate scaled down to 25 nm with a front gate region of 100 nm, and operation even at elevated temperatures (125 °C). The insights into DG TFET DRAM operation in terms of individual as well as total lengths highlights the RT enhancement by a factor of 3 with constant total length (200 nm) and an improved scalability with total length scaled down to 160 nm. This paper provides new opportunities to realize TFET-based DRAM with improved RT, scalability, and high temperature operation. [ABSTRACT FROM PUBLISHER]

Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs). [ABSTRACT FROM AUTHOR]

Tunnel FETs (TFETs) have been identified as the most promising steep slope devices for ultralow power logic circuits. In this paper, we demonstrate in-plane InAs/Si TFETs monolithically integrated on Si, using our recently developed template-assisted selective epitaxy approach. These devices represent some of the most scaled TFETs with dimensions of less than 30 nm, combined with excellent aggregate performance with average subthreshold swing (SS), of around 70 mV/decade combined with I\mathrm{\scriptscriptstyle ON} of a few \mu \textA / \mu \textm for |V\mathrm {\mathbf {DS}}| = |V\mathrm {\mathbf {GS}}| = 0.5 V. Here, we will discuss the device fabrication as well as the experimental electrical data. Extensive low temperature characterization and activation energy analysis is used to gain insights into the factors limiting device performance. Combined with the simulation study presented in part 2 of this paper, this will elucidate how traps are ultimately limiting the SS. [ABSTRACT FROM AUTHOR]

Increased drain-induced barrier lowering caused by drain electric flux (or field) passing through the buried-oxide (BOX) layer in silicon-on-insulator (SoI) MOSFETs has been reported as an inherent disadvantage of SoI technology. Part I of this paper discussed derivation of the relationships between coordinates in MOSFETs and potential/stream function in preparation for the modeling of electric flux using conformal mapping in subthreshold regions of ground plane SoI MOSFETs and the validity of the approach was checked via device simulation. Here, in Part II of this paper, we discussed the model’s derivation based on these relationships. The dependences of the flux amount on BOX thickness, BOX permittivity, SoI thickness, and gate length estimated using the model were also discussed in comparison with those estimated via device simulation. [ABSTRACT FROM PUBLISHER]

The effects of gamma rays on two kinds of GaN high-electron-mobility transistors (HEMTs) have been investigated in this paper. We have identified a gate degradation using a combination of optical and electrical measurements. We have demonstrated that the channel current under the degradation position is outside of the gate’s control. This degradation prevents the gate from fully pinching off the channel, creating a current concentration region when applying a reverse gate voltage. An integrated analysis, including ${I}$ – ${V}$ characterization, the emission microscope (EMMI) technique, and temperature-dependent measurements, was applied to study its mechanism. It is attributed to an irradiation-induced degradation in the Schottky contact. [ABSTRACT FROM AUTHOR]

Detailed physics of the third quadrant electrical characteristics of 1.2-kV rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs, based on experimentally measured data and TCAD numerical simulations, are described in this paper for the first time. The power MOSFETs with various channel lengths (0.3, 0.5, 0.8, 1.1 $\mu \text{m}$) used in this paper were fabricated in a 6-in commercial foundry. Numerical simulations verified that there are two current paths in the third quadrant: 1) through the base region and 2) through the p-n body diode. This paper demonstrates that the Acc MOSFETs have a smaller third quadrant knee voltage (${V}_{{\text {knee}}})$ of −1.2 V compared with −1.9 V for the Inv MOSFETs (at ${V}_{g} = {0}$ V and room temperature). Numerical simulations show that this difference is due to a smaller potential barrier for electron transport from the drain to the source in the base region for accumulation channel devices than inversion channel devices. Acc devices are shown to have a lower voltage drop in the third quadrant. [ABSTRACT FROM AUTHOR]

In this paper, we report the characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz. The self-heating effect (SHE) in NWFETs is investigated experimentally using the small-signal output conductance (${g}_{{\text {ds}}}$) technique. The frequency-dependent complex thermal impedance, ${Z}_{{\text {th}}}({f})$ , is extracted by fitting an ${n}$ th-order thermal network with the experimental data. We show that the temperature rise $\Delta {T}$ (=85 °C) due to SHE is significant in short-channel silicon on insulator (SOI) NWFETs. Finally, we have evaluated the RF figure of merit (FOM) for these NWFETs as ${f}_{T}$ (=70 GHz) and ${f}_{\text {max}}$ (=80 GHz). We also report the RF performance metric sensitivity on temperature, $\partial {f}_{\text {max}}/\partial {T}_{{\text {amb}}}$ ($\approx -0.104$ GHz/K). The reported BSIM-CMG compact model shows a good correlation with the measurement data. [ABSTRACT FROM AUTHOR]

In this paper, AlGaN/GaN high-electron mobility transistors (HEMTs) with different fin configurations are fabricated and analyzed. Through S-parameter measurements and modeling of the designed devices, a detailed RF investigation on small-signal model parameters is performed under different biasing conditions. Good agreements between measured and simulated scattering parameters up to 40 GHz illustrate the validity and accuracy of the model. The influence of different fin structures on model parameters and linearity improvement is examined, and this can help to improve the frequency characteristics of fin structure by optimizing the fin length, fin width, and trench width. The significant linearity of Fin-HEMTs is confirmed by the analysis of the model parameters, which is the first time to study the small-signal characteristic of AlGaN/GaN Fin-HEMTs in detail. [ABSTRACT FROM AUTHOR]

This paper reports the very first systematic study on the physics of avalanche instability and safe operating area (SOA) reliability in AlGaN/GaN high-electron-mobility transistor (HEMT) using submicroseconds pulse characterization, poststress degradation analysis, well-calibrated TCAD simulations, and failure analysis by scanning electron microscopy (SEM) and transmission electron microscopy (TEM). Impacts of electrical and thermal effects on SOA boundary and avalanche instability are investigated. Trap-induced cumulative nature of degradation is studied in detail. The root cause for avalanche instability in AlGaN/GaN HEMTs is investigated. Postfailure SEM, energy dispersive X-ray (EDX), and TEM analysis reveal distinct failure modes in the presence and absence of carrier trapping. [ABSTRACT FROM AUTHOR]

A novel fast-switching lateral-insulated gate bipolar transistor (LIGBT) with double gates and integrated Schottky barrier diode (SBD) is proposed and studied in this paper by TCAD simulation. In order to reduce the turn-off time and maintain a low forward voltage drop, the proposed structure introduces an integrated SBD structure at the anode and an additional trench gate at the cathode. First, the integrated SBD provides an extra electron extraction path and the additional trench gate enhances the injection of the N+-cathode. Furthermore, the insulated oxide pillar between the N-buffer and integrated SBD further reduces the snapback voltage. Finally, the simulation results show that the turn-off time of the conventional LIGBT is 52.4% larger than that of trench/planar gate SBD (TP-SBD) LIGBT under the same forward voltage of 1.49 V. Moreover, the latch current density of TP-SBD LIGBT is increased by nearly 200% compared to that of the conventional LIGBT, while almost the same latch voltage is obtained, so the proposed TP-SBD LIGBT can improve the latch immunity. [ABSTRACT FROM AUTHOR]

This paper investigates the fin-width ($\text{W}_{\textsf {Fin}}$) sensitivity of threshold voltage ($\text{V}_{\textsf {T}}$) for InGaAs and Si channel negative-capacitance FinFETs (NC-FinFETs) using a theoretically derived quantum subthreshold model corroborated with TCAD numerical simulation. Our study indicates that due to the action of negative capacitance, the NC-FinFET possesses smaller $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ than the FinFET counterpart. In addition, we point out and demonstrate that a device design with higher internal voltage amplification can be utilized to further reduce the $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ for NC-FinFETs. Our study may provide insights for future scaling of FinFETs. [ABSTRACT FROM AUTHOR]

Recently demonstrated CMOS circuits based on Ge nanowires (Ge-FET) promise sustained technology scaling because higher mobility Ge guarantees target ${I}_{\text {ON}}$ at a lower ${V}_{{\textit {DD}}}$. Unfortunately, this promise is counterbalanced by the fact that Ge is a poor thermal conductor, thus, the thermal confinement of the surround-gate topology may exacerbate self-heating (SHE) and erode the intrinsic performance gain associated with the high channel mobility. In this paper, we use: 1) electrical and optical methods to, respectively, characterize channel and surface SHE of Ge-FET with various channel lengths ( ${L}_{\text {ch}}$ ), widths ( ${W}_{\text {ch}}$ ), and the number of the nanowires (NWs) (#NW); 2) interpret the results obtained by the 3-D thermal modeling, and compare theoretically the SHE in Ge-FET configured in various topologies, such as bulk FinFET, silicon-on-insulator FinFET, and gate-all-around NW-FET; and 3) embed the results in an electrothermal SPICE simulator to compare the performance of ring oscillators based on Ge-FET and Si-FET. Our results show that the existing Ge-FET (with an airgap) is thermally suboptimal, but once optimized, SHE in Ge-FET would be comparable to that of Si-FET. The results encourage sustained development of Ge-FETs. [ABSTRACT FROM AUTHOR]

In this paper, we present a surface potential-based explicit continuous model for a metal-ferroelectric-insulator-semiconductor (MFIS) type gate-all-around negative capacitance transistor (GAA-NCFET). Unlike previously reported models, an explicit formulation to calculate the electrical characteristics of GAA-NCFET is proposed. Our model includes the radial dependence of the electric field in the ferroelectric, ignored in the previous works and accurately captures ferroelectric material parameter variations in the nonhysteretic regime. In contrast to bulk NCFETs, GAA-NCFET characteristics show different bias dependence due to the absence of bulk charge. We also present analytical expressions for the terminal charges which are essential to obtain the trans-capacitances for transient simulations. We find that, compared with conventional MOSFETs, the gate charge saturates to a different fraction of its maximum value. Furthermore, the modeling of quantum mechanical effect and overlap capacitances in an MFIS NCFET structure is discussed. Finally, the proposed model has been implemented in Verilog-A and tested for the transient response of ring oscillator in a commercial circuit simulator. [ABSTRACT FROM AUTHOR]

There have been a lot of ambiguities related to physics of quasi-saturation (QS) in laterally diffused MOS (LDMOS) devices in the published literature. For example, models that explain QS in input characteristics do not explain the same in output characteristics and vice versa. In addition to this, none of the earlier models explain early onset of QS at higher temperatures nor the models were validated using counter arguments. Attributed to this, a need for unified theory explaining physics of QS is justified in this paper. Furthermore, this paper for the first time, while addressing missing links between the observations reported in the past, develops a unified theory to explain physics of QS behavior. The theory presented here is independent of device architecture and covers all voltage-current–temperature trends. While considering velocity saturation and space charge modulation, we have discovered key role of high field mobility degradation of majority carriers and electric field screening, which is found to be the root cause of QS in LDMOS devices. The theory presented is further validated with numerous counter arguments. Finally, based on the new physical insight developed, we have proposed different approaches to mitigate QS effect. A detailed device design guideline to mitigate QS and its correlation with analog/RF performance, electo static discharge, hot-carrier reliability, self-heating, and safe operating area concern is presented in Part II of this paper. [ABSTRACT FROM PUBLISHER]

In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III-V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor charges by considering the wave function penetration into the gate insulator, effective mass discontinuity at the semiconductor-oxide interface, 2-D confinement in the NW, and Fermi-Dirac statistics. The semiconductor charge expression proposed in this paper is completely explicit in terms of applied gate voltage, therefore, making it highly suitable for large circuit simulations. The model is also compared with the results from self-consistent Schrödinger-Poisson solver for different NW sizes and materials and found to be accurate over a wide range of gate voltages. [ABSTRACT FROM AUTHOR]

With lots of interest in negative capacitance field-effect transistors for ultralow-power complementary metal-oxide-semiconductor technology, negative capacitance thin-film transistors (NCTFTs) have also received much attention. Although previous studies on NCTFTs were done, the NC effect in organic-based TFTs was not studied yet. In this paper, P(VDF-TrFE) ferroelectric-gated P3HT semiconductor channel TFTs are experimentally demonstrated with solution-based fabrication process. Especially, this paper shed light on the NC effect in the organic based TFTs. The step-up current-voltage characteristics are repeatedly and reliably observed in diverse TFTs, and then, with the results, transconductance (gm) amplification implemented by the negative capacitance was delved. Moreover, with the aid of ferroelectric polarization switching, super steep-switching characteristic of the organic-based TFT was experimentally confirmed. These experimental results and discussion would be helpful in understanding NC effects in TFTs. [ABSTRACT FROM AUTHOR]

In this paper, we propose a vertical transistor with n-bridge and body on gate (BOG-DRAM) for Low-power 1T-DRAM application. The vertical channel of the device can reduce the short-channel effect and improve scalability. The storage region stacked on the gate leads to the efficient utilization of storage space. The device with junctionless channel layers on three sides can improve writing time. The conventional current bridge device only has one side gatecontrol depletion region, but the proposed BOG-DRAM has triple-side gate-control depletion region which can improve programming window at shorter gate lengths. BOG-DRAM achieves programming window of 33.6 μA/μm when the storage length is 20 nm. In addition, the work function offset is exploited for low-power application. [ABSTRACT FROM AUTHOR]

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip. [ABSTRACT FROM PUBLISHER]

Wafer-scale, CMOS compatible graphene transfer has been established for device fabrication and can be integrated into a conventional CMOS process flow back end of the line. In Part I of this paper, statistical analysis of graphene FET (GFET) devices fabricated on wafer scale is presented. Device yield is approximately 75% (for 4500 devices) measured in terms of the quality of the top gate, oxide layer, and graphene channel. Statistical evaluation of the device yield reveals that device failure occurs primarily during the graphene transfer step. In Part II of this paper, device statistics are further examined to reveal the primary mechanism behind device failure. The analysis from Part II suggests that significant improvements to device yield, variability, and performance can be achieved through mitigation of compressive strain introduced in the graphene layer during the graphene transfer process. The combined analyses from Parts I and II present an overview of mechanisms influencing GFET behavior as well as device yield. These mechanisms include residues on the graphene surface, tears, cracks, contact resistance at the graphene/metal interface, gate leakage as well as the effects of postprocessing. [ABSTRACT FROM PUBLISHER]

This paper presents a compact analytical I – V model for short-channel double-gate transition metal dichalcogenide filed-effect transistors in the subthreshold region. A closed-form expression is proposed for the characteristic length in the scale length approach, which is based on physical device parameters. It is then used to find the channel potential and drain current in the subthreshold region. This model is verified with the numerical results of a nonequilibrium Green’s function (NEGF) simulator. There is good agreement between the results of the proposed model and the numerical NEGF simulations in the subthreshold region, while it captures the effects of the device’s physical parameters. [ABSTRACT FROM PUBLISHER]

In our earlier work, we presented a percolation theory-based analytical model to estimate FinFET’s VT distribution due to fin edge roughness. The earlier models in the literature were based on minimum fin width, the limitations of which were discussed in detail. In this paper, we advance the percolation theory-based model to capture the variability in all key-device parameters, viz. I \mathrm{\scriptscriptstyle ON} , I \mathrm{\scriptscriptstyle OFF} , subthreshold slope, and VT . The entire distribution of these parameters obtained by the model is presented and compared against stochastic TCAD to demonstrate excellent match. The model reduces rms error in $\mu $ of various parameters by 5%–60%, and 20%–50% in $\sigma $ with respect to the minimum fin width-based models present in the literature. [ABSTRACT FROM PUBLISHER]

Recent advances in the fabrication technology have yielded nanometer-scale InGaAs quantum-well (QW) MOSFETs with extremely low and reproducible external contact and access region resistances. This allows, for the first time, a detailed analysis of the role of ballistic transport in the operation of these devices. This paper presents a systematic analysis of external resistance, ballistic resistance, and channel mobility in InGaAs QW-MOSFETs under near-equilibrium conditions, i.e., under very low drain-source bias. This is an important regime for device characterization. Devices with a wide range of channel lengths, from 70 to 650 nm, are investigated. Our analysis includes the consideration of the impact of carrier degeneracy in the QW channel. We show that unless the ballistic behavior in the intrinsic channel is accounted for, the standard extraction technique for external resistance grossly exaggerates its value as it incorporates the so-called ballistic resistance. By separating out the ballistic resistance, the external resistance in our devices is shown to be extremely low, $74~\Omega $ - \mu \text{m} , including both source and drain sides. This is thanks to our contact-first self-aligned Mo-contact technology. Furthermore, taking the advantage of the wide range of ballisticity of the devices studied in this paper, we demonstrate a methodology to self-consistently extract scattering-dependent effective mobility, mean-free-path length, and ballistic mobility. [ABSTRACT FROM AUTHOR]

A bond-pad charging protection design for charging-free reference transistor test structures was examined. This paper concludes that truly charging-free reference transistors cannot be realized with the one conventional bond-pad charging protection design of protecting transistor gates only. This, however, can be achieved by simultaneously protecting all terminals of the reference transistors. The simulations, in this paper, reconfirm the earlier important experimental conclusion that placing protection device(s) at transistor gates may inflict severe damage to transistor gate oxides instead of protecting them. The implication of the above suggests that attention may be required in a circuit layout design stage for those transistors which gates begin to connect, at high metal layers, to highly efficient leakage paths, such as protection devices, n-type source/drain diffusion regions, and VSS bus lines, which tend to pull transistor gates to low potentials during a backend integrated-circuit manufacturing process. This paper proposes an optimum bond-pad charging protection design for the truly charging-free reference transistor test structures by considering a minimum usage in a layout space and minimum gate oxide stress in the fuse zap-off process. [ABSTRACT FROM AUTHOR]