Search

Microporous SiO2 can provide large electric-double-layer (EDL) capacitance and negligible leakage current, owing to lack of electron carrier and limited mobility of mobile ions. The impedance spectroscopy (ionic-conductivity-frequency and capacitance-voltage characteristics) and Fourier-transformed infrared spectroscopy of microporous SiO2 are characterized, which demonstrated that such dielectric is actually a solid-electrolyte dielectric. InGaZnO4 thin-film transistors (TFTs) on paper substrates gated by microporous-SiO2 solid electrolyte are fabricated at room temperature. The large EDL-specific capacitance (1.36 μF/ cm2) results in the paper TFTs operate at a battery-drivable low voltage of 1.0 V. Both depletion-mode (Vth = -0.45 V) and enhancement-mode (Vth = 0.25 V) operations are realized by rationally controlling the oxygen concentration in argon ambient during InGaZnO4 channel deposition. Electrical characteristics with an equivalent field-effect mobility of ~ 21 cm2/V·s, a current on/off ratio of greater than 105, and a subthreshold swing of ~ 80 mV/dec are demonstrated at low frequencies, which are promising for portable paper electronics.

This paper presents a parallel plate-type field emission device of potassium hydroxide-doped electrochemically reduced graphene oxide (GO) manufactured using highly oriented pyrolytic graphite through electrochemical exfoliation. The material properties of the GO were tested through Raman spectroscopy, X-ray diffraction, and X-ray photoelectron spectroscopy. The optimal electron emission characteristics of the device were as follows: turn-on field = 2.03 V/ $\mu \text{m}$ , field emission current $= \,\, 16.4~\mu \text{A}$ , and field emission enhancement factor = 8377. At an emission peak wavelength of 563.7 nm, the optimal device had a light flux of 4.21 lumens and an illumination of 140.3 lux. These properties can be utilized in various optoelectronic devices, such as nanoelectronics devices, sensors, electrochemical systems, and energy storage devices.

We present a computational study on hybrid nanomaterial-insulator-silicon solar cells where single-walled carbon nanotube or graphene forms the emitter as well as top conducting electrode on n-type crystalline silicon having a thin interfacial tunnel oxide. The effects of nanomaterial doping and tunnel oxide thickness on cell characteristics are modeled. Similar to bulk emitters, cell efficiency could be increased by chemical doping (p-type) of the nanomaterial. Unlike bulk, nanomaterial could get electrostatically doped (n-type) due to its low quantum capacitance, by the surface charge density in silicon. For chemically undoped graphene on lightly ( $10^{{16}}$ /cm $^{{3}}$ ) doped silicon, efficiency loss due to the electrostatic doping effect is $\sim 11$ %. A moderate p-type chemical doping (0.2 eV shift in Fermi level) of graphene reduces the aforementioned loss to $\sim 2$ %. The electrostatic doping effect in carbon nanotube-based cells is relatively small and independent to nanotube’s chemical doping. For tunnel oxide thickness $\ge 2$ nm, photogenerated carrier accumulation at silicon/oxide interface considerably enhances the electrostatic doping effect. The effect of tunnel oxide thickness variation on fill factor and open circuit voltage is shown to be qualitatively similar to standard bulk metal–insulator–silicon solar cells. Our model predicts an optimal oxide thickness of $\sim 1$ nm which confirms the experimental reports.

This paper investigates the plasma-spraying technique as applied to oxide cathodes compared with the conventional coating method. In the conventional oxide cathode manufacturing process, a carbonate powder layer BaSrCa(CO3) is either painted or sprayed onto the nickel-base material at room temperature after the carbonate powder has been mixed with a nitrocellulose binder to provide adhesion to the nickel surface. However, the by-products deposited due to the coating of the oxide cathode and the decomposing process, combined with the relatively weak adhesion resulting from this coating method, undermine the performance of the oxide cathode. Plasma spraying can produce a high-quality coating by applying a relatively inert medium using a high-temperature high-particle velocity process. Impacts on the performance of the plasma-sprayed oxide cathode, as compared with a conventionally coated oxide cathode, are presented. The experimental results show that the pulsed-current emission density of a plasma-sprayed oxide cathode is nearly twice that of the conventionally coated oxide cathode, whereas the evaporation rate of the plasma-sprayed oxide cathode is only 10% as much as the conventionally coated oxide cathode.

An electrophoretic display (EPD) cell with a triple-layered microcavity structure was fabricated using a convenient dry film resist. The inherent structural advantage arising from the function of the middle channel layer as a background colored state enabled the EPD to operate with two different-colored states by using a single type of electronic-ink particles, thereby eliminating the possible agglomeration of oppositely charged ink particles and supporting the potential application of the proposed structure to color the electronic paper. The preliminary operation of this new EPD structure was demonstrated as white and blue display states on a rigid glass exhibiting a contrast ratio of 1.5 : 1 with saturation voltages of + 30 and -30 V, respectively. Successful demonstrations on both the indium-tin-oxide-patterned glass and flexible polyethylene substrates are also provided.

We demonstrate that the residual carbon concentration in the drift region can have a significant impact on the reverse leakage, breakdown voltage, and breakdown stability of GaN-on-GaN vertical diodes. Two generations (Gen1, Gen2) of polarization-doped p-n junctions with different C concentrations were compared, in terms of avalanche voltage, avalanche instability, and deep-level concentration. The original results collected within this paper show that: 1) both generations of devices can safely reach the avalanche regime; diodes with a lower residual CN have a higher reverse leakage and a lower avalanche voltage, due to an uneven distribution of the electric field; 2) the presence of residual carbon can lead to breakdown walkout, i.e. a recoverable increase in breakdown voltage under reverse-bias stress. Specifically, devices with higher C concentration show a fully-recoverable breakdown walkout, whereas the breakdown voltage is stable in devices with lower C concentration; and 3) steady-state photocapacitance measurements confirm the presence of CN in both generations, and are used to assess the relative difference in concentration between Gen1 and Gen2, even for levels below secondary ion mass spectroscopy (SIMS) sensitivity. The results described in this paper indicate the existence of a trade-off between breakdown voltage (increasing by improving compensation) and breakdown stability (improving by reducing CN concentration) and are of fundamental importance for the optimization of GaN power devices.

Detailed physics of the third quadrant electrical characteristics of 1.2-kV rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs, based on experimentally measured data and TCAD numerical simulations, are described in this paper for the first time. The power MOSFETs with various channel lengths (0.3, 0.5, 0.8, 1.1 $\mu \text{m}$ ) used in this paper were fabricated in a 6-in commercial foundry. Numerical simulations verified that there are two current paths in the third quadrant: 1) through the base region and 2) through the p-n body diode. This paper demonstrates that the Acc MOSFETs have a smaller third quadrant knee voltage ( ${V}_{{\text {knee}}})$ of −1.2 V compared with −1.9 V for the Inv MOSFETs (at ${V}_{g} = {0}$ V and room temperature). Numerical simulations show that this difference is due to a smaller potential barrier for electron transport from the drain to the source in the base region for accumulation channel devices than inversion channel devices. Acc devices are shown to have a lower voltage drop in the third quadrant.

We report in this paper the design and fabrication of single-chip alternating current-LEDs (AC-LEDs) by monolithically integrating, for the first time, high-breakdown Schottky barrier diodes (SBDs) and micro-LED arrays using III-nitride LED epi-wafers of standard specs for volume production. A technique of cyclic mixed-etching has been introduced to restore the surface of inductively coupled-plasma (ICP) etching processed gallium nitride to device quality for fabricating high-breakdown Schottky junctions. Proof-of-concept single-chip AC-LED devices and a prototype driver-free white AC-LED lamp were demonstrated, showing high-efficiency LED emission, high chip area utilization efficiency, low power loss of the on-chip SBD bridge rectifier, and good luminous efficacy of the prototype AC-LED lamp. This paper paves the way toward mass-producing reliable and low-cost driver-free AC-LED lamps for solid-state lighting with existing LED manufacturing infrastructures.

This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 °C–500 °C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation.

To develop an efficient thermal design for gallium-nitride (GaN) high-electron-mobility transistors (HEMTs) that usually hold a super-high-power density, it is essential to accurately predict the junction temperature. In GaN HEMTs, the heat transfer process is dominated by thermal spreading resistance. Moreover, the phonon mean free paths (MFPs) of GaN are comparable with the channel layer thickness and the heat spot width. Thus, a ballistic effect emerges, resulting in the invalidity of Fourier’s heat conduction law. Therefore, Fourier’s law-based thermal resistance model should be reexamined and modified for this case. In this paper, we used the phonon Monte Carlo (MC) method to investigate the thermal spreading resistance in a ballistic-diffusive regime for GaN HEMTs. Our simulation results indicate that the ballistic effect significantly altered the temperature distributions within channel layers and resulted in a dramatic increase in the thermal resistance when compared with Fourier’s law-based predictions. Furthermore, a semiempirical thermal resistance model with a fitting parameter was derived. This model can accurately address the issues of thermal spreading and the ballistic effect. This paper can provide a more in-depth understanding of the thermal spreading resistance in a ballistic-diffusive regime, and it can be useful for the prediction of junction temperatures and for the thermal management of HEMTs.

This paper clarifies the correct transmission mechanism, misattributed in the previous research, of a hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) device. Complete drain current–gate voltage ( ${I}_{\text {D}}$ – ${V}_{\text {G}}$ ) transfer characteristics including the forward and backward gate sweeps (gate voltage carried out in the OFF-state $\to $ on-state and the ON-state $\to $ OFF-state) are performed, and the physics models of an energy-band schematic are clearly explained. This paper reveals that the ${I}_{\text {D}}$ – ${V}_{\text {G}}$ curve stretch-out behavior of the subthreshold region is due to the leakage of the Poole–Frenkel region. At the Poole–Frenkel regions, electrons transfer to the drain terminal, and holes remain in the valance band of the a-Si:H bulk. The remaining holes represent the positive voltage and cause the electron barrier height lowering. This causes an increase in subthreshold current of the subthreshold region. Finally, three experiments are performed to prove the correctness of these models, and the a-Si TFTs device improvement methods will be proposed to enhance the stability and performance of product of the a-Si TFTs.

International audience; Abstract:This paper details an extraction procedure to fully model the transient self-heating of transistors from a GaN HEMT technology. Frequency-resolved gate resistance thermometry (f-GRT) is used to extract the thermal impedance of HEMTs with various gate widths. A fully scalable analytical model is developed from the experimental results. In the second stage, transient thermoreflectance imaging (TTI) is used to bring deeper insights into the HEMTs' temperature distribution by individually extracting the transient self-heating of each finger. TTI results are further used to successfully validate the f-GRT results and the modeling of the thermal impedance. Overall, f-GRT is demonstrated to be a fast and robust method for characterizing the transient thermal characteristics of a GaN HEMT. For the first time to the authors' knowledge, a scalable model of the thermal impedance is extracted fully from experimental results.

In this paper, an inner ultrathin oxide metal–oxide–semiconductor (MOS) capacitor is fabricated with another outer MOS-gate ring as a coupling controller. Capacitance–voltage characteristics of inner MOS capacitor show that the excess minority carriers supplied from the outer MOS-gate ring can efficiently change the inner capacitance ( ${C} _{\text {inner}}$ ). It is observed that outer MOS-gate ring under the conditions at floating and at ground has quite different coupling effects on ${C} _{\text {inner}}$ when the inner MOS is biased at 1 V. Comparing to ${V} _{\text {outer}} = \text {floating}$ , ${C} _{\text {inner}}$ reduces significantly when ${V} _{\text {outer}} = {0}$ V at 1k Hz. The transient behavior of ${C} _{\text {inner}}$ as ${V} _{\text {outer}}$ changes from 0 V to floating is long enough to read, and the difference of two capacitance values can be regarded as two states. As a result, a two capacitance states operation is proposed for possible memory application. Based on the experimental results, the possible memory cell configuration is designed. Comparing to the present emerging memories, since the two states in this paper are in conditions of floating and 0 V, ultralow power is consumed, which is believed a promising concept for future memory application.

In this paper, an analytical model has been developed to observe the recombination losses involved in a tunnel oxide passivated contact solar cell with a carrier-selective layer constituting polycrystalline silicon (poly-Si). The main focus of this paper is to observe the contribution of each component of recombination current density and its effect on open-circuit voltage, Voc. The effect of emitter saturation current density (Joe), surface recombination velocity, substrate thickness, and doping density of carrier-selective layer on Voc has been presented. The analysis indicates that Voc = 766 mV can be achieved for Joe = 2 fA/cm2, and a doping density of poly-Si > 1021cm−3 in a c-Si/SiO2/poly-Si contact for a 50- $\mu \text{m}$ -thick substrate in case of ideal surface passivation. For identical conditions, Voc attains a lower value of 750mV for a 180- $\mu \text{m}$ -thick substrate. The dependence of Voc on bandgap of tunnel layers has also been observed by considering other materials like Si3N4 and SiC. These results from the analyticalmodel have been compared with results froma simulation using automat FOR simulation of HETerostructures v2.5 and have been found to be in good agreement with each other.

In this paper, we have developed a physics-based analytical model for the electrical characteristics of passivated silicon carrier-selective contact (CSC) solar cells and validated it with numerical simulations. The model comprises analytical solutions of: 1) the Poisson equation, accurately capturing the level of inversion and accumulation at the crystalline silicon (c-Si) layer interfaces, and 2) the recombination current capturing the various recombination mechanisms at work in the solar cell. The calculations establish that CSC solar cells have the potential to achieve an efficiency greater than 26% even when both c-Si interfaces have realistic SRV values of 100 cm/s. The model helps illustrate the physics underlying the performance of CSC solar cells for variation in key device parameters such as surface recombination velocities, bulk lifetime, contact layer doping, and amorphous silicon (a-Si) thickness amongst others. By circumventing the need for resource-intensive numerical simulations, the analytical model described in this paper can assist in the design and development of high-performance CSC solar cells.

In part I of this paper, we developed physical insights into the role and impact of acceptor and donor traps—resulting from C-doping in GaN buffer—on avalanche breakdown in AlGaN/GaN HEMT devices. It was found that the donor traps are mandatory to explain the breakdown voltage improvement. In this paper, silicon doping is proposed and explored as an alternative to independently engineer donor trap concentration and profile. Keeping in mind the acceptor and donor trap relative concentration requirement for achieving higher breakdown buffer, as depicted in part I of this paper, silicon & carbon codoping of GaN buffer is proposed and explored in this paper. The proposed improvement in breakdown voltage is supported by physical insight into the avalanche phenomena and role of acceptor/donor traps. GaN buffer design parameters and their impact on breakdown voltage as well as leakage current are presented. Finally, a modified Si-doping profile in the GaN buffer is proposed to lower the C-doping concentration near GaN channel to mitigate the adverse effects of acceptor traps in GaN buffer.

Because of charge trapping in GaN HEMTs, dc characteristics of these devices are not representative of high-frequency operation. The advanced spice model GaN model presented in Part I of this paper is combined with a Shockley–Reed–Hall-based trap model, yielding a comprehensive FET model for GaN HEMTs which can accurately model GaN devices exhibiting trapping-related dispersion effects. Measurement results of the dc and pulsed output and transfer characteristics of a commercially available GaN HEMT are presented, trapping in the device is modeled, and excellent fit to the measured data is shown. This paper presents an accurate model of trapping which is validated for eight different quiescent bias points of pulse measurements, with quiescent drain voltage ranging from 5 to 20 V and quiescent gate voltage ranging from −2.8 to −3.8 V, and a large range of gate and drain voltages to which the device was pulsed in the pulse measurements and at which the device was measured in the dc measurements, with gate voltage ranging from −4 to 0.4 V and drain voltage ranging from 0 to 40 V. This paper also presents high-frequency (10 GHz) large-signal RF validation of the model for optimal complex load condition.

This paper presents the 2-D numerical simulation results of single-event burnout (SEB) in 4H-SiC junction barrier Schottky (JBS) diode by low carrier lifetime control (LCLC) for the first time. We investigate the SEB performance based on an 1800-V JBS structure and find that the most sensitive ion’s strike position is the middle of junction spacing because of the punchthrough of the electric field at anode contact. Then, the SEB hardening mechanism of LCLC is studied in this paper that the double-sided peak electric field can be effectively improved which results in a significantly decrease of maximal temperature. For the incident particle with different linear energy transfer values, we find that the SEB threshold voltage can be substantially enhanced when the carrier lifetime ( $\tau $ ) is under a certain value. In addition, the basic characteristics with LCLC are discussed that the forward and reversed characteristics are hardly affected.

Esaki diodes based on interband tunneling have the characteristics of negative differential resistance (NDR) and ultrafast transient time, which lead to broad applications including oscillators, multivalue memories, and terahertz detectors. In this paper, we present the first demonstration of Esaki diodes based on 2-D/3-D heterojunctions—more specifically, chemical vapor deposition MoS2 on degenerately doped silicon. As compared to traditional 3-D heterostructures, these 2-D/3-D heterostructures have the following advantages: dislocation-free 2-D crystals even when the lattices are mismatched, dangling bond-free surface, and capability for large-scale synthesis at low cost. In this paper, monolayer, bilayer, and trilayer MoS2 are synthesized directly on degenerated Si substrate, forming the ultraclean heterostructures without surface contamination from tape and resist. Based on these pristine heterostructures, we are able to observe prominent NDR effect at room temperature. This NDR effect is attributed to the degenerately p-type doping in silicon and the natural n-type doping in MoS2. We also found that the peak voltage corresponding to the local maximum tunneling current depends on the MoS2 thickness. While MoS2 is changing from the monolayer (0.7 nm) to bulk (9.5 nm), the peak voltage increases from 0.8 to 1.6 V. This phenomenon can be explained by the energy-level differences between the monolayer and bulk MoS2. This paper provides the experimental groundwork for the synthesis of transition metal dichalcogenides on degenerately doped Si substrates and opens up new and exciting opportunities for electronic applications of 2-D/3-D heterostructures.

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPt x NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPt x NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior.

Many methods have been proposed for the experimental determination of the collector resistance in bipolar junction transistors and HBTs. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs with a large variety of device sizes fabricated in different technologies and generations, including high-speed and high-voltage transistors. First, the accuracy of those methods, which are based on an extraction from single-transistor characteristics, is evaluated from simulated data using a sophisticated compact model and, where applicable, also device simulation. This approach allows the origin of observed inaccuracies or failures of certain methods to be identified. Second, the test structure-based methods are reviewed, and third, all methods were applied to experimental data. This paper and its results provide insight into each method’s accuracy; its application limits with respect to a technology, a device size, and an operating range as well as its requirements in terms of equipment and extraction effort.

Performance limitations of superjunction (SJ) devices due to charge imbalance (CI) are analyzed in this paper. It is demonstrated that in the presence of CI, the specific on-resistance has a quadratic dependence on blocking voltage, similar to a conventional drift region. We also show that by designing the SJ structure with an optimally modified pillar doping, we can achieve better performance under conditions of CI. The design guidelines presented in this paper are applicable to any semiconductor, although all calculations are based on silicon carbide.

4H-silicon carbide (SiC) is a suitable candidate for high-temperature and radiation prone applications, due to its superior electrical and material properties. Several researchers have demonstrated small-scale logic circuits, entirely in 4H-SiC; however, to build a complete electronic module in 4H-SiC, a memory component is yet to be developed. This paper presents for the first time the design, optimization, and performance analysis of a 4H-SiC-based bipolar memory column including a static random access memory cell and peripherals, designed for voltages as low as 5 V. The memory column has average noise margins of 2 V and delays in the range of few nanoseconds at room temperature. The proposed memory architecture also demonstrates robust operation across a wide range of temperatures (27 °C–500 °C) with stable noise margins and speeds. This paper validates the potential of developing memory architectures in 4H-SiC, which operates reliably for varying conditions, paving the way to build complete electronic systems entirely based on 4H-SiC.

A systematic analytical investigation of the charge distribution and gate control of the normally-off GaN double-channel MOS-HEMT (DC-MOS-HEMT) is presented in this paper. Compared to conventional GaN MOS-HEMT, the DC-MOS-HEMT features a thin AlN insertion layer (AlN-ISL) below the original two dimensional electron gas (2DEG) channel, thus forming a second channel at the interface between AlN-ISL and the underlying GaN. This paper reveals the impact of the AlN-ISL on the 2DEG distribution and the gate control of the channels. The sensitivity of ${V}_{\text {th}}$ against the recess depth is also analytically studied and is found to be nearly independent of the recess depth as long as the recess is terminated in the upper channel layer. The analytical results are well supported by numerical device simulations, and the physical mechanisms behind these findings are explained along with the analytical investigations.

With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation. The anisotropic thermal conductivity of nanosheets with the dependence of silicon thickness and temperature is implemented in the FEM simulator to evaluate thermal behavior accurately. The impact of layout design on thermal properties is investigated comprehensively from single device to device arrays with implication on electrical performance. The results indicate that the width of nanosheet is the key parameter to make the tradeoffs between self-heating and electrical characteristic. Meanwhile, the optimizations of layout design are given to suppress the thermal effects, including self-heating, nonuniformity of temperature, and thermal crosstalk at device level. This paper will provide guidelines for layout design, thermal management, device performance, and thermal-aware reliability prediction in the GAA-stacked structure.

This paper presents experimental and simulation analysis of an $\Omega $ -shaped silicon junctionless nanowire field-effect transistor (JL-NWT) with gate lengths of 150 nm and diameter of the Si channel of 8 nm. Our experimental measurements reveal that the ON-currents up to 1.15 mA/ $\mu \text{m}$ for 1.0 V and 2.52 mA/ $\mu \text{m}$ for the 1.8-V gate overdrive with an OFF-current set at 100 nA/ $\mu \text{m}$ . Also, the experiment data reveal more than eight orders of magnitude ON-current to OFF-current ratios and an excellent subthreshold slope of 66 mV/dec recorded at room temperature. The obtained experimental current–voltage characteristics are used as a reference point to calibrate the simulations models used in this paper. Our simulation data show good agreement with the experimental results. All simulations are based on drift-diffusion formalism with activated density gradient quantum corrections. Once the simulations methodology is established, the simulations are calibrated to the experimental data. After this, we have performed statistical numerical experiments of a set of 500 different JL-NWTs. Each device has a unique random distribution of the discrete dopants within the silicon body. From those statistical simulations, we extracted important figures of merit, such as OFF-current and ON-current, subthreshold slope, and voltage threshold. The performed statistical analysis, on samples of those 500 JL-NWTs, shows that the mean ${I}_{D} - {V}_{\text {Gs}}$ characteristic is in excellent agreement with the experimental measurements. Moreover, the mean ${I}_{D} - {V}_{\text {Gs}}$ characteristic reproduces better the subthreshold slope data obtained from the experiment in comparison to the continuous model simulation. Finally, performance predictions for the JL transistor with shorter gate lengths and thinner oxide regions are carried out. Among the simulated JL transistors, the configuration with 25-nm gate length and 2-nm oxide thickness shows the most promising characteristics offering scalable designs.

In this paper, a high-quality crystalline thin film (~10 nm) of titanium dioxide (TiO2-II) phase is grown on p-GaAs $\langle 100\rangle $ substrate by employing the vapor–liquid–solid method. The formation of crystalline TiO2-II films is confirmed by X-ray diffraction study. A very small rms surface roughness of ~1 nm has been measured from atomic force microscopy. The capacitance–voltage characteristics of Al/TiO2-II/GaAs metal–oxide–semiconductor (MOS) capacitor indicate the growth of excellent thin film of TiO2-II phase with high effective dielectric constant of 28, 35, 65, and 14 for the as-grown and 600 °C, 625 °C, and 650 °C annealed samples, respectively. An effective oxide thickness of ~0.7 nm, a negligible hysteresis of 10 mV, very small frequency dispersion of 3.5%, and a reduced gate leakage current of ~10−13 A/ $\mu \text{m}^{\textsf {2}}$ at +2 V are achieved due to annealing in the temperature range of 600 °C–625 °C. Thus, this paper provides a cost-effective novel alternative technique to grow high-quality TiO2-II films on GaAs substrate which may be used as the reliable high- ${k}$ gate dielectrics on III–V semiconductor-based MOS devices and circuits.

This paper describes the separation between the area and the perimeter current density components of 4H-SiC vertical p+-i-n diode with a circular Al+ implanted emitter of different diameters in the range 150– $1000~\mu \text{m}$ and for temperatures of measurement in the range 30–290 °C. It is shown that before the diode series resistances become dominant, the forward current is given by the sum of an area plus a perimeter component, both of exponential trend with ideality factor 2; while toward high voltages, an area component with exponential trend and ideality factor 1 adds to the previous components. Moreover, this paper shows that forward area and perimeter current density components can be used for a straightforward identification of the parameters controlling the current transport, provided that they can be fit by the p-n junction equations in the frame of the abrupt junction approximation. Finally, this paper shows that the area reverse current density can be used for the identification of the electrically active defects in the drift layer.

Although oxide thin-film transistors (TFTs) have drawn great interests in flexible displays, a key obstacle is the requirement of high-temperature annealing to realized mobility>10 cm $^{2}/\text {V}\cdot \text {s}$ . In this paper, a fully room-temperature strategy, involving the deposition of ~10 nm In–Ga–Zn–O (IGZO) channel layer and ~4 nm Al2O3 passivation layer, is introduced. The as-prepared flexible TFT on polymide substrate exhibits a saturation mobility of 15.3 cm $^{2}/\text {V}\cdot \text {s}$ , $V_{{\text {th}}}$ of 3.08 V, and on/off current ratio of $2.3\times 10^{{\text {7}}}$ . Thickness-dependent analysis indicates that the interface between Al2O3 and IGZO is composed of negative O-rich layer, which impel the energy band bending inside the IGZO layers and release of electrons from traps. This paper opens up a route to achieve fully room-temperature fabrication of high-performance flexible TFT.

With the development of novel device applications, e.g., in the field of Internet of Things or point-of-care personalized diagnostic systems, came an increased demand for MESFETs for fast and low-power consumption integrated circuits and active-matrix displays. In this paper, we present fabrication and characterization of transparent Ru–Si–O/In–Ga–Zn–O MESFETs on flexible substrates. The use of transparent conducting oxide, namely, Ru–Si–O, as Schottky gate electrode, allows for processing the devices at room temperature, enabling the utilization of such low-temperature substrates as polyethylene terephthalate foil and paper. It was shown that tuning the device geometry allows realization of transistors providing on-current up to 2 mA, while the highest on-to-off current ratio equals $2\times 10^{\mathrm { {5}}}$ , with off-current below 1 nA, carrier mobility in the channel exceeds 9 cm $^{\mathrm { {2}}}\cdot \text{V}^{\mathrm { {-1}}}\cdot \text{s}^{\mathrm { {-1}}}$ , and subthreshold swing is below 250 mV $\cdot $ decade $^{\mathrm { {-1}}}$ .

This paper presents using ultrasonic spray pyrolysis deposition method to grow MgO nanorod arrays on the top surface and the sidewall of the GaN-based ultraviolet light-emitting diodes. It is found that when the thickness of the MgO film is over 60 nm, the self-assembled MgO nanorod arrays are obtained. Transmission electron microscopy, scanning electron microscopy, X-ray diffraction, X-ray photoelectron spectroscopy, refractive index, extinction coefficient, and photoluminescence spectrum are used to analyze the structural, chemical, and optical characteristics of the MgO nanorod arrays. The LED chip with the MgO nanorod arrays shows slightly degraded electrical characteristics for it requires a higher forward voltage to provide 0.35-A forward current and higher series resistance. However, the LED chip with the MgO nanorod arrays has great improvement in electroluminescence and efficiency. Compared to the LED chip with a standard SiO2 passivation layer, the LED chip with the MgO nanorod arrays shows improvement of 14.1% in light output power (LOP), 12% in external quantum efficiency and wall plug efficiency. The uniformity of the LED performance like forward voltage, LOP, and wall-plug efficiency is investigated in this paper.

The physical mechanisms involved in the trapping and de-trapping processes associated with surface donor traps in gallium nitride (GaN) transistors are discussed in this paper. The paper challenges the conventional transient techniques adopted for extrapolating the trap energy level via experiments and TCAD simulations. Transient TCAD simulations were employed to reproduce the time-dependent electrical behavior of a metal-on-insulator field-effect transistor and explain the influence of the electric field and energy barrier on the transient time associated with the trapping and de-trapping mechanisms of surface traps. The comparison between three test structures and the relative variation of the trapping and de-trapping times with the bias and trap parameters leads to the suggestion of a proposed test structure and bias configuration to accurately extrapolate the energy level of surface traps in GaN transistors.

In this paper, a p-channel vertical 4H-silicon carbide (SiC) MOSFET (SiC p-MOSFET) has been fabricated successfully for the first time as a potential candidate for the complementary inverter application. The static characteristics and the robustness, including short circuit and avalanche capabilities of the p-MOSFET, are experimentally tested. Moreover, the comparison between the p-MOSFET and similar rating n-MOSFET is carried out. The short-circuit capability is 15% higher than that of the n-channel MOSFET. Furthermore, this paper also provides the physical insights into the failure mechanism during the short-circuit transient of the p- and n-MOSFET. Meanwhile, an electro-thermal analytical model is proposed to explain the thermal distribution during this transient. Last, the avalanche withstand time of the fabricated SiC p-MOSFET is experimentally demonstrated to be 27% higher than that of the n-channel one. It is concluded that the SiC p-MOSFET could be a competitive power switch applicable for high-frequency complementary inverters.

As the transparent contact in radial p-n junction core-shell nanowire array solar cells can be either planar or conformal, the characteristics of these two types of device structure would be very different since conformal contact gives rise to severe band bending. Although radial p-n junction GaAs core-shell nanowire array solar cell with conformal transparent contact has been briefly inferred to have an inferior performance compared to the same nanowire array solar cell with planar transparent contact, the characteristics of these two types of radial p-n junction core-shell nanowire array solar cells are not known. Furthermore, it is unknown how the performance of these two types of solar cell compares with each other when the nanowire design parameters are optimized according to device physics of these two types of solar cell. In this paper, it is shown that radial p-n junction GaAs core-shell nanowire array solar cells with planar transparent contact are prone to carrier avalanche breakdown, and hence have a limited range of doping density. On the other hand, carrier diffusion in radial p-n junction GaAs core-shell nanowire array solar cells with conformal transparent contact is poor and hence requires a high doping to the core in order to increase the output voltage. All in all, this paper reveals that either type of transparent contact structure yields essentially the same energy conversion efficiency as long as the radial p-n junction GaAs core-shell nanowires are designed to suit the device physics of the type of transparent contact.

Wafer-scale, CMOS compatible graphene transfer has been established for device fabrication and can be integrated into a conventional CMOS process flow back end of the line. In Part I of this paper, statistical analysis of graphene FET (GFET) devices fabricated on wafer scale is presented. Device yield is approximately 75% (for 4500 devices) measured in terms of the quality of the top gate, oxide layer, and graphene channel. Statistical evaluation of the device yield reveals that device failure occurs primarily during the graphene transfer step. In Part II of this paper, device statistics are further examined to reveal the primary mechanism behind device failure. The analysis from Part II suggests that significant improvements to device yield, variability, and performance can be achieved through mitigation of compressive strain introduced in the graphene layer during the graphene transfer process. The combined analyses from Parts I and II present an overview of mechanisms influencing GFET behavior as well as device yield. These mechanisms include residues on the graphene surface, tears, cracks, contact resistance at the graphene/metal interface, gate leakage as well as the effects of postprocessing.

A low-leakage electrostatic discharge power clamp with adjustable triggering voltage ( ${V}_{t1})$ is proposed in this paper. By enabling the static detection path using the transient one, the proposed clamp achieves a wide range of adjustable ${V}_{t1}$ while maintaining low standby leakage current ( ${I}_{\text {leak}})$ , which overcomes the flaw of traditional static clamps. Besides, the adjustable ${V}_{t1}$ with low ${I}_{\text {leak}}$ is attractive for nanoscale applications. Moreover, the proposed clamp achieves enhanced false-triggering immunity over traditional transient clamps. The proposed clamp is successfully verified in a 65-nm CMOS process. Aside from silicon verifications, detailed comparisons with prior arts and practical application concerns are also addressed in this paper.

This paper presents the first fully integrated sigma–delta modulator implemented in an in-house silicon carbide (SiC) bipolar technology for high-temperature applications. A second-order 1-b continuous-time architecture is adopted. Dual-loop compensation technique is employed to accommodate one clock period comparator delay. The circuits are designed to have enough margins without degrading the modulator’s performance, considering the variation of device parameters over a large temperature range. The measurement results show that from room temperature to 500 °C, the modulator’s peak SNDR is constant around 30 dB at a clock speed of 512 kHz. The chip area of the modulator is $6.9~\text {mm} \times 2.8$ mm with one metal layer. It consumes around 1 W from a 15 V power supply. This paper demonstrates the feasibility to further develop highly integrated SiC bipolar junction transistor integrated circuits for extremely high-temperature sensing applications.

Black phosphorus (BP) has arisen as the preferred material with great applications in electronics devices. Nanoinvestigation of the thermal properties and thermal stability of BP transistors at the nanoscale is extremely challenging. This paper reports nanothermal investigation of BP MOSFET transistors, using the dual-phase-lagging (DPL) model including the phonon scattering. The thermal properties of the BP including the thermal conductivity and volumetric heat generation rate considered depend on the temperature. The results are compared with those obtained from the classical silicon MOSFET. Using the finite-element method, we have demonstrated that the temperature variation of the BP MOSFET does not exceed 305 K instead of 319 K in the case of a classical MOSFET. This paper not only exposes various novel properties of BP transistors, but also demonstrates the great usefulness of the BP transistors.

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( ${C}_{rss})$ . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher ${C}_{{{\text {rss}}}}$ and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic ${R}_{{ \mathrm{ON}}}$ during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high ${V}_{{{\text {DS}}}}$ , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high ${V}_{{{\text {DS}}}}$ is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained.

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained.

In this paper, a 1-Transitor (1-T) capacitorless dynamic random access memory (DRAM) using bandgap-engineered silicon-germanium Bipolar ionization metal oxide semiconductor field effect transistor (I-MOS) is investigated through numerical simulations. We have demonstrated the application of the proposed Si0.6Ge0.4 Bipolar I-MOS for realization of a 1-T capacitorless DRAM. The proposed device can achieve hysteresis at significantly lower drain voltages ( $V_{\mathrm{LD}} =0.45$ V to $V_{\mathrm{LU}} =1.15$ V), in comparison to the inversion mode device ( $V_{\mathrm{LD}} = 8$ V to $V_{\mathrm{LU}} =11$ V). In addition, the proposed 1-T capacitorless DRAM exhibits a wider hysteresis window ( $\Delta \text{V}$ ) of the order ~700 mV and a sensing margin ( $\Delta \text{I}$ ) of ~5 orders in comparison to the inversion mode based 1-T capacitorless DRAM. Moreover, the proposed 1-T capacitorless DRAM exhibits the retention time of ~750 msec and ~320 msec for T = 25 °C and T = 85 °C, respectively. The proposed 1-T capacitorless DRAM also shows nondestructive read and an extreme long-term endurance. Therefore, the results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology.

Direct conversion crystalline silicon X-ray imagers are used for low-energy X-ray photon (4–20 keV) detection in scientific research applications such as protein crystallography. In this paper, we demonstrate a novel pixel architecture that integrates a crystalline silicon X-ray detector with a thin-film transistor amorphous silicon pixel readout circuit. We describe a simplified two-mask process to fabricate a complete imaging array and present preliminary results that show the fabricated pixel to be sensitive to 5.89-keV photons from a low activity Fe-55 gamma source. This paper presented can expedite the development of high spatial resolution, low cost, direct conversion imagers for X-ray diffraction and crystallography applications.

Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs).

A novel optically activated cascode gallium nitride (GaN) high-electron-mobility transistor (HEMT) is introduced and evaluated in this paper. Furthermore, optical triggering of GaN HEMT structures by cost-effective and high-power long-wavelength light sources is proposed for the first time. In electrical domain, GaN HEMTs suffer from being normally on devices, making it more complicated to design and implement gate drivers for these devices. In optical domain, GaN devices suffer from being triggered by low-power short-wavelength light sources, making them significantly more expensive and practically unprofitable. Therefore, a new optical cascode (OC) GaN HEMT is proposed in this paper to solve the problems of both electrical and optical domains. The structure of this OC GaN HEMT includes a high-power normally on (depletion mode) GaN HEMT in combination with a low-power optical switch in cascode configuration. This OC not only realizes an overall normally off (enhancementmode) structure, but also offers activationwith cost-effective long-wavelength optical sources. It also offers a single-biased configurationwithout the need for complicated electrical gate drivers. Unlike conventional electrically activated cascode GaN HEMT structures, which may be prone to electromagnetic interference noise due to the high-frequency switching operation, the optical link in this proposed scheme is immune to external noise. The results showa high-frequency switching capability of 1MHz for theOCGaN HEMT under a bias voltage of 600 V and a current of 10 A. Less voltage and current ringing are observed in the OC compared with the electrical alternative due to the elimination of gate controlling inductance introduced in the electrical cascode configuration.

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability.

The base series resistance is an important parameter for bipolar junction transistors and heterojunction bipolar transistor (HBTs). Although many methods have been proposed for its experimental determination, their results vary significantly. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations including different device types, i.e. high-speed and high-voltage SiGe HBTs. The accuracy of the methods is evaluated by applying them to a sophisticated physics-based compact model, allowing to clearly detect and explain the causes for the observed inaccuracies or failures. The methods are then also applied to experimental data. In both cases, a large variety of device sizes have been investigated. This paper and its results provide insight into each method’s accuracy, its application limits with respect to a technology, device size, and operating range as well as its requirements in terms of equipment and extraction effort.

Silicon heterojunction solar cells having semiconducting oxide-selective contacts can revolutionize the photovoltaic industry with the promise of low cost and high efficiency. In this paper, we have identified the potential design issues of silicon heterojunction cell using simulation. This paper compares two possible electron-selective oxides (TiO2 and ZnO) and two possible hole-selective oxides (CuAlO2 and NiO). The Fermi level in the oxide at the oxide/metal interface is pinned by the metal (its workfunction and eventual interface dipoles). We considered this effect, which determines the effective workfunction of the metal contact as opposed to the actual metal workfunction. Our simulation suggests that Fermi level pinning has significant impact on the device performance. We also considered different interface passivation effects and oxide dopings in our simulation. The simulation suggests that high doping in oxides is beneficial to counter balance the effect of poor surface passivation. This paper provides an extensive understanding of the design of Si heterojunction solar cell using band-engineered semiconducting oxide as the selective contact replacing highly doped emitter and back surface field.