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In this paper, we demonstrate CMOS characteristics on a Si(110) surface using surface flattening processes and radical oxidation. A Si(110) surface is easily roughened by OH- ions in the cleaning solution compared with a Si(100) surface. A flat Si(110) surface is realized by the combination of flattening processes, which include a high-temperature wet oxidation, a radical oxidation, and a five-step room-temperature cleaning as a pregate-oxidation cleaning, which does not employ an alkali solution. On the flat surface, the current drivability of a p-channel MOSFET on a Si(110) surface is three times larger than that on a Si(100) surface, and the current drivability of an n-channel MOSFET on a Si(100) surface can be improved compared with that without the flattening processes and alkali-free cleaning. The 1/f noise of the n-channel MOSFET and p-channel MOSFET on a flattened Si(110) surface is one order of magnitude less than that of a conventional n-channel MOSFET on a Si(100) surface. Thus, a high-speed and low-flicker-noise p-channel MOSFET can be realized on a flat Si(110) surface. Furthermore, a CMOS implementation in which the current drivabilities of the p-channel and n-channel MOSFETs are balanced can be realized (balanced CMOS). These advantages are very useful in analog/digital mixed-signal circuits.

This paper reports that the low-frequency noise in p-channel MOSFETs fabricated on [110] and (100) crystallographic oriented silicon is related to the microroughness of the silicon surface. Since the conventional RCA cleaning process makes the surface rough, especially in the case of [110] orientation, the authors developed the so-called 5-step room temperature cleaning process that does not use alkaline solution. The combination of this new cleaning process with the microwave-excited high-density plasma oxidation process for the formation of the gate oxide, instead of the standard 900/spl deg/C thermal oxidation process, leads to a reduction of the microroughness and a drop in the 1/f noise level of more than one decade. Furthermore, this reduction is not only observed for the [110] orientation but also seen, albeit to a much lesser extent, for (100) if it is treated in the same way.

This paper focuses attention on electrical properties of ultra-thin silicon nitride films grown by radial line slot antenna high-density plasma system at a temperature of 400/spl deg/C as an advanced gate dielectric film. The results show low density of interface trap and bulk charge, lower leakage current than jet vapor deposition silicon nitride and thermally grown silicon oxide with same equivalent oxide thickness. Furthermore, they represent high breakdown field intensity, almost no stress-induced leakage current, very little trap generation even in high-field stress, and excellent resistance to boron penetration and oxidation.

An overview of ionizing radiation effects in imagers manufactured in a 0.18-mum CMOS image sensor technology is presented. Fourteen types of image sensors are characterized and irradiated by a 60Co source up to 5 kGy. The differences between these 14 designs allow us to separately estimate the effect of ionizing radiation on microlenses, on low- and zero-threshold-voltage MOSFETs and on several pixel layouts using P+ guard-rings and edgeless transistors. After irradiation, wavelength dependent responsivity drops are observed. All the sensors exhibit a large dark current increase attributed to the shallow trench isolation that surrounds the photodiodes. Saturation voltage rises and readout chain gain variations are also reported. Finally, the radiation hardening perspectives resulting from this paper are discussed.