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With lots of interest in negative capacitance field-effect transistors for ultralow-power complementary metal-oxide-semiconductor technology, negative capacitance thin-film transistors (NCTFTs) have also received much attention. Although previous studies on NCTFTs were done, the NC effect in organic-based TFTs was not studied yet. In this paper, P(VDF-TrFE) ferroelectric-gated P3HT semiconductor channel TFTs are experimentally demonstrated with solution-based fabrication process. Especially, this paper shed light on the NC effect in the organic based TFTs. The step-up current-voltage characteristics are repeatedly and reliably observed in diverse TFTs, and then, with the results, transconductance (gm) amplification implemented by the negative capacitance was delved. Moreover, with the aid of ferroelectric polarization switching, super steep-switching characteristic of the organic-based TFT was experimentally confirmed. These experimental results and discussion would be helpful in understanding NC effects in TFTs. [ABSTRACT FROM AUTHOR]

The article presents editorial policy of the journals which includes both manual and electronic submission.

Wide bandgap (WBG) semiconductors, especially silicon carbide (SiC) and gallium nitride (GaN), promise transformational advances in electrical power systems, with increased power conversion efficiency for transportation and renewable energy utilization. Compared with the semiconductor silicon, SiC and GaN materials offer significantly higher electrical and thermal conductivities, increased avalanche breakdown field strength, and improved ruggedness under extreme environmental operating conditions. These basic material properties translate into more compact and lightweight power conversion systems with significant energy savings, much improved signal sensing and transmission characteristics, and longer operating life in the field. [ABSTRACT FROM AUTHOR]

Tunnel FETs (TFETs) have been identified as the most promising steep slope devices for ultralow power logic circuits. In this paper, we demonstrate in-plane InAs/Si TFETs monolithically integrated on Si, using our recently developed template-assisted selective epitaxy approach. These devices represent some of the most scaled TFETs with dimensions of less than 30 nm, combined with excellent aggregate performance with average subthreshold swing (SS), of around 70 mV/decade combined with I\mathrm{\scriptscriptstyle ON} of a few \mu \textA / \mu \textm for |V\mathrm {\mathbf {DS}}| = |V\mathrm {\mathbf {GS}}| = 0.5 V. Here, we will discuss the device fabrication as well as the experimental electrical data. Extensive low temperature characterization and activation energy analysis is used to gain insights into the factors limiting device performance. Combined with the simulation study presented in part 2 of this paper, this will elucidate how traps are ultimately limiting the SS. [ABSTRACT FROM AUTHOR]

In this paper, we systematically evaluate the variation in the reversal delay of a nanomagnet driven by a longitudinal spin current under the influence of thermal noise. We then use the results to evaluate the performance of an all-spin-logic (ASL) circuit. First, we review and expand on the physics of previously published analytical models on stochastic nanomagnet switching. The limits of previously established models are defined, and it is shown that these models are valid for nanomagnet reversal times <200 ps. Second, the insight obtained from previous models allows us to represent the probability density function (pdf) of the nanomagnet switching delay using the double exponential function of the Fréchet distribution. The pdf of a single nanomagnet is extended to more complex nanomagnet circuit configurations. It is shown that the delay-variation penalty incurred by nanomagnets arranged in parallel configuration is dwarfed by the average delay increase for nanomagnets arranged in a series configuration. Finally, we demonstrate the impact of device-level performance variation on the circuit behavior using ASL logic gates. While the analysis presented in this paper uses an ASL-AND gate as the prototype switching circuit in the spin domain, the physical concepts are generic and can be extended to any complex spin-based circuit. [ABSTRACT FROM PUBLISHER]

In this paper, we present extensive characterization of low-frequency noise in advanced silicon germanium heterojunction bipolar transistors. We demonstrate the extraction methodology of base and collector noise spectral densities for a wide range of transistor geometries. In addition to 1/ $f$ noise, generation–recombination (G–R) mechanisms are observed at low bias in the base current noise. Their existence is confirmed by Random Telegraph Signal (RTS) noise measurements. 1/ $f$ and G–R components are extracted from the base current noise spectra and their bias dependencies are studied. Finally, base current noise spectral densities measured at the same base current density in different geometries are compared to study the individual contribution of 1/ $f$ noise from the periphery as well as the intrinsic device. Part II of this paper will discuss the modeling aspects and noise correlation. [ABSTRACT FROM AUTHOR]

The physical unclonable function (PUF) is a promising innovative hardware security primitive that leverages the inherent randomness in the physical systems to produce unique responses upon the inquiry of challenges, thus the PUF could serve as a fingerprint for device authentication. In this paper, we propose a novel PUF implementation exploiting the sneak paths in the resistive cross-point (X-point) array, as a hardware security primitive. The entanglement of the sneak paths in the X-point array greatly enhances the entropy of the physical system, thereby increasing the space of challenge-response pairs to make a strong PUF. The X-point PUF characteristics, such as uniqueness and reliability, are experimentally evaluated on the fabricated $12 \times 12$ cross-point arrays based on the Pt/HfOx/TiN structure. The measurement results show that the average inter-Hamming distance of the response bits is around 46.2% across 28 different arrays, showing sufficient uniqueness. The measurement results also demonstrate that 0% intra-Hamming distance (or 100% reliability) of the response bits can be maintained more than 7.2 h at 100 °C (or equivalently ten years at 40 °C). This paper demonstrates the feasibility of using X-point PUF as a lightweight and reliable PUF for device authentication. [ABSTRACT FROM PUBLISHER]

Thermionic energy converter (TEC) is a heat engine that generates electricity directly using heat as its source of energy and electron as its working fluid. Despite having a huge potential as an efficient direct energy conversion device, the progress in vacuum-based thermionic energy converter development has always been hindered by the space charge problem and the unavailability of materials with low work function. It is only recently that researchers have started to look back into this technology as recent advances in manufacturing technology techniques have made it possible to solve these problems, making TECs a viable option in replacing current energy production systems. The focus of this paper is to review the challenges of producing efficient and practical TECs, along with recent findings and developments in mitigating these challenges. Furthermore, this paper looked into potential applications of TECs, based on recent works and technologies, and found that, with certain improvements, it can be applied in many sectors. [ABSTRACT FROM PUBLISHER]

Recent advances in the fabrication technology have yielded nanometer-scale InGaAs quantum-well (QW) MOSFETs with extremely low and reproducible external contact and access region resistances. This allows, for the first time, a detailed analysis of the role of ballistic transport in the operation of these devices. This paper presents a systematic analysis of external resistance, ballistic resistance, and channel mobility in InGaAs QW-MOSFETs under near-equilibrium conditions, i.e., under very low drain-source bias. This is an important regime for device characterization. Devices with a wide range of channel lengths, from 70 to 650 nm, are investigated. Our analysis includes the consideration of the impact of carrier degeneracy in the QW channel. We show that unless the ballistic behavior in the intrinsic channel is accounted for, the standard extraction technique for external resistance grossly exaggerates its value as it incorporates the so-called ballistic resistance. By separating out the ballistic resistance, the external resistance in our devices is shown to be extremely low, $74~\Omega $ - \mu \text{m} , including both source and drain sides. This is thanks to our contact-first self-aligned Mo-contact technology. Furthermore, taking the advantage of the wide range of ballisticity of the devices studied in this paper, we demonstrate a methodology to self-consistently extract scattering-dependent effective mobility, mean-free-path length, and ballistic mobility. [ABSTRACT FROM AUTHOR]

A bond-pad charging protection design for charging-free reference transistor test structures was examined. This paper concludes that truly charging-free reference transistors cannot be realized with the one conventional bond-pad charging protection design of protecting transistor gates only. This, however, can be achieved by simultaneously protecting all terminals of the reference transistors. The simulations, in this paper, reconfirm the earlier important experimental conclusion that placing protection device(s) at transistor gates may inflict severe damage to transistor gate oxides instead of protecting them. The implication of the above suggests that attention may be required in a circuit layout design stage for those transistors which gates begin to connect, at high metal layers, to highly efficient leakage paths, such as protection devices, n-type source/drain diffusion regions, and VSS bus lines, which tend to pull transistor gates to low potentials during a backend integrated-circuit manufacturing process. This paper proposes an optimum bond-pad charging protection design for the truly charging-free reference transistor test structures by considering a minimum usage in a layout space and minimum gate oxide stress in the fuse zap-off process. [ABSTRACT FROM AUTHOR]

An emission–diffusion theory that describes MOSFETs from the ballistic to diffusive limits is developed. The approach extends the Crowell–Sze treatment of metal–semiconductor junctions to MOSFETs and is equivalent to the scattering/transmission model of the MOSFET. This paper demonstrates that the results of the transmission model can be obtained from a traditional, drift–diffusion analysis when the boundary conditions are properly specified, which suggests that the traditional drift–diffusion MOSFET models can also be extended to comprehend ballistic limits. [ABSTRACT FROM PUBLISHER]

Detailed physics of the third quadrant electrical characteristics of 1.2-kV rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs, based on experimentally measured data and TCAD numerical simulations, are described in this paper for the first time. The power MOSFETs with various channel lengths (0.3, 0.5, 0.8, 1.1 $\mu \text{m}$) used in this paper were fabricated in a 6-in commercial foundry. Numerical simulations verified that there are two current paths in the third quadrant: 1) through the base region and 2) through the p-n body diode. This paper demonstrates that the Acc MOSFETs have a smaller third quadrant knee voltage (${V}_{{\text {knee}}})$ of −1.2 V compared with −1.9 V for the Inv MOSFETs (at ${V}_{g} = {0}$ V and room temperature). Numerical simulations show that this difference is due to a smaller potential barrier for electron transport from the drain to the source in the base region for accumulation channel devices than inversion channel devices. Acc devices are shown to have a lower voltage drop in the third quadrant. [ABSTRACT FROM AUTHOR]

The effects of gamma rays on two kinds of GaN high-electron-mobility transistors (HEMTs) have been investigated in this paper. We have identified a gate degradation using a combination of optical and electrical measurements. We have demonstrated that the channel current under the degradation position is outside of the gate’s control. This degradation prevents the gate from fully pinching off the channel, creating a current concentration region when applying a reverse gate voltage. An integrated analysis, including ${I}$ – ${V}$ characterization, the emission microscope (EMMI) technique, and temperature-dependent measurements, was applied to study its mechanism. It is attributed to an irradiation-induced degradation in the Schottky contact. [ABSTRACT FROM AUTHOR]

Confocal gyrotron traveling-wave tube (gyro-TWT) is capable of operating in higher order modes, so it is attractive in high-frequency (> 100 GHz) band. However, the reported experimental and simulation results of confocal gyro-TWT usually operated at fundamental harmonic, so high external magnetic field was essential. In this paper, a second harmonic 220-GHz confocal gyro-TWT was designed through linear and nonlinear theory and particle-in-cell (PIC) simulation. The key problem of suppressing the backward-wave oscillations (BWOs) of both fundamental and second harmonics was solved by limiting the cavity length of the first section less than the critical BWOs length. In PIC simulations, the gyro-TWT operates at HE07 mode with an output power of 4.55 kW, the efficiency of 2.2% gain of 21.8 and the −3 dB bandwidth of 6 GHz. The calculated results from the nonlinear theory are in good agreement with the results from PIC simulation. [ABSTRACT FROM AUTHOR]

This paper presents an optical sensor based on amorphous In–Ga–Zn–O (a-IGZO) photo thin-film transistors (TFTs). To maintain a high signal-to-noise ratio (SNR) of the optical sensor against a variety of ambient white light, this paper employed a-IGZO photo-TFTs for detecting optical input signal sensitive only to short-wavelength light. Measurements of the photosensitivity for optical signal with different wavelengths and optical response for optical input signal under various white light irradiances are proposed to support the reliability of the a-IGZO photo-TFTs under different ambient white light conditions. This paper also simulates a-IGZO photo-TFTs under various white light conditions to predict and design the proposed new sensors and circuits. The simulation results indicated that the proposed optical sensor can maintain the obvious difference in the output voltages with or without optical input signal under the white light irradiances of 0, 268, and $750~\mu \text{W}$ /cm2, demonstrating the feasibility and the reliability of the proposed optical pixel sensor. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel compact statistical model for the low-frequency noise (LFN) of MOS devices with halo implants. The compact model is suited for the incorporation in modern models, such as BSIM, PSP, and EKV, and can be used to predict the dependence of the LFN of halo-implanted MOSFETs with bias, temperature, geometry, and technological parameters. This compact model is based on the physics-based random telegraph noise (RTN) model, previously published by our group. The previous model was simplified in analytical expressions dependent on parameters and on physical quantities already calculated in modern compact models. Following the physics-based model, the LFN compact model predicts the large bias dependence of the LFN statistics induced by the halo implants in long-channel devices. Moreover, we show for the first time that the halo implants also induce a large temperature dependence of the LFN statistics for devices operated near the weak inversion or saturation, and the proposed compact model predicts this dependence. [ABSTRACT FROM AUTHOR]

In this paper, we report the characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz. The self-heating effect (SHE) in NWFETs is investigated experimentally using the small-signal output conductance (${g}_{{\text {ds}}}$) technique. The frequency-dependent complex thermal impedance, ${Z}_{{\text {th}}}({f})$ , is extracted by fitting an ${n}$ th-order thermal network with the experimental data. We show that the temperature rise $\Delta {T}$ (=85 °C) due to SHE is significant in short-channel silicon on insulator (SOI) NWFETs. Finally, we have evaluated the RF figure of merit (FOM) for these NWFETs as ${f}_{T}$ (=70 GHz) and ${f}_{\text {max}}$ (=80 GHz). We also report the RF performance metric sensitivity on temperature, $\partial {f}_{\text {max}}/\partial {T}_{{\text {amb}}}$ ($\approx -0.104$ GHz/K). The reported BSIM-CMG compact model shows a good correlation with the measurement data. [ABSTRACT FROM AUTHOR]

Efficiency roll-off defined as the rapid efficiency drop by increasing the electrical current density is a major issue in the design of novel organic light-emitting diodes (OLEDs) based on thermally activated delayed fluorescence (TADF). In this paper, it is shown that efficiency enhancement and suppression of efficiency roll-off in TADF OLEDs can be accomplished by broadening the exciton generation zone by precisely tuning the doping concentration of the TADF emissive material in the host matrix. This universal and simply tunable parameter can be applied to any TADF OLED to further enhance its performance characteristics. In this paper, a typical TADF OLED with realistic parameters is numerically investigated by solving the charge carrier transport and excitonic equations and taking into account all relevant processes such as triplet–triplet annihilation, triplet–polaron, and singlet–triplet quenching, and (reverse) intersystem crossing. It is shown that the internal quantum efficiency (IQE) decreases at very low and very high doping densities due to exciton distribution nonuniformity and charge balance factor reduction, respectively. Power efficiency depends on the IQE as well as the potential drop across the emissive layer and decreases at very low doping densities even for a perfectly balanced device; however, the reduction for an unbalanced device is much more substantial. For a perfectly balanced device with an emissive layer thickness of 30 nm, at a current density of 10 mAcm−2, the IQE can be increased from 18% to more than 58% by decreasing the doping concentration from ${c}= {15}$ % to 0.5%. Power efficiency reaches its peak value of 38 lm/W at 1.4% doping. [ABSTRACT FROM AUTHOR]

Ferroelectric (FE) materials are being studied for a variety of applications in memory, logic, and neuromorphic computing, for which predictive models of FE polarization are essential. In this paper, we present a Monte Carlo simulation framework capable of predicting the dynamic, history-dependent response of an FE under arbitrary input waveforms. The simulation is developed by generalizing the physics-based nucleation-limited switching model for polarization reversal in a polycrystalline FE. Measured polarization reversal data from fabricated FE Hf0.5Zr0.5O2 capacitors are used to extract the statistical distribution of FE grains. After parameter extraction, the model is able to predict the dynamics of the FE capacitor without further calibration. Finally, the model is applied to characterize the dynamic response of FE–dielectric bilayer structures and quantify the reduction in memory window due to device variability. [ABSTRACT FROM AUTHOR]

Multipactor is an electron discharge driven by secondary electron emission (SEE) that plagues microwave components, accelerator structures, space-borne systems, and other related electronics. Recently, a novel theoretical approach for multipactor based on principles from nonlinear dynamics and chaos theory has been expanded to a parallel-plate geometry. In this paper, this new theory is used to construct multipactor susceptibility diagrams that portray breakdown boundaries as a function of device parameters. These results are compared to industrial design standards and particle-in-cell simulations. [ABSTRACT FROM AUTHOR]

In this paper, AlGaN/GaN high-electron mobility transistors (HEMTs) with different fin configurations are fabricated and analyzed. Through S-parameter measurements and modeling of the designed devices, a detailed RF investigation on small-signal model parameters is performed under different biasing conditions. Good agreements between measured and simulated scattering parameters up to 40 GHz illustrate the validity and accuracy of the model. The influence of different fin structures on model parameters and linearity improvement is examined, and this can help to improve the frequency characteristics of fin structure by optimizing the fin length, fin width, and trench width. The significant linearity of Fin-HEMTs is confirmed by the analysis of the model parameters, which is the first time to study the small-signal characteristic of AlGaN/GaN Fin-HEMTs in detail. [ABSTRACT FROM AUTHOR]

This paper reports the very first systematic study on the physics of avalanche instability and safe operating area (SOA) reliability in AlGaN/GaN high-electron-mobility transistor (HEMT) using submicroseconds pulse characterization, poststress degradation analysis, well-calibrated TCAD simulations, and failure analysis by scanning electron microscopy (SEM) and transmission electron microscopy (TEM). Impacts of electrical and thermal effects on SOA boundary and avalanche instability are investigated. Trap-induced cumulative nature of degradation is studied in detail. The root cause for avalanche instability in AlGaN/GaN HEMTs is investigated. Postfailure SEM, energy dispersive X-ray (EDX), and TEM analysis reveal distinct failure modes in the presence and absence of carrier trapping. [ABSTRACT FROM AUTHOR]

In this paper, we argue that communication at the speed of light (CaSoL) through on-chip copper interconnects is possible in the near future based on giga-scale integration (GSI) technologies. A three-step algorithm is introduced to design the optimum buffers in such systems. HSPICE simulations show that a $1.3\times $ time of flight (${T}_{\text {F}}$) is reachable in 7-nm FinFET technology. It is also shown that such a design is by nature, robust, and immune to process variations and crosstalk noise. [ABSTRACT FROM AUTHOR]

A novel fast-switching lateral-insulated gate bipolar transistor (LIGBT) with double gates and integrated Schottky barrier diode (SBD) is proposed and studied in this paper by TCAD simulation. In order to reduce the turn-off time and maintain a low forward voltage drop, the proposed structure introduces an integrated SBD structure at the anode and an additional trench gate at the cathode. First, the integrated SBD provides an extra electron extraction path and the additional trench gate enhances the injection of the N+-cathode. Furthermore, the insulated oxide pillar between the N-buffer and integrated SBD further reduces the snapback voltage. Finally, the simulation results show that the turn-off time of the conventional LIGBT is 52.4% larger than that of trench/planar gate SBD (TP-SBD) LIGBT under the same forward voltage of 1.49 V. Moreover, the latch current density of TP-SBD LIGBT is increased by nearly 200% compared to that of the conventional LIGBT, while almost the same latch voltage is obtained, so the proposed TP-SBD LIGBT can improve the latch immunity. [ABSTRACT FROM AUTHOR]

In this paper, a charge plasma-based monolayer transition metal dichalcogenide (TMD) tunneling field-effect transistor (TFET) is investigated by solving self-consistent 3-D Poisson and Schrodinger equations in nonequilibrium Green’s function (NEGF) framework. We propose a work function engineered charge plasma-based dual-metal source TFET (DMS TFET) structure for an optimum performance of the device. The proposed TFET structure demonstrates superior performance than the conventional charge plasma TFETs in terms of ${I}_{{\scriptscriptstyle {\text {ON}}}}$ , ${I}_{{\scriptscriptstyle {\text {ON}}}}/{I}_{{\scriptscriptstyle {\text {OFF}}}}$ ratio, and subthreshold slope (SS). It provides ${I}_{{\scriptscriptstyle {\text {ON}}}}$ of $222~\mu \text{A}/\mu \text{m}$ , ${I}_{{\scriptscriptstyle {\text {ON}}}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $2.22\times 10^{{5}}$ , a minimum SS of 42.41 mV/decade, and an average SS of 54.15 mV/decade for three-decade increase in drain current (${I}_{\text {DS}}$). The performance of the device is observed at different channel lengths. Based on this analysis, a device design guideline for sub-10-nm channel length TFETs is presented in the paper. Finally, the circuit level metrics of the proposed structure are estimated by calculating delay and energy-delay product of a 45-stage inverter chain. [ABSTRACT FROM AUTHOR]

This paper investigates the fin-width ($\text{W}_{\textsf {Fin}}$) sensitivity of threshold voltage ($\text{V}_{\textsf {T}}$) for InGaAs and Si channel negative-capacitance FinFETs (NC-FinFETs) using a theoretically derived quantum subthreshold model corroborated with TCAD numerical simulation. Our study indicates that due to the action of negative capacitance, the NC-FinFET possesses smaller $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ than the FinFET counterpart. In addition, we point out and demonstrate that a device design with higher internal voltage amplification can be utilized to further reduce the $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ for NC-FinFETs. Our study may provide insights for future scaling of FinFETs. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel technique to overcome the conductance limitation in metal contacted single-walled carbon nanotubes (SWNTs)-based devices using metal nanoparticles (MNPs). Schottky barrier (SB) height at metal-SWNTs contact is believed to be the major contributor for this conductance limitation. Metal contacts with SWNTs are fabricated on a thermally grown SiO2/Si substrate using a conventional lithography process. The SWNTs are aligned between the metal electrodes using dielectrophoresis method. MNPs are introduced in the device using a small drop of MNP suspension to decorate the SWNTs. It is observed that the introduction of MNPs in the device reduces the SB height significantly. We found 0.34 eV reduction in SB height with silver (Ag) nanoparticles (NPs) and 0.15 eV with gold (Au) NPs. The proposed technique has improved the conductance in decorated SWNTs four times for Ag and Au NPs as compared to the bare SWNTs. Improvement in the conductance behavior of the SWNTs using MNPs enhances the sensitivity and switching speed of the devices, therefore, make it a promising alternative to silicon-based devices. [ABSTRACT FROM AUTHOR]

This paper presents the simulation-based comparison between silicon (Si) and silicon carbide (SiC) MOSFETs on the single-event burnout (SEB) performance for the first time. The safe operation areas (SOAs) regarding SEB are extracted and compared between the two structures when the heavy ions with a different linear energy transfer (LET) strike the sensitive areas of the devices. It is demonstrated that benefiting from the higher doped drift region, SiC MOSFET has a larger SEB threshold voltage than Si MOSFET at low LET range. However, it is the other way around at high LET range, which is attributed to the thicker epitaxy of Si MOSFET. The introduction of buffer layer to enhance the SEB hardness is also discussed. Results indicate that a thicker buffer layer is required for SiC MOSFET to enlarge the SOA, resulting in a more serious degradation of the specific ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$). Consequently, other hardening solutions need to be further explored to ensure the safe operation of SiC MOSFET in space applications. [ABSTRACT FROM AUTHOR]

The TCAD framework developed in part-I of this paper is used to study the impact of fin length (FL) and fin width (FW) scaling on interface trap generation ($\Delta \mathrm{V}_{\mathrm {IT}}$) during negative bias temperature instability (NBTI) in FinFETs. Structure and mechanical stress are obtained by Sentaurus process. Sentaurus device having capture-emission depassivation (CED) and multistate configuration (MSC) models are used for the trap kinetics. The mechanical strain and quantum confinement (QC) impacts are considered. The framework is validated using measured data from p-FinFETs having different FL and FW. The calibrated framework is used to estimate the impact of scaling on NBTI for 14-nm technology node and below. Different scenarios such as iso-stress bias ($\mathrm{V}_{\mathrm {GSTR}}$) versus iso-stress overdrive (OD), and devices having iso-workfunction (WF) or iso-off current ($\mathrm{I}_{ \mathrm{\scriptscriptstyle OFF}}$) are used for comparison. [ABSTRACT FROM AUTHOR]

In the domain of printed electronics (PE), field-effect transistors (FETs) with an oxide semiconductor channel are very promising. In particular, the use of high gate-capacitance of the composite solid polymer electrolytes (CSPEs) as a gate-insulator ensures extremely low voltage requirements. Besides high gate capacitance, such CSPEs are proven to be easily printable, stable in air over wide temperature ranges, and possess high ion conductivity. These CSPEs can be sensitive to moisture, especially for high surface-to-volume ratio printed thin films. In this paper, we provide a comprehensive experimental study on the effect of humidity on CSPE-gated single transistors. At the circuit level, the performance of ring oscillators (ROs) has been compared for various humidity conditions. The experimental results of the electrolyte-gated FETs (EGFETs) demonstrate rather comparable currents between 30%–90% humidity levels. However, the shifted transistor parameters lead to a significant performance change of the RO frequency behavior. The study in this paper shows the need of an impermeable encapsulation for the CSPE-gated FETs to ensure identical performance at all humidity conditions. [ABSTRACT FROM AUTHOR]

In prior researches, carbon nanotube (CNT)-based nano-random access-memory (NRAM) uses reset initialization which obtains >1011 high write endurance for large-time programmable (LTP) application. In this paper, for the first time, NRAM one-time programmable (OTP) application is proposed by using set initialization for data archive. Specifically, virgin NRAM cells are all in high resistance state (HRS) for storing bit “0.” In contrast, set initialization uses reversed polarity voltage to obtain low resistance state (LRS) for bit “1.” Furthermore, physical models of set initialization and retention current degradation are proposed for the first time. The current increment during set initialization can be attributed to electron tunneling and CNT deformation. Retention current degradation may be due to variation of paralleled CNT contacts in bottleneck zone. As for OTP performance, median NRAM bit and 1% tail bit demonstrate more than 1 billion years and 15 years data retentions, respectively, on 150 °C. The tail bit activation energy is 2.41 eV. Finally, no LRS read disturb is found after 10 s 0.5-V stress on both polarities. The virgin NRAM cells in HRS should be more stable than set initialized NRAM cells in LRS for both retention time and read disturb. [ABSTRACT FROM AUTHOR]

Because of the predicted shortage of fossil fuels in the future, public interest in utilizing solar energy for photovoltaic (PV) electricity has exponentially increased in recent years. In particular, interest in the building integration of PVs is growing worldwide, and the use of building-integrated PVs (BIPVs) is one of the fastest growing segments of the PV industry. Luminescent solar concentrators (LSCs) are one of the possible approaches for BIPVs. However, the high cost and poor stability of the dyes or quantum dots used in conventional LSCs prevent the widespread adoption of electricity generation through the LSC-based solar energy. Therefore, inorganic phosphors with long lifetime and photostability under ultraviolet (UV) excitation and moisture are favorable luminescent materials for LSCs. In this paper, thin-film LSCs using commercial inorganic phosphors are proposed. The thin-film LSCs with different inorganic phosphors were examined. The phosphor concentration and relative position of the thin phosphor layer were investigated to determine the suitable structure of a thin-film LSC. This paper aimed to achieve an understanding of thin-film LSCs by using inorganic phosphors and to provide useful guidelines for future commercialization. [ABSTRACT FROM AUTHOR]

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]

Integrated circuits operated in the near-threshold region exhibit specific merit with high energy efficiency. A near-threshold model is highly required for the circuit design. In this paper, a near-threshold drain current model is proposed based on the surface inversion layer charge model for analyzing digital circuits. The short-channel effect in deep submicrometer is also included in the model. Moreover, the delay and energy parts based on the near-threshold drain current model are derived and integrated in the model. Two process design kits (PDKs) are used for parameter extraction to demonstrate the feasibility of the proposed model. The results show that the proposed model can be used for the near-threshold circuit calculation, with the benefit of high accuracy. [ABSTRACT FROM AUTHOR]

This paper presents the GaxZn1−xO (x = 0, 0.1, and 0.3)-based photodetectors (PDs) by using mist atmospheric pressure chemical vapor deposition. X-ray diffraction and X-ray photoelectron spectroscopy are used to characterize crystal orientation, chemical qualitative, and quantitative characteristics of the GaxZn1−x (x = 0, 0.1, and 0.3) thin films. The photoluminescence is used to observe the near-band-edge emission and trap energy level. Among these three PDs, the Ga0.3Zn0.7O-based PD shows the lowest dark current, smallest noise current, and shortest response time. Furthermore, the Ga0.3Zn0.7O-based PD exhibits higher UV-B to UV-A rejection ratio and higher UV-B to visible rejection ratio. It is found that the cutoff wavelength is tunable by changing Ga contents in GaxZn1−x thin films. [ABSTRACT FROM AUTHOR]

Modeling of the packaged wind sensor operating on constant power (CP) mode is proposed in this paper. The proposed model is based on the theory of heat conduction and forced convection. The presented model indicates that the total output dc voltage is proportional to the square root of the wind speed, and ${V}_{x}$ , as well as ${V}_{y}$ , varies with the wind direction based on cosine function. The wind sensor is fabricated by microelectromechanical systems (MEMS) technology and packaged with the glue. The test is performed in the wind tunnel and the measured results indicate an agreement with the presented model. The relative error of voltage for the wind speed is less than 14% up to 30 m/s, while that for the wind direction is no more than 10.7% from 0° to 360°. [ABSTRACT FROM AUTHOR]

InGaAs FinFETs are challenged by relatively high leakage current in the OFF state. This originates from band-to-band tunneling (BTBT) at the drain end of the channel that is amplified by a parasitic bipolar effect (PBE) as a result of its floating body. In this paper, we present a simple model of the PBE in InGaAs FinFETs, which captures the key gate length and fin width dependences. Our model accounts for surface recombination at the sidewalls of the fin as well as bulk recombination at the heavily doped source. When compared with experimental results, our model suggests that fin sidewall recombination dominates in long gate length transistors and leads to an exponential gate length dependence of the current gain on the parasitic bipolar junction transistor (BJT). The model enables the extraction of the carrier diffusion length which exhibits the predicted fin width dependence. For short gate length transistors, source recombination is shown to dominate and the parasitic bipolar gain scales with the inverse of the gate length. [ABSTRACT FROM AUTHOR]

This paper investigates the advantages and disadvantages of bonding pad over active area (BPOA) layout over a conventional layout for lateral AlGaN/GaN HEMTs designed for use in power applications. Extensive analysis of the performance of a BPOA device, both experimentally and supported by 3-D TCAD model simulations, reveals that while it can offer a higher current capability per unit area, it can lead to other disadvantages compared to a conventional design when considering reliability aspects. [ABSTRACT FROM AUTHOR]

Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of $10~\mu \text{s}$ or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in “pseudo” charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect. [ABSTRACT FROM AUTHOR]

Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to have a variety of measurement approaches, including methods familiar to the electron-device and microwave communities that can aid in fully understanding the behavior of ferroelectrics in FeFETs and NCFETs. In this paper, we propose and show the viability of using frequency-domain electrical measurement techniques employing the well-known microwave S-parameters, and their large-signal generalization and X-parameters. Our methods provide the means to trace the intrinsic polarization versus electric-field curve of the ferroelectric, i.e., with the parasitics de-embedded, thereby showing the innate ferroelectric response, which cannot be done using conventional techniques. These methods also enable extraction of all the parameters of the Landau–Khalatnikov equation, which is commonly used to model ferroelectric behavior in FeFETs and NCFETs. This paper hence takes a useful step toward methods familiar to the electron-device community that can help to better understand and optimize FeFET and NCFET technologies. [ABSTRACT FROM AUTHOR]

Silicon carbide (4H-SiC) devices experiencing avalanche conditions can reach temperatures above 1500 K. Simulation of impact ionization in devices should, therefore, include models valid up to such high temperatures. However, calibrations of impact ionization coefficients are available only up to 580 K, and simulations of switching show deviations from measurements at higher temperatures. In this paper, a more accurate model based on the underlying physics of high temperature and anisotropic avalanche generation is proposed. This model enables calibrations performed at room temperature along the ${c}$ -axis to be more precisely extrapolated to any temperature of interest in 2-D device simulations. The model provides an excellent fit to the measurements of breakdown voltages during unclamped inductive switching tests of power MOSFETs, enabling a more accurate prediction of ruggedness. The more comprehensive physics included in the model makes it also applicable to other wide bandgap semiconductors such as GaN, diamond, and Ga2O3, which also exhibit a high critical electric field. [ABSTRACT FROM AUTHOR]

In this paper, we show that MoS2 multilayers have mechanical and electrical properties that qualify them as promising channel materials for an n-type piezoelectric FET (PZ-FET). We present extensive density functional theory calculations to investigate the effects of a compressive, out-of-plane stress on MoS2 monolayers and multilayers and extract the corresponding stiffness, as well as the sensitivity to stress of the conduction and valence band edge, and of the effective masses. Then, we use these material properties and a top-of-the-barrier ballistic transistor model to evaluate numerically the ${I}_{\textsf {DS}}$ versus ${V}_{\textsf {G}}$ characteristics of n-type PZ-FETs with an MoS2 channel material. Our results indicate that MoS2 multilayers are the best material option for n-type PZ-FETs, which can reach a subthreshold swing of about 40 mV/decade for a 5-nm-thick piezoelectric layer. This is because the weak interlayer van der Waals bonding makes the conduction band edge in MoS2 multilayers very sensitive to vertical compressive stress. The simulated MoS2 PZ-FETs exhibit large ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratios at low voltage and have better subthreshold steepness compared with the counterpart device employing a 3-D semiconductor. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

Recently, exploiting emerging nonvolatile memories to implement the process-in-memory (PIM) paradigm have shown great potential to address the von Neumann bottleneck and have attracted extensive research and development. In this paper, we present a novel PIM platform—spintronic processing unit (SPU), within spin transfer toque magnetic random access memory (STT-MRAM). This energy-efficient and reconfigurable PIM platform can perform different tasks—data storage and logic computing—using the same physical fabric that is programmable at the finest grain, i.e., the individual memory cell level, without the need to move data outside the memory fabric. The proposed SPU works just like a typical memory and all the logic functions are achieved through regularmemory-like write and read operations with minimal modifications. The functionality and performance are evaluated via hybrid circuit simulations under the 40-nm process technology node. Our proposed SPU is expected to be a feasible PIM platform in the near future, owing to the increasing maturity of STT-MRAM. [ABSTRACT FROM AUTHOR]

In this paper, we propose and simulate a novel drain-engineered structure of a quadruple-gate tunnel field-effect transistor (TFET). The proposed device employs a lateral dual source with a vertical drain extension on top of T-shaped channel region. This enables the modification of screening length ($\lambda $) by varying the silicon film (${t}_{\textsf {Si},\textsf {v}}$) and the oxide (${t}_{\textsf {Si},\textsf {v}}$) thicknesses at the channel–drain junction to overcome the limitations of high ambipolar leakage in the conventional double-gate TFET (DG-TFET). A 2-D calibrated simulation study has revealed the doubling of on-current (${I}_{ \mathrm{\scriptscriptstyle ON}}$) and significantly suppressed ambipolar leakage (${I}_{\textsf {AMB}}$) in the proposed device as compared to the conventional DG-TFET. Furthermore, a five orders of magnitude improvement in ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , 73% increase in transconductance (${g}_{\textsf {m}}$), 62% increase in cutoff frequency (${f}_{\textsf {T}}$), 72% increase in gain-bandwidth product, and 54% improvement in fall propagation delay (${t}_{\textsf {pHL}}$) are achieved in the proposed device. [ABSTRACT FROM AUTHOR]

In this paper, we develop an accurate analytical electrostatic potential model for both the n-type and p-type double-gate heterostructure tunnel field-effect transistors (H-TFETs). We solve the Poisson’s equation in four distinct regions inside the device, the depletion regions of the source, channel, and drain, and the drift-diffusion region of the channel, where the mobile charge carriers should be taken into account. It is shown that the model predicts the electrostatic potential profile of the various heterostructure devices with different material systems in all regions of the device operation accurately. The potential model is used for developing a model for the tunneling distance at the given energy level. Due to the physical nature of the models, the influence of the transistor parameters on the electrostatic characteristics of H-TFETs with desired heterojunction materials may be easily pursued. We show that the model results accurately predict the numerical simulation results for different device parameters. [ABSTRACT FROM AUTHOR]

This paper investigates the issues of oxygen accumulation and variation in the high-resistance state of HfO2-based resistive random access memory (RRAM), with improvement attained by inserting a thin oxygen-vacancy-rich layer of indium-tin-oxide (ITO) film. By acting as the oxygen ion reservoir, this ITO thin film on the TiN electrode can further stabilize resistance switching (RS) characteristics. In terms of reliability, ac endurance, and retention tests confirm stable RS characteristics for the Pt/HfO2/ITO/TiN device. Finally, a conducting model was proposed to explain the influence of the ITO thin layer and clarify the physical mechanism of electrical improvements. [ABSTRACT FROM AUTHOR]

In this paper, uniformly doped drift region of silicon carbide (SiC) super-junction (SJ) MOSFET is replaced with vertical variable doping profile (VVD) to achieve a better tradeoff between breakdown voltage (BV) and specific ON-resistance (${R}_{\text {sp,on}}$). While it is known that the SJ device consists of two vertical columns of n- and p-type, SJ VVD feature lies in increasing the doping concentration from top to bottom in the N-column and vice-versa in the P-column within the drift region. The proposed SJ VVD allows $\text {R}_{{\text {sp, on}}}$ to reduce further due to increased average doping concentration in conducting N-column and BV to increase further due to shifting of an electric field from corners to the center of the drift region. BV and ${R}_{\text {sp,on}}$ improved by 10% in an SJ VVD MOSFET and these parameters follow linear relationship similar to SJ MOSFET. The 2-D numerical simulations from Synopsys TCAD are used for investigating the static and dynamic characteristics of the device. In addition to 30% improvement in Baliga figure of merit, 35% improvement is obtained over SJ MOSFET in turn on and turn off switching energies for a clamped inductive circuit at 1200 V–20 A. Improved dynamic characteristics of SJ VVD can be attributed to reduction in gate charge (${Q}_{g}$) and miller capacitance (${c}_{\text {rss}}$) compared to SJ MOSFET. [ABSTRACT FROM AUTHOR]

This paper extends Johnson’s classical theory [Johnson, Proc. IRE 43, 684 (1955)] for the threshold of backward-wave oscillation (BWO) in a traveling-wave tube by considering the effects of: 1) small random variations of the circuit phase velocity along the tube axis and 2) end reflections. We find that both the BWO threshold and BWO frequency are minimally affected by random variations of the phase velocity, but we find that the oscillation threshold depends sensitively on the magnitude and phase of the composite reflection coefficients. [ABSTRACT FROM AUTHOR]

This paper presents a low-temperature process to transfer devices on ultrathin silicon layers from a parent substrate to a foreign substrate or stack. MOS devices were fabricated on silicon-on-insulator (SOI) wafer. The device wafer was then temporarily bonded on a carrier wafer. The handle layer was etched and the remaining ultrathin silicon device layer of ~1.4 $\mu \text{m}$ was transferred to a foreign substrate using permanent bonding. Here, we explored two different bonding approaches, namely, 1) the gold–indium (Au–In) transient liquid phase (TLP) bonding and 2) the epoxy bonding. We demonstrate the advantages of epoxy bonding method over the TLP method. The unique characteristic of this epoxy bonding approach is its capability to vertically stack multiple thin silicon layers. Furthermore, we demonstrate three-layer stacking of the ultrathin silicon layers with functional metal–oxide–semiconductor field-effect transistors in each layer. Electrical characterization results of nMOS/pMOS devices in each layer is presented and compared for before and after transfer. Changes in measured device performance before and after stacking are studied using simulations. The maximum process temperature in this approach is 150 °C, which is considerably lower than those reported in the literature. This result demonstrates the feasibility of multilayer low-temperature stacking. [ABSTRACT FROM AUTHOR]