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In this article, an analytical thermal conductivity model considering the degradation caused by the different phonon scattering mechanisms is presented for studying the self-heating effects (SHEs) in ultrathin body and buried oxide (UTBB) silicon-on-insulator (SOI) MOSFETs. By allowing for phonon-boundary and phonon–electron scattering, as well as tuning the surface roughness, the model enables accurate predictions for silicon films of different thicknesses over a wide temperature range. In order to apply the temperature-dependent self-built thermal conductivity model to the technology computer-aided design (TCAD) electrothermal simulation, a piecewise fitting, and equivalent strategy is developed by using the zero points (ZPs) and extreme points (EPs) of the first- and second-order discrete differentials of the model. The results show that the modified model is closer to the experimental data from literature studies than the default TCAD model in predicting the thermal conductivity distribution of the SOI-structure. Furthermore, the TCAD simulation results with our modified model show the same trend as that with its default model in predicting the performance degradation of UTBB SOI devices due to SHEs, such as the degradation of carrier mobility in the channel and the increase of subthreshold swing (SS). [ABSTRACT FROM AUTHOR]

This study simulates and compares symmetric and asymmetric MoS2 nanosheet transistor structures. The results show that the asymmetric MoS2 nanosheet transistor achieves higher current density and better gate control, and thus, this structure is optimized to meet the current density requirement for low-power applications in the International Roadmap for Devices and Systems (IRDS). Dielectric materials of Al2O3 and HfO2 are investigated, and equivalent oxide thicknesses ranging from 0.8 to 2 nm are analyzed. Transistors with Al2O3 as the dielectric exhibit better performance than those with HfO2 due to the lower level of remote phonon scattering. The gate length and underlap region are scaled down from 14 to 5 nm and from 7 to 1 nm, respectively, in an attempt to further enhance the ON-current. The substoichiometric metal oxide AlOx is used to induce more electrons in the undoped MoS2 channel. AlOx increases the ON-current with no gate control degradation. After optimization, the transistor demonstrates a subthreshold swing of 62.3 mV/dec, a drain-induced barrier lowering (DIBL) of 21.6 mV/dec, and a current density of $495 ~\mu \text{A}/\mu \text{m}$ with a supply voltage of 0.65 V. Compared with Si gate-all-around transistors, the MoS2 nanosheet transistor exhibits excellent gate control, good electrostatics, and comparable current density. [ABSTRACT FROM AUTHOR]

InGaZnO thin-film transistors (IGZO TFTs) adopting p-type Si with different doping concentrations as the gate electrodes are fabricated to study the effects of the electrical coupling between the gate electrode and the gate dielectric on the carrier mobility in the IGZO channel. In general, the carrier mobility is found to increase with increasing gate doping concentration because more holes in the gate electrode can screen/suppress the remote phonon scattering of the gate dielectric on the channel electrons (the screening effect). However, for certain gate doping concentrations, the carrier mobility surprisingly shows a decrease instead (the anti-screening effect). This has three implications: 1) like the free electrons in the n-Si gate electrode of OTFT, the holes in the p-Si gate electrode can oscillate about the dopant ions; 2) when the oscillation frequency is close/equal to the atomic vibration frequency of the high- ${k}$ gate dielectric, the resulting resonance between the gate electrode and the gate dielectric can enhance the atomic vibration of the latter to increase the remote phonon scattering on the channel carriers of the IGZO TFTs; and 3) the anti-screening effect could occur in any MOS-based devices. [ABSTRACT FROM AUTHOR]

In this study, the inversion layer mobility characteristics in Si-face 4H silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with nitrided and phosphorus-doped gate oxides were compared using Hall effect measurements. The inversion layer mobility was evaluated by applying a body bias and changing the temperature. The carrier scattering properties were determined for elevated temperatures (i.e., 473 K), at which point the impact of Coulomb scattering decreases and that of phonon scattering increases. The phonon-limited mobility of these MOSFETs was almost the same when plotted as a function of the effective normal electric field in the inversion layer, possibly representing the nature of the thermally grown SiO2/SiC interface. On the basis of this finding, the effect of phonon scattering was separated from the inversion layer mobility. The MOSFETs exhibited a remarkable difference in Coulomb scattering: the MOSFETs with phosphorus-doped gate oxide exhibited a more rapid increase in Coulomb-limited mobility with increasing surface carrier density than did the MOSFETs with nitride gate oxide. This resulted from the effective suppression of Coulomb scattering in the inversion layer, which is one of the reasons why phosphorus-doped gate oxide achieves higher inversion layer mobility than nitrided gate oxide. These results show that the inversion layer mobility of SiC MOSFETs can be modeled using a conventional framework of phonon, Coulomb, and surface roughness scattering. Therefore, the suppression of Coulomb scattering is key to further improving the inversion layer mobility of SiC MOSFETs. [ABSTRACT FROM AUTHOR]

The effects of the Si-substrate doping concentration on electrical characteristics of back-gate (BG) and top-gate (TG) MoS2 field-effect transistors (FETs) are investigated. The experimental results show that MoS2 FETs fabricated on different-concentration Si substrates using the same processing have similar interface characteristics and surface roughness of gate dielectric but exhibit different carrier mobility, and the higher the doping concentration, the higher the carrier mobility. This is because the carriers in Si substrate can screen the phonon scattering from the low-energy surface optical phonon produced by the soft Hf-O bonds in HfO2 dielectric, which will couple with the carriers in MoS2 channel, resulting in the reduction of the mobility, and the higher the Si-substrate concentration, the better the screening effect. Also, it is found that the BG dielectric scattering will impact on the mobility of the TG transistor, which causes a similar change trend of carrier mobility to that of the BG MoS2 FET as the Si-substrate concentration increases. Therefore, it can be revealed that the Si-substrate concentration has an important influence on the carrier mobility of MoS2 FETs, and the high Si-substrate concentration is beneficial for fabricating high-performance BG and TG MoS2 FETs. [ABSTRACT FROM AUTHOR]

With the development of separation and sorting techniques, highly enriched semiconducting single-walled carbon nanotubes (SWNTs) have become widely accessible, which has led to the rapid growth of high-performance solution-processed SWNT-based thin-film field-effect transistors (TFTs) showing capabilities comparable to the ideal single-SWNT FETs. With such improvements, theoretical studies and detailed analyses of these networks have become necessary. In this work, a model justifying the near-ideal electrical transport in SWNT networks is presented. The field-dependent resistive properties of the networks are calculated using a numerical solver based on the derived individual resistances of SWNTs and the intertube couplings. The model is capable of simulating mixed SWNT networks consisting of both metallic and semiconducting nanotubes of varying chiralities. Our analysis reveals that the high electrical currents in networks could be largely attributed to the suppression of phonon scattering and strong intertube couplings in highly dense SWNT networks (>30–40 SWNTs μm2). Comparisons between the simulated and experimental results indicate good agreement thereby demonstrating the accuracy of the proposed model. [ABSTRACT FROM AUTHOR]

This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron–phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simulation predictions reveal that a very noticeable effect of the HITR of Si/M0 at front end of line (FEOL) and back end of line (BEOL) interface (FEOL/BEOL) is that the hot-spot location is shifted into the channel away from drain depletion region, which affects the device SHE and degrades device performance. The impact of nanosheet width (WNSH) and sheets stacking number (N) on device SHE and drive current degradation with and without HITR effect are also studied. It is revealed that wider nanosheets with lower HITR can be a better device design choice for heat mitigation in high performance logic transistors. [ABSTRACT FROM AUTHOR]

In this article, an analytical thermal conductivity model for confined nanochannel in gate-all-around silicon nanowire field-effect transistors (GAA SiNW FETs) is developed by considering the limitations caused by the cross section and length. A geometry dependence of phonon mean free path (MFP) is established for quantitatively analyzing the influence of cross-sectional dimension. Furthermore, the length-induced degradation mechanism is revealed by employing the transverse transportation phonon effective MFP. The results calculated by the model which was verified by published data indicate that the thermal conductivity of confined nanochannel in the GAA SiNW FETs is suffering from a severe degradation compared to that of ultrathin silicon in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. In addition to the suppression caused by the cross-sectional boundaries, the impact of the channel length should be taken into consideration during the modeling of thermal conductivity for accurately evaluating the self-heating effects (SHEs) in GAA SiNW FETs. [ABSTRACT FROM AUTHOR]

We propose two different designs of p-type piezoelectric (PE) FinFETs (PE-FinFETs) covering low-power (LP) and high-performance (HP) operation modes. LP mode PE-FinFETs achieve a lower OFF-current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) and HP mode PE-FinFETs result in a larger ON-current (${I}_{ \mathrm{\scriptscriptstyle ON}}$). These two different modes are achieved by simply changing the outer PE-gates bias. The advanced nonequilibrium Green’s function (NEGF) approach self-consistent with six-band ${k}\cdot {p}$ method including phonon scattering is used to investigate the device performance. The gate voltage-controlled strain is analytically derived from the principle of PE effect. The HP and LP PE-FinFETs are studied, respectively, and the impacts of channel material, device orientation, and phonon scattering on both HP and LP PE-FinFETs are comprehensively investigated. The simulation results show that Ge is superior to Si for both LP and HP PE-FinFETs. With a supply voltage of 0.5 V, ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ of Ge LP mode PE-FinFETs is reduced by 18 times, and Ge HP mode PE-FinFETs obtain 50% ON-current enhancement. ${I}_{ \mathrm{\scriptscriptstyle ON}}$ (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) is unchanged for LP (HP) mode PE-FinFETs. Phonon scattering not only causes a large ${I}_{ \mathrm{\scriptscriptstyle ON}}$ degradation but also changes the optimal device orientation for both Si and Ge HP mode PE-FinFETs compared to their counterparts without phonon scattering. [ABSTRACT FROM AUTHOR]

In this paper, the effect of electron–phonon scattering on the negative differential resistance of graphene nanoribbon p-n junctions is investigated. The results show that the optical phonon scattering, due to inelasticity, significantly increases the valley current such that the peak-to-valley ratio decreases several orders of magnitude compared to ballistic approximation. It also shifts up the valley voltage. The former effect manifests itself more in structures with a smaller band gap and better ballistic characteristics. We show that it remains remarkable in different lengths of the transition region and severely affects the performance of the device. The results also show that phonon scattering plays a significant role even in ultrascaled nanodevices. [ABSTRACT FROM AUTHOR]

We study the noncoherent transport due to electron–phonon (e-ph) interaction in graphene nanoribbon (GNR) field-effect transistors (GNRFETs) using nonequilibrium Green’s function method in mode space. Phonon dispersion calculations in conjunction with the e-ph interaction computations show that in an armchair GNR, only a small number of phonon modes are coupled to the carriers. Our simulation shows that under a threshold gate voltage, the drain–source current is diminished by the low-energy phonons such as acoustic phonon modes and radial-breathing-like phonon modes, while at great biases of the gate, the current drop is essentially due to high-energy optical phonon modes. The effect of drain voltage on scattering process is discussed, which shows that at higher drain voltages, the ballisticity decreases. We also explore the phonon scattering dependence on the dimensions of GNRFET channel. In larger width ribbon, the impact of phonon scattering decreases. The channel with a length of 30 nm is ballistic up to 90%, and only when its length is increased to approximately 180 nm, transport becomes semiballistic, which infers to an effective mean free path of ~200 nm. [ABSTRACT FROM AUTHOR]

A new nonballistic analytical model for the intrinsic channel region of MOSFET-like single-walled carbon-nanotube FETs (CNTFETs) with ohmic contacts has been developed which overcomes the limitations of existing models and extends their applicability toward high bias voltages needed for analog applications. The new model comprises an improved description of the electron–phonon scattering mechanism, considering the accumulation of electrons at the bottom of conduction subband due to back scattering by optical phonons. The model has been justified by a Boltzmann transport equation solver. The simulation results are found to be in agreement with the experimental data for highly doped CNTFETs. [ABSTRACT FROM PUBLISHER]

In this paper, we report, for the first time, that surface roughness scattering is not necessarily the dominant scattering mechanism in the high-normal-field region of Ge nMOSFETs. This statement is quite different from the well-recognized situation in Si MOSFETs. In Ge(100), phonon scattering is dominant in the high-field region. Thus, it is difficult to increase the high-normal-field mobility in Ge(100) nMOSFETs by controlling the interface roughness. In contrast, because Ge(111) and Ge(110) are free of intervalley phonon scattering, the high-field mobility in Ge(111) and Ge(110) nMOSFETs could be enhanced by the Ge interface engineering. Furthermore, different from that in Si nMOSFETs, mobility limited by surface roughness scattering in Ge nMOSFETs shows a strong temperature dependence due to the valley occupancy change of electrons. The results in this paper should facilitate efforts to increase the high-normal-field mobility in Ge nMOSFETs. [ABSTRACT FROM AUTHOR]

Electron transport in Si double-gate junctionless transistors (JLTs) is simulated on the basis of the multisubband Monte Carlo method, considering acoustic phonons, intervalley phonons, ionized impurities (IIs), and surface roughness (SR) scattering. It is demonstrated that JLTs can actually minimize the mobility degradation caused by SR scattering and improve the current drivability. On the other hand, II scattering is confirmed to degrade the current drivability compared with conventional MOSFETs with an intrinsic channel. However, the performance degradation in JLTs due to II scattering is shown to be insignificant, owing to the screening effect of free carriers and the forward scattering properties of high-speed carriers. Furthermore, by extracting a backscattering coefficient, the screening effect and the forward scattering properties are shown to more mitigate II scattering as the gate voltage increases. [ABSTRACT FROM AUTHOR]

Hole mobility in strained ultrathin body InSb-on-insulator (InSb-OI) devices is calculated by a microscopic approach. The anisotropic valence band structures, in consideration of quantum confinement, are obtained via solving the six-band $k\cdot p$ Schrödinger and Poisson equations self-consistently. Hole mobility is calculated using the Kubo–Greenwood formula accounting for nonpolar acoustic and optical phonons, polar optical phonons, and surface roughness scatterings. The models are calibrated and verified with experimental data. The influences of body thickness and strain effect, including both biaxial and uniaxial strains, are investigated in InSb-OI devices. Our results indicate that mobility degradation occurs in both single-gate (SG) and double-gate (DG) mode when body thickness scales down below a certain range. Moreover, mobility in the DG mode outperforms that in the SG for thick body thickness, but loses its superiority over SG for extremely thin body. Compressive strain is favorable to hole mobility. Furthermore, more enhancement is achieved by uniaxial strain than biaxial strain. [ABSTRACT FROM AUTHOR]

An empirical model for the effective electron mobility in silicon nanowires (SiNWs) is presented. The model is based on published mobility data from numerical simulations of electron transport in SiNWs with different cross sections. Both phonon scattering and surface roughness scattering as well as the impact of the effective vertical field are considered. A comparison with a variety of experimental mobility data from the literature shows that the model can be treated as a reference for benchmarking different NW technologies. The effective field dependence is modeled by a simple expression making our mobility model very efficient for the use in numerical device simulators or in analytical MOSFET models. [ABSTRACT FROM AUTHOR]

The phonon-limited electron mobility in rectangular cross-sectional germanium (Ge) nanowires (NWs) with various orientations was theoretically investigated. The electronic states were calculated by a tight-binding model and the phononic states were calculated by a valence force field model. Then, transition probability was calculated by Fermi's golden rule, and Boltzmann's transport equation was solved for calculating low-field mobility. The electron mobility of Ge NWs strongly depends on the wire orientations and cross-sectional shapes, and this dependence can be explained by the conduction band structure of Ge NWs. Among several geometries investigated in this paper, $[110]$ -oriented NWs with wider width along [001]$ showed the highest electron mobility at low carrier concentration, and [112]$ NWs with wider width along showed the highest electron mobility at high carrier concentration. This result indicates that these kinds of Ge NWs are suitable as n-channel material. [ABSTRACT FROM AUTHOR]

We assess the analog/RF intrinsic performance of graphene FETs (GFETs) through a semiclassical transport model, including local and remote phonon scattering as well as band-to-band tunneling generation and recombination, validated by comparison with full quantum results over a wide range of bias voltages. We found that scaling is expected to improve the fT , and that scattering plays a role in reducing both the fT and the transconductance also in sub-100-nm GFETs. Moreover, we observed a strong degradation of the device performance due to the series resistances and source/drain to channel underlaps. [ABSTRACT FROM PUBLISHER]

The ultimate scaling limit of double-gate molybdenum disulfide (MoS2) field-effect transistors (FETs) with a monolayer thin body is examined and compared with ultrathin-body Si FETs by self-consistent quantum transport simulation in the presence of phonon scattering. Modeling of phonon scattering, quantum mechanical effects, and self-consistent electrostatics allows us to accurately assess the performance potential of monolayer MoS{2} FETs. The results revealed that monolayer MoS{2} FETs show 52% smaller drain-induced barrier lowering (DIBL) and 13% smaller subthreshold swing (SS) than 3-nm-thick-body Si FETs at a channel length of 10 nm with the same gating. With a requirement of DIBL <100~mV/V, the scaling limit of monolayer MoS{2} FETs is assessed to be 8 nm, comparing with 10 nm of the ultrathin-body Si counterparts due to the monolayer thin body and higher effective mass, which reduces direct source-to-drain tunneling. By comparing with the international technology roadmap for semiconductor (ITRS) target for high performance logic devices of 2023; double-gate monolayer MoS{2} FETs can fulfill the ITRS requirements. [ABSTRACT FROM AUTHOR]

In this paper, compact models of spin-relaxation lengths (SRLs) in copper and aluminum interconnects by incorporating contributions to spin relaxation from phonon-induced and defect-induced scatterings are developed. The proposed models have been exhaustively calibrated with experimental data from mesoscopic lateral spin valves. The compact models are used to predict the SRL in ultrascaled copper and aluminum interconnects with cross-sectional dimensions of only few hundreds of nm^2. Even though the SRL in bulk copper can be as large as 400 nm, it is predicted that SRL can become sub-100 nm for a 7.5-nm-wide channel in the presence of nominal size effects. It is found that the SRL in aluminum is more than that in copper for the same size effects and interconnect cross-sectional dimensions. The degradation in SRL in aluminum with size effects is slower than that in copper. Using the compact models for SRL in conjunction with spin-diffusion theory, spin injection and transport efficiency (SITE) for metallic interconnects in a conventional spin-valve configuration is quantified in the presence of phonon and defect scatterings. [ABSTRACT FROM PUBLISHER]

In this paper, we study the spin relaxation in bilayer armchair graphene nanoribbons (acGNRs) by employing the semiclassical Monte Carlo approach. D'yakonov–Perel relaxation due to structural inversion asymmetry (Rashba spin–orbit coupling) and Elliott–Yafet relaxation cause spin dephasing in bilayer GNRs. We investigate the spin relaxation in bilayer \alpha-, \beta-, and \gamma-acGNRs with varying their width and the temperature. We consider injection polarization along the z-direction, which is perpendicular to the plane of grapheme, and study the magnitude of ensemble-averaged spin variation along the x-direction which is the transport direction. To the best of our knowledge, there has been no Monte Carlo simulation performed on spin transport in acGNRs. We investigate the role of various scattering events in spin relaxation in bilayer acGNRs. We find that the spin relaxation length in the \alpha-acGNR is 6.5% higher than in \beta-acGNR and 10.8% higher than in \gamma-acGNR at 300 K. We also report the results of the variation of spin relaxation length with varying temperatures. We find that the spin relaxation length decreases by 9% in \alpha-acGNR, by 10.5% in \beta-acGNR, and 11% in \gamma-ac GNR at 300 K compared to 4 K. The decrease in spin relaxation length at the higher temperature is due to the increase in phonon and spin-flip scattering rates at the higher temperature. This theoretical investigation is particularly important to identify the factors responsible for the experimentally observed spin relaxation length in GNRs. [ABSTRACT FROM PUBLISHER]

This paper and the companion work present a full quantum study of the influence of interface traps on the I-V characteristics of InAs nanowire Tunnel-field effect transistors (FETs) and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on non equilibrium Green's function formalism, employing an 8\,\times\,8 \bf k\cdot\bf p Hamiltonian and accounting for phonon-scattering. In our model, traps can affect the I-V curves of the transistors both by modifying the device electrostatics and by directly participating the carrier transport. This paper investigates the impact of single trap on the I-V characteristics of Tunnel-FETs by varying the trap energy level, its volume and position, as well as the working temperature. Our 3-D self-consistent simulations show that: 1) even a single trap can deteriorate the inverse subthreshold slope of a nanowire InAs Tunnel-FET; 2) shallow traps have the largest impact on subthreshold slopes; and 3) the inelastic phonon-assisted tunneling through interface traps results in a temperature dependence of the otherwise temperature-independent Tunnel-FETs I-V characteristics. [ABSTRACT FROM AUTHOR]

We discuss the performances of (001) and (110) oriented gate-all-around silicon nanowire (Si NW) transistors within a nonequilibrium Green's functions framework, taking surface roughness and phonon scatterings into account. We show, in agreement with previous studies, that uniaxial tensile (respectively, compressive) strains can significantly improve the mobility of electrons (respectively, holes) in the channel. This does not, however, necessarily result in a comparable enhancement of the device performances. Indeed, the current in short channels is limited by both the scattering and the number of sub-bands available for carrier transport in quantum confined systems (intrinsic “ballistic” resistance). The dependence of the mobility and ballistic resistance on strains can be different, which calls for a careful design of the devices. We show, in this respect, that (110) Si NWs provide the best opportunities for strain engineering in ultimate short channel transistors. [ABSTRACT FROM AUTHOR]

This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band \bf k \cdot \bf p Hamiltonian within the nonequilibrium Green function formalism. Our model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the band structure. The effect of acoustic- and optical-phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in n-type InAs tunnel FETs induce a remarkable enhancement of Ion with a small degradation of the subthreshold slope, as well as large improvements in the Ioff versus Ion tradeoff for low Ioff and VDD values. Hence, an important widening of the range of Ioff and VDD values where tunnel FETs can compete with strained silicon MOSFETs is obtained. [ABSTRACT FROM AUTHOR]

Phonon-limited mobilities of electrons and holes in Si nanowires (NWs) with \langle \001\rangle, \langle \110\rangle, and \langle \111\rangle orientations are calculated in a fully atomistic framework for diameters up to 10 nm. Electron–phonon scattering rates are computed with an sp^3d^5s^\ast tight-binding model for electrons and a valence-force field model for phonons. The Boltzmann equation is then solved exactly for the low-field mobility. Compared to bulk Si, the electron mobilities are strongly reduced, but the hole mobilities can be enhanced in \langle \111\rangle and \langle \110\rangle NWs with diameters around 3.5 nm. The mobility, however, rapidly decreases with carrier concentration > \10^19\ \cm^-3. [ABSTRACT FROM PUBLISHER]

We have investigated the main scattering mechanisms affecting the mobility in graphene nanoribbons using detailed atomistic simulations. We have considered carrier scattering due to acoustic and optical phonons, edge roughness, single defects, and ionized impurities, and we have defined a methodology based on simulations of statistically meaningful ensembles of nanoribbon segments. Edge disorder heavily affects the mobility at room temperature in narrower nanoribbons, whereas charged impurities and phonons are hardly the limiting factors. Results are favorably compared with the few experiments available in the literature. [ABSTRACT FROM PUBLISHER]

We study the effect of surface roughness (SR) at the \Si/SiO2 interfaces on transport properties of quasi 1-D and 2-D silicon nanodevices by comparing the electrical performances of nanowire (NW) and double-gate (DG) field-effect transistors. We address a full-quantum analysis based on the 3-D self-consistent solution of the Poisson–Schrödinger equation within the coupled mode-space nonequilibrium Green function (NEGF) formalism. The influence of SR scattering is also compared with phonon (PH) scattering addressed in the self-consistent Born approximation. We analyze transfer characteristics, current spectra, density of states, and low-field mobility of devices with different lateral size, showing that the dimensionality of the quasi 1-D and 2-D structures induces significant differences only for thin silicon thicknesses. Thin NWs are found more sensitive to the SR-induced variability of the threshold voltage with respect to the DG planar transistors. [ABSTRACT FROM PUBLISHER]

A comprehensive study, which is presented in two parts, is performed to assess the radio-frequency (RF) performance potential of array-based carbon-nanotube field-effect transistors (CNFETs). In Part I, which is presented in this paper, the time-dependent Boltzmann transport equation is solved self-consistently with the Poisson equation to study the impact of nanotube phonon scattering on different aspects of intrinsic (single-tube, contact-independent) CNFET operation, including the attainable drive current and transconductance per tube, the intrinsic cutoff frequency, the intrinsic y-parameters, and the small-signal equivalent circuit for the intrinsic transistor. These intrinsic results are used to assess the tube-to-tube distance (pitch) that would be required in a multitube array-based structure to meet the drive current and transconductance requirements of the International Technology Roadmap for Semiconductors for the year 2015, which we use as a benchmark for CNFET technology going forward. In Part II of our paper, we elaborate on the results of Part I by adding the effects of extrinsic (contact-dependent) parasitics, thus providing an overall performance assessment of array-based structures. [ABSTRACT FROM AUTHOR]

Quantum confinement in nanoscale MOSFETs based on silicon-on-insulator FinFET architecture will affect the effectiveness of strain engineering. This is because energy valley splitting due to quantum confinement may weaken the strain effect. In this paper, we investigate this phenomenon by an in-house quantum transport simulator, Schrödinger equation Monte Carlo in three dimensions, which can provide the quantum transport simulation of nanoscale 3-D MOSFET geometries such FinFETs, as well as take various scattering processes into account. Our simulation results indicate that the strain effect is more significant for devices with a \langle\110\rangle channel orientation than those with a \langle\100\rangle channel orientation. In addition, we also found that the strain effect is more notable when the scattering effect is considered in the quantum transport simulation. This result indicates that the scattering of hot carriers still plays a role in the carrier transport and, thus, the drain current of the nanoscale MOSFETs. [ABSTRACT FROM AUTHOR]

Tunneling field-effect transistors (TFETs) have gained a great deal of interest recently due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been to achieve high drive currents, which is a prerequisite for high-performance operation. In this paper, we explore the performance potential of a 1-D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, as well as the carbon nanotube band structure as the model 1-D material system. We provide detailed insights into broken-gap TFET (BG-TFET) operation and show that it can, indeed, produce less than 60 mV/dec subthreshold swing at room temperature, even in the presence of electron–phonon scattering. The 1-D geometry is recognized to be uniquely favorable due to its superior electrostatic control, reduced carrier thermalization rate, and beneficial quantum confinement effects that reduce the off-state leakage below the thermionic limit. Because of higher source injection compared to staggered-gap and homojunction geometries, BG-TFET delivers superior performance that is comparable to MOSFET's. BG-TFET even exceeds the MOSFET performance at lower supply voltages (VDD), showing promise for low-power/high-performance applications. [ABSTRACT FROM PUBLISHER]

In this paper, we study the influence of elastic and inelastic phonon scattering on the drive current of Si MOSFETs under quasi-ballistic transport. Inelastic phonon emission involving energy relaxation helps achieve ballistic current, even in the presence of scattering, if the channel length is scaled down to the 10-nm scale. This result agrees with Natori's previous predictions. However, for longer channel devices, inelastic phonon emission degrades the drain current due to space charge effects caused by charge accumulation. We also demonstrate that source-end potential engineering to electrically reduce the bottleneck barrier length can result in a ballistic current even in longer channel devices. [ABSTRACT FROM AUTHOR]

effects of the nonequilibrium population of optical phonon (hot-phonon effect) and acoustic phonon (self-heating effect) on the dc performance of carbon nanotube (CNT) MOSFET are examined by solving coupled semiclassical electron and phonon transport equations. In this paper, the numerical solution of these coupled transport equations is described. Full-band electron and phonon Boltzmann transport equations are solved to simulate the electron and phonon transport. Electron-phonon scattering rates are calculated using the tight-binding approach and the phonon-phonon scattering by relaxation time approximation (optical phonon relaxation time extracted by fitting the measured data of metallic tube). We show that the dc ballisticity of a CNT MOSFET degrades by approximately 10% due to hot-phonon effects, which is a much smaller degradation compared to two-terminal measurement of metallic tubes. Self-heating of the tube is also examined and is found to be insignificant for a single-tube transistor. [ABSTRACT FROM AUTHOR]

We present a detailed treatment of dissipative quantum transport in carbon-nanotube field-effect transistors (CNTFETs) using the nonequilibrium Green's function formalism. The effect of phonon scattering on the device characteristics of CNTFETs is explored using extensive numerical simulation. Both intra- and intervalley scattering mediated by acoustic (AP), optical (OP), and radial-breathing-mode (RBM) phonons are treated. Realistic phonon dispersion calculations are performed using force-constant methods, and electron-phonon coupling is determined through microscopic theory. Specific simulation results are presented for (16,0), (19,0), and (22,0) zigzag CNTFETs, which are in the experimentally useful diameter range. We find that the effect of phonon scattering on device performance has a distinct bias dependence. Up to moderate gate biases, the influence of high-energy OP scattering is suppressed, and the device current is reduced due to elastic backscattering by AP and low-energy RBM phonons. At large gate biases, the current degradation is mainly due to high-energy OP scattering. The influence of both AP and high-energy OP scattering is reduced for larger diameter tubes. The effect of RBM mode, however, is nearly independent of the diameter for the tubes studied here. [ABSTRACT FROM AUTHOR]