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In recent years, 3-D GaN-based transistors have been intensively studied for their dramatically improved performance. However, thermal analysis of such devices is often oversimplified using the conventional Fourier's law in thermal simulations. In this aspect, accurate temperature predictions can be achieved by coupled phonon and electron Monte Carlo (MC) simulations that track the movement and scattering of individual phonons and electrons. Based on these MC simulations for the transistor region and the Fourier's law analysis for the rest of the chip, accurate electrothermal simulations are carried out on a nanowire-based GaN transistor to reveal the temperature rise in such devices. [ABSTRACT FROM AUTHOR]

The phonon-limited electron mobility in rectangular cross-sectional germanium (Ge) nanowires (NWs) with various orientations was theoretically investigated. The electronic states were calculated by a tight-binding model and the phononic states were calculated by a valence force field model. Then, transition probability was calculated by Fermi's golden rule, and Boltzmann's transport equation was solved for calculating low-field mobility. The electron mobility of Ge NWs strongly depends on the wire orientations and cross-sectional shapes, and this dependence can be explained by the conduction band structure of Ge NWs. Among several geometries investigated in this paper, $[110]$ -oriented NWs with wider width along [001]$ showed the highest electron mobility at low carrier concentration, and [112]$ NWs with wider width along showed the highest electron mobility at high carrier concentration. This result indicates that these kinds of Ge NWs are suitable as n-channel material. [ABSTRACT FROM AUTHOR]

This paper extends the analysis of the companion paper by presenting a comparative analysis of the impact of interface traps on the I-V characteristics of InAs nanowire tunnel FETs or MOSFETs with a spatially random distribution of traps. The physical mechanisms behind the effects of traps in either tunnel FETs or MOSFETs are compared and, furthermore, traps are also investigated as a possible source of device variability. Our results show that, in MOSFETs, an aggressive oxide thickness scaling can effectively counteract the degradation of the subthreshold slope (SS) possibly produced by interface traps. Tunnel FETs are instead more vulnerable to traps, which are probably the main hindrance to the experimental realization of tunnel FETs with an SS better than 60 mV/decade. [ABSTRACT FROM AUTHOR]

This paper and the companion work present a full quantum study of the influence of interface traps on the I-V characteristics of InAs nanowire Tunnel-field effect transistors (FETs) and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on non equilibrium Green's function formalism, employing an 8\,\times\,8 \bf k\cdot\bf p Hamiltonian and accounting for phonon-scattering. In our model, traps can affect the I-V curves of the transistors both by modifying the device electrostatics and by directly participating the carrier transport. This paper investigates the impact of single trap on the I-V characteristics of Tunnel-FETs by varying the trap energy level, its volume and position, as well as the working temperature. Our 3-D self-consistent simulations show that: 1) even a single trap can deteriorate the inverse subthreshold slope of a nanowire InAs Tunnel-FET; 2) shallow traps have the largest impact on subthreshold slopes; and 3) the inelastic phonon-assisted tunneling through interface traps results in a temperature dependence of the otherwise temperature-independent Tunnel-FETs I-V characteristics. [ABSTRACT FROM AUTHOR]

We discuss the performances of (001) and (110) oriented gate-all-around silicon nanowire (Si NW) transistors within a nonequilibrium Green's functions framework, taking surface roughness and phonon scatterings into account. We show, in agreement with previous studies, that uniaxial tensile (respectively, compressive) strains can significantly improve the mobility of electrons (respectively, holes) in the channel. This does not, however, necessarily result in a comparable enhancement of the device performances. Indeed, the current in short channels is limited by both the scattering and the number of sub-bands available for carrier transport in quantum confined systems (intrinsic “ballistic” resistance). The dependence of the mobility and ballistic resistance on strains can be different, which calls for a careful design of the devices. We show, in this respect, that (110) Si NWs provide the best opportunities for strain engineering in ultimate short channel transistors. [ABSTRACT FROM AUTHOR]

This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band \bf k \cdot \bf p Hamiltonian within the nonequilibrium Green function formalism. Our model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the band structure. The effect of acoustic- and optical-phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in n-type InAs tunnel FETs induce a remarkable enhancement of Ion with a small degradation of the subthreshold slope, as well as large improvements in the Ioff versus Ion tradeoff for low Ioff and VDD values. Hence, an important widening of the range of Ioff and VDD values where tunnel FETs can compete with strained silicon MOSFETs is obtained. [ABSTRACT FROM AUTHOR]

In this paper, we review and extend recent work on the effect of random discrete dopants on the statistical variability in gate-all-around silicon nanowire transistors. The electron transport is described using the nonequilibrium Green's function formalism. Full 3-D real-space and coupled-mode-space representations are used. Two different cross sections (i.e., \2.2 \times \2.2 and \4.2 \times \4.2\ \nm^2) and two different channel lengths (i.e., 6 and 12 nm) have been considered. The resistivity associated with discrete dopants can be estimated from the averaged current–voltage characteristics. The threshold-voltage variability and the subthreshold-slope variability are reduced greatly in the transistors with longer channel length. Both are smaller at equivalent channel lengths in the \2.2 \times \2.2\ \nm^2 device due to better electrostatic integrity. At the same time, the on-state-current variability associated with the varying resistance of the access regions is virtually independent of the channel length. However, it is reduced greatly in the \4.2 \times \4.2\ \nm^2 transistor due to a fourfold increase in the number of dopants in the access regions and corresponding self-averaging effects. Finally, we present results for the smallest transistor combining two sources of variability (i.e., discrete random dopants and surface roughness) and phonon scattering. [ABSTRACT FROM PUBLISHER]

We study the effect of surface roughness (SR) at the \Si/SiO2 interfaces on transport properties of quasi 1-D and 2-D silicon nanodevices by comparing the electrical performances of nanowire (NW) and double-gate (DG) field-effect transistors. We address a full-quantum analysis based on the 3-D self-consistent solution of the Poisson–Schrödinger equation within the coupled mode-space nonequilibrium Green function (NEGF) formalism. The influence of SR scattering is also compared with phonon (PH) scattering addressed in the self-consistent Born approximation. We analyze transfer characteristics, current spectra, density of states, and low-field mobility of devices with different lateral size, showing that the dimensionality of the quasi 1-D and 2-D structures induces significant differences only for thin silicon thicknesses. Thin NWs are found more sensitive to the SR-induced variability of the threshold voltage with respect to the DG planar transistors. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate quasi-ballistic transport in nanowire field-effect transistors (NW-FETs). In order to do so, we address the 1-D Boltzmann transport equation (BTE) and find its exact analytical solution for any potential profile with the constraint of dominant elastic scattering. A simulation code implementing a self-consistent Schrödinger-Poisson solver in the transverse direction and the present BTE solution in the longitudinal direction is worked out, providing the I-V characteristics of the NW-FET. Such characteristics are compared with those computed using a numerical BTE solver accounting for both inelastic and elastic collisions, and the two of them turn out to agree very nicely. From this comparison, it may be concluded that inelastic scattering plays a minor role for small-diameter FETs with device lengths in the decananometer range. Next, a methodology for the calculation of the transmission and backscattering coefficients is worked out for the first time starting from the scattering probabilities. The aforementioned coefficients turn out to be functions of the ratio between the carrier transit time and a suitably averaged momentum-relaxation time. Therefore, one of the main conclusions of this paper is that, so long as inelastic collisions are negligible, the so-called kT layer plays no role in 1-D quasi-ballistic carrier transport. [ABSTRACT FROM AUTHOR]

Using physics-based circuit models, the performances of carbon nanotube (CNT) interconnects, both single- and multiwall (SWNT and MWNT), are benchmarked against their copper counterparts at a realistic operating temperature (100 °C). The models used capture various electron phonon scattering mechanisms and the dependence of quantum conductance on temperature and diameter. It is demonstrated that any performance comparison between CNT and copper wires needs to be done at realistic temperatures because changes in temperature affect copper and CNT interconnects quite differently. The results of this paper demonstrate that a hybrid system of copper/SWNT/MWNT offers the highest performance enhancement for interconnects. [ABSTRACT FROM AUTHOR]