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In this article, an analytical thermal conductivity model considering the degradation caused by the different phonon scattering mechanisms is presented for studying the self-heating effects (SHEs) in ultrathin body and buried oxide (UTBB) silicon-on-insulator (SOI) MOSFETs. By allowing for phonon-boundary and phonon–electron scattering, as well as tuning the surface roughness, the model enables accurate predictions for silicon films of different thicknesses over a wide temperature range. In order to apply the temperature-dependent self-built thermal conductivity model to the technology computer-aided design (TCAD) electrothermal simulation, a piecewise fitting, and equivalent strategy is developed by using the zero points (ZPs) and extreme points (EPs) of the first- and second-order discrete differentials of the model. The results show that the modified model is closer to the experimental data from literature studies than the default TCAD model in predicting the thermal conductivity distribution of the SOI-structure. Furthermore, the TCAD simulation results with our modified model show the same trend as that with its default model in predicting the performance degradation of UTBB SOI devices due to SHEs, such as the degradation of carrier mobility in the channel and the increase of subthreshold swing (SS). [ABSTRACT FROM AUTHOR]

This study simulates and compares symmetric and asymmetric MoS2 nanosheet transistor structures. The results show that the asymmetric MoS2 nanosheet transistor achieves higher current density and better gate control, and thus, this structure is optimized to meet the current density requirement for low-power applications in the International Roadmap for Devices and Systems (IRDS). Dielectric materials of Al2O3 and HfO2 are investigated, and equivalent oxide thicknesses ranging from 0.8 to 2 nm are analyzed. Transistors with Al2O3 as the dielectric exhibit better performance than those with HfO2 due to the lower level of remote phonon scattering. The gate length and underlap region are scaled down from 14 to 5 nm and from 7 to 1 nm, respectively, in an attempt to further enhance the ON-current. The substoichiometric metal oxide AlOx is used to induce more electrons in the undoped MoS2 channel. AlOx increases the ON-current with no gate control degradation. After optimization, the transistor demonstrates a subthreshold swing of 62.3 mV/dec, a drain-induced barrier lowering (DIBL) of 21.6 mV/dec, and a current density of $495 ~\mu \text{A}/\mu \text{m}$ with a supply voltage of 0.65 V. Compared with Si gate-all-around transistors, the MoS2 nanosheet transistor exhibits excellent gate control, good electrostatics, and comparable current density. [ABSTRACT FROM AUTHOR]

In this study, the inversion layer mobility characteristics in Si-face 4H silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with nitrided and phosphorus-doped gate oxides were compared using Hall effect measurements. The inversion layer mobility was evaluated by applying a body bias and changing the temperature. The carrier scattering properties were determined for elevated temperatures (i.e., 473 K), at which point the impact of Coulomb scattering decreases and that of phonon scattering increases. The phonon-limited mobility of these MOSFETs was almost the same when plotted as a function of the effective normal electric field in the inversion layer, possibly representing the nature of the thermally grown SiO2/SiC interface. On the basis of this finding, the effect of phonon scattering was separated from the inversion layer mobility. The MOSFETs exhibited a remarkable difference in Coulomb scattering: the MOSFETs with phosphorus-doped gate oxide exhibited a more rapid increase in Coulomb-limited mobility with increasing surface carrier density than did the MOSFETs with nitride gate oxide. This resulted from the effective suppression of Coulomb scattering in the inversion layer, which is one of the reasons why phosphorus-doped gate oxide achieves higher inversion layer mobility than nitrided gate oxide. These results show that the inversion layer mobility of SiC MOSFETs can be modeled using a conventional framework of phonon, Coulomb, and surface roughness scattering. Therefore, the suppression of Coulomb scattering is key to further improving the inversion layer mobility of SiC MOSFETs. [ABSTRACT FROM AUTHOR]

We report the characterization of the channel mobility properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) on the heterogeneous β-Ga2O3-on-SiC (GaOSiC) substrate fabricated by an ion-cutting process. The mobility of GaOSiC MOSFETs is significantly improved as the postannealing temperature of Ga2O3 channel increases from 900 °C to 1200 °C. The GaOSiC transistor annealed at 1200 °C exhibits mobility consistent with the β-Ga2O3 donor wafer, which suggests that the defects in Ga2O3 channel induced by the H+ implantation for the ion-cutting step can be eliminated by the high-temperature annealing. As the ambient temperature (Tamb) increases from 0 °C to 150 °C, the mobility within the accumulation regime of GaOSiC MOSFETs decreases with the temperature following a Tamb−1 law, which is limited by the phonon scattering. The results of this work will be critically important for designing the transport properties of the GaOSiC channel, significantly advancing the development of Ga2O3 power devices on high thermal conductivity substrate. [ABSTRACT FROM AUTHOR]

In this article, an analytical thermal conductivity model for confined nanochannel in gate-all-around silicon nanowire field-effect transistors (GAA SiNW FETs) is developed by considering the limitations caused by the cross section and length. A geometry dependence of phonon mean free path (MFP) is established for quantitatively analyzing the influence of cross-sectional dimension. Furthermore, the length-induced degradation mechanism is revealed by employing the transverse transportation phonon effective MFP. The results calculated by the model which was verified by published data indicate that the thermal conductivity of confined nanochannel in the GAA SiNW FETs is suffering from a severe degradation compared to that of ultrathin silicon in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. In addition to the suppression caused by the cross-sectional boundaries, the impact of the channel length should be taken into consideration during the modeling of thermal conductivity for accurately evaluating the self-heating effects (SHEs) in GAA SiNW FETs. [ABSTRACT FROM AUTHOR]

In the past couple of years, GaN-based vertical FETs have been explored to complement their potential logic applicability along with its well-known advantages in high-power and RF applications. In this article, the performances of short-channel gate-all-around (GAA) GaN vertical nanowire MOSFETs, fabricated for a possible low-voltage logic application, have been investigated via simulation, assuming the multilevel trapping effects at the gate interface and the self-heating effects. The simulation results reveal that shallow traps at the interface increase the OFF-state current, the subthreshold swing, and the drain-induced barrier lowering, while deep traps at the interface lower the ON-state current and cause the threshold voltage instability. When the gate voltage is higher than the flat-band voltage of the nanowire channel in the saturation region of operation, the mobility degradation, related to the self-heating, becomes significant due to the increased incorporation of the optical phonon scattering. [ABSTRACT FROM AUTHOR]

A new nonballistic analytical model for the intrinsic channel region of MOSFET-like single-walled carbon-nanotube FETs (CNTFETs) with ohmic contacts has been developed which overcomes the limitations of existing models and extends their applicability toward high bias voltages needed for analog applications. The new model comprises an improved description of the electron–phonon scattering mechanism, considering the accumulation of electrons at the bottom of conduction subband due to back scattering by optical phonons. The model has been justified by a Boltzmann transport equation solver. The simulation results are found to be in agreement with the experimental data for highly doped CNTFETs. [ABSTRACT FROM PUBLISHER]

An empirical model for the effective electron mobility in silicon nanowires (SiNWs) is presented. The model is based on published mobility data from numerical simulations of electron transport in SiNWs with different cross sections. Both phonon scattering and surface roughness scattering as well as the impact of the effective vertical field are considered. A comparison with a variety of experimental mobility data from the literature shows that the model can be treated as a reference for benchmarking different NW technologies. The effective field dependence is modeled by a simple expression making our mobility model very efficient for the use in numerical device simulators or in analytical MOSFET models. [ABSTRACT FROM AUTHOR]

This paper investigates electrothermal aspects of high-k material as well as silicon-on-insulator (SoI) technology in the nanoscale nMOSFET by the numerical simulation of dual-phase-lag (DPL) heat conduction model under the effect of self-heating phenomenon. Three types of MOS devices including bulk, SoI, and high-k MOSFETs are considered. All of the electrothermal parameters are considered temperature-dependent, and three solution schemes including drift-diffusion (DD), hydrodynamic models, and the Monte Carlo method are compared. Consequently, the DPL-DD model is detected suitable to model the device with 100-nm gate length and \({\rm Kn}=3\) . The reason lies in low computational cost and high ability of the DPL–DD model to combine the advantages of the DPL-based thermal equation with the semiconductor equations to model the nanoscale phonon transport in the transistor. The temperature-jump boundary condition is applied on all boundaries to consider the boundary phonon scattering phenomenon. The output characteristics along with the temperature field are presented, and the effect of using high-k material on the electrothermal behavior of the transistor has been investigated. It is found that by changing the high-k gate dielectric material, the hotspot temperature decreases, and consequently, the thermal performance of the device increases. [ABSTRACT FROM PUBLISHER]

We discuss the performances of (001) and (110) oriented gate-all-around silicon nanowire (Si NW) transistors within a nonequilibrium Green's functions framework, taking surface roughness and phonon scatterings into account. We show, in agreement with previous studies, that uniaxial tensile (respectively, compressive) strains can significantly improve the mobility of electrons (respectively, holes) in the channel. This does not, however, necessarily result in a comparable enhancement of the device performances. Indeed, the current in short channels is limited by both the scattering and the number of sub-bands available for carrier transport in quantum confined systems (intrinsic “ballistic” resistance). The dependence of the mobility and ballistic resistance on strains can be different, which calls for a careful design of the devices. We show, in this respect, that (110) Si NWs provide the best opportunities for strain engineering in ultimate short channel transistors. [ABSTRACT FROM AUTHOR]

This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band \bf k \cdot \bf p Hamiltonian within the nonequilibrium Green function formalism. Our model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the band structure. The effect of acoustic- and optical-phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in n-type InAs tunnel FETs induce a remarkable enhancement of Ion with a small degradation of the subthreshold slope, as well as large improvements in the Ioff versus Ion tradeoff for low Ioff and VDD values. Hence, an important widening of the range of Ioff and VDD values where tunnel FETs can compete with strained silicon MOSFETs is obtained. [ABSTRACT FROM AUTHOR]

Quantum confinement in nanoscale MOSFETs based on silicon-on-insulator FinFET architecture will affect the effectiveness of strain engineering. This is because energy valley splitting due to quantum confinement may weaken the strain effect. In this paper, we investigate this phenomenon by an in-house quantum transport simulator, Schrödinger equation Monte Carlo in three dimensions, which can provide the quantum transport simulation of nanoscale 3-D MOSFET geometries such FinFETs, as well as take various scattering processes into account. Our simulation results indicate that the strain effect is more significant for devices with a \langle\110\rangle channel orientation than those with a \langle\100\rangle channel orientation. In addition, we also found that the strain effect is more notable when the scattering effect is considered in the quantum transport simulation. This result indicates that the scattering of hot carriers still plays a role in the carrier transport and, thus, the drain current of the nanoscale MOSFETs. [ABSTRACT FROM AUTHOR]

Tunneling field-effect transistors (TFETs) have gained a great deal of interest recently due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been to achieve high drive currents, which is a prerequisite for high-performance operation. In this paper, we explore the performance potential of a 1-D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, as well as the carbon nanotube band structure as the model 1-D material system. We provide detailed insights into broken-gap TFET (BG-TFET) operation and show that it can, indeed, produce less than 60 mV/dec subthreshold swing at room temperature, even in the presence of electron–phonon scattering. The 1-D geometry is recognized to be uniquely favorable due to its superior electrostatic control, reduced carrier thermalization rate, and beneficial quantum confinement effects that reduce the off-state leakage below the thermionic limit. Because of higher source injection compared to staggered-gap and homojunction geometries, BG-TFET delivers superior performance that is comparable to MOSFET's. BG-TFET even exceeds the MOSFET performance at lower supply voltages (VDD), showing promise for low-power/high-performance applications. [ABSTRACT FROM PUBLISHER]

This paper presents an extension of a ballistic compact model to the case of nonballistic transport for the conventional carbon nanotube FET featuring a MOSFET-like operation. A large part of the novelty lies on the analytical implementation of acoustic phonon (AP) and optical phonon (OP) scattering mechanism. To carry out this implementation, some simplifications of the theoretical description are proposed while staying as close as possible to physics and keeping the high-speed simulation and good convergence capability of the compact model. The compact model simulation results are systematically compared and validated with respect to nonequilibrium Green function simulation results. Then, we have investigated the impact of AP and OP scattering on transistor figures of merit. Taking into account the scattering processes is of utmost importance for both analog and digital circuit designs, since neglecting the scattering leads to an overestimation of more than 70% of the main figures of merit and will mislead designers when optimizing the operating point for analog applications. [ABSTRACT FROM AUTHOR]

In this paper, we present a detailed performance comparison between conventional n-i-n MOSFET transistors and tunneling field-effect transistors (TFETs) based on the p-i-n geometry, using semiconducting carbon nanotubes as the model channel material. Quantum-transport simulations are performed using the nonequilibrium Green's function formalism considering realistic phonon-scattering and band-to-band tunneling mechanisms. Simulations show that TFETs have a smaller quantum capacitance at most gate biases. Despite lower on-current, they can switch faster in a range of on/off-current ratios. Switching energy for TFETs is observed to be fundamentally smaller than that for MOSFETs, leading to lower dynamic power dissipation. Furthermore, the beneficial features of TFETs are retained with different bandgap materials. These reasons suggest that the p-i-n TFET is well suited for low-power applications. [ABSTRACT FROM AUTHOR]

Device-level simulation capabilities have been developed to investigate low-frequency noise behavior in p-type Si0.7Ge0.3/Si heterostructure MOS (SiGe p-HMOS) transistors. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation, a layer-dependent correlated mobility fluctuation, and a Hooge mobility fluctuation in the buried and parasitic surface channels, respectively. Simulations based on such models have been conducted for SiGe p-HMOS transistors, and the results have been carefully correlated with experimental data. Quantitative agreement has been obtained in terms of the noise level dependence on gate biases, drain currents, and body biases, revealing the important role of the dual channels in the low-frequency noise behavior of SiGe p-HMOS devices. [ABSTRACT FROM AUTHOR]

effects of the nonequilibrium population of optical phonon (hot-phonon effect) and acoustic phonon (self-heating effect) on the dc performance of carbon nanotube (CNT) MOSFET are examined by solving coupled semiclassical electron and phonon transport equations. In this paper, the numerical solution of these coupled transport equations is described. Full-band electron and phonon Boltzmann transport equations are solved to simulate the electron and phonon transport. Electron-phonon scattering rates are calculated using the tight-binding approach and the phonon-phonon scattering by relaxation time approximation (optical phonon relaxation time extracted by fitting the measured data of metallic tube). We show that the dc ballisticity of a CNT MOSFET degrades by approximately 10% due to hot-phonon effects, which is a much smaller degradation compared to two-terminal measurement of metallic tubes. Self-heating of the tube is also examined and is found to be insignificant for a single-tube transistor. [ABSTRACT FROM AUTHOR]

In this paper, we have extensively investigated the silicon thickness dependence of the low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single- and in double-gate mode. A physically based model including all the scattering mechanisms that are known to be most relevant in bulk MOSFETs has been extended and applied to SOI structures. A systematic comparison with the measurements shows that the experimental mobility dependence on the silicon thickness (T[subSI]) cannot be quantitatively explained within the transport picture that seems adequate for bulk transistors. In an attempt to improve the agreement with the experiments, we have critically rediscussed our model for the phonon scattering and developed a model for the scattering induced by the T[subSI] fluctuations. Our results suggest that the importance of the surface optical (SO) phonons could be significantly enhanced in UT-SOI MOSFETs with respect to bulk transistors. Furthermore, both the SO phonon and the T[subSI] fluctuation scattering are remarkably enhanced with reducing T[subSI], so that they could help explain the experimental mobility behavior. [ABSTRACT FROM AUTHOR]

This paper investigates the temperature dependence of phonon-scattering-limited mobility \muPH for advanced shortchannel strained pMOS devices. By using the split CV method and Matthiessen's rule, surface-roughness-limited mobility \muSR and \muPH are successfully decoupled. This paper indicates that the temperature sensitivity of \muPH is proportional to T^-1.75 for a neutral stressor and becomes higher when compressive strain is applied. It is explained by the higher optical phonon energy induced by uniaxially compressive strain. Our new findings may also explain the previously reported higher temperature sensitivity of drain current present in uniaxial strained pMOSFETs. [ABSTRACT FROM AUTHOR]