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This study simulates and compares symmetric and asymmetric MoS2 nanosheet transistor structures. The results show that the asymmetric MoS2 nanosheet transistor achieves higher current density and better gate control, and thus, this structure is optimized to meet the current density requirement for low-power applications in the International Roadmap for Devices and Systems (IRDS). Dielectric materials of Al2O3 and HfO2 are investigated, and equivalent oxide thicknesses ranging from 0.8 to 2 nm are analyzed. Transistors with Al2O3 as the dielectric exhibit better performance than those with HfO2 due to the lower level of remote phonon scattering. The gate length and underlap region are scaled down from 14 to 5 nm and from 7 to 1 nm, respectively, in an attempt to further enhance the ON-current. The substoichiometric metal oxide AlOx is used to induce more electrons in the undoped MoS2 channel. AlOx increases the ON-current with no gate control degradation. After optimization, the transistor demonstrates a subthreshold swing of 62.3 mV/dec, a drain-induced barrier lowering (DIBL) of 21.6 mV/dec, and a current density of $495 ~\mu \text{A}/\mu \text{m}$ with a supply voltage of 0.65 V. Compared with Si gate-all-around transistors, the MoS2 nanosheet transistor exhibits excellent gate control, good electrostatics, and comparable current density. [ABSTRACT FROM AUTHOR]

InGaZnO thin-film transistors (IGZO TFTs) adopting p-type Si with different doping concentrations as the gate electrodes are fabricated to study the effects of the electrical coupling between the gate electrode and the gate dielectric on the carrier mobility in the IGZO channel. In general, the carrier mobility is found to increase with increasing gate doping concentration because more holes in the gate electrode can screen/suppress the remote phonon scattering of the gate dielectric on the channel electrons (the screening effect). However, for certain gate doping concentrations, the carrier mobility surprisingly shows a decrease instead (the anti-screening effect). This has three implications: 1) like the free electrons in the n-Si gate electrode of OTFT, the holes in the p-Si gate electrode can oscillate about the dopant ions; 2) when the oscillation frequency is close/equal to the atomic vibration frequency of the high- ${k}$ gate dielectric, the resulting resonance between the gate electrode and the gate dielectric can enhance the atomic vibration of the latter to increase the remote phonon scattering on the channel carriers of the IGZO TFTs; and 3) the anti-screening effect could occur in any MOS-based devices. [ABSTRACT FROM AUTHOR]

In this study, the inversion layer mobility characteristics in Si-face 4H silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with nitrided and phosphorus-doped gate oxides were compared using Hall effect measurements. The inversion layer mobility was evaluated by applying a body bias and changing the temperature. The carrier scattering properties were determined for elevated temperatures (i.e., 473 K), at which point the impact of Coulomb scattering decreases and that of phonon scattering increases. The phonon-limited mobility of these MOSFETs was almost the same when plotted as a function of the effective normal electric field in the inversion layer, possibly representing the nature of the thermally grown SiO2/SiC interface. On the basis of this finding, the effect of phonon scattering was separated from the inversion layer mobility. The MOSFETs exhibited a remarkable difference in Coulomb scattering: the MOSFETs with phosphorus-doped gate oxide exhibited a more rapid increase in Coulomb-limited mobility with increasing surface carrier density than did the MOSFETs with nitride gate oxide. This resulted from the effective suppression of Coulomb scattering in the inversion layer, which is one of the reasons why phosphorus-doped gate oxide achieves higher inversion layer mobility than nitrided gate oxide. These results show that the inversion layer mobility of SiC MOSFETs can be modeled using a conventional framework of phonon, Coulomb, and surface roughness scattering. Therefore, the suppression of Coulomb scattering is key to further improving the inversion layer mobility of SiC MOSFETs. [ABSTRACT FROM AUTHOR]

In this article, we present a surface-potential-based approach to model the bias-dependent effective velocity observed in AlGaN/GaN high-electron-mobility transistors (HEMTs) due to optical phonon scattering. Our model precisely reproduces the progressive decrease in the saturation velocity in GaN HEMTs with increasing gate voltages, as reported in the literature, which is predominantly due to the scattering of electrons, forming the high-density two-dimensional electron gas (2DEG), by optical phonons at high overdrive voltages. We show that this dependence differs from the traditional mobility degradation models in terms of its impact on the device current–voltage (I – V) characteristics and illustrate how the inclusion of a velocity saturation model also provides the model users with an additional handle for parameter extraction. The model is explicit and, by virtue of its Simulation Program with Integrated Circuit Emphasis (SPICE) compatibility, is readily implemented in the industry-standard Advanced SPICE Model for HEMTs (ASM-HEMTs) model and has been validated against experimental dc I – V and RF S-parameter measurements of an in-house GaN device. [ABSTRACT FROM AUTHOR]

The effects of the Si-substrate doping concentration on electrical characteristics of back-gate (BG) and top-gate (TG) MoS2 field-effect transistors (FETs) are investigated. The experimental results show that MoS2 FETs fabricated on different-concentration Si substrates using the same processing have similar interface characteristics and surface roughness of gate dielectric but exhibit different carrier mobility, and the higher the doping concentration, the higher the carrier mobility. This is because the carriers in Si substrate can screen the phonon scattering from the low-energy surface optical phonon produced by the soft Hf-O bonds in HfO2 dielectric, which will couple with the carriers in MoS2 channel, resulting in the reduction of the mobility, and the higher the Si-substrate concentration, the better the screening effect. Also, it is found that the BG dielectric scattering will impact on the mobility of the TG transistor, which causes a similar change trend of carrier mobility to that of the BG MoS2 FET as the Si-substrate concentration increases. Therefore, it can be revealed that the Si-substrate concentration has an important influence on the carrier mobility of MoS2 FETs, and the high Si-substrate concentration is beneficial for fabricating high-performance BG and TG MoS2 FETs. [ABSTRACT FROM AUTHOR]

We report the characterization of the channel mobility properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) on the heterogeneous β-Ga2O3-on-SiC (GaOSiC) substrate fabricated by an ion-cutting process. The mobility of GaOSiC MOSFETs is significantly improved as the postannealing temperature of Ga2O3 channel increases from 900 °C to 1200 °C. The GaOSiC transistor annealed at 1200 °C exhibits mobility consistent with the β-Ga2O3 donor wafer, which suggests that the defects in Ga2O3 channel induced by the H+ implantation for the ion-cutting step can be eliminated by the high-temperature annealing. As the ambient temperature (Tamb) increases from 0 °C to 150 °C, the mobility within the accumulation regime of GaOSiC MOSFETs decreases with the temperature following a Tamb−1 law, which is limited by the phonon scattering. The results of this work will be critically important for designing the transport properties of the GaOSiC channel, significantly advancing the development of Ga2O3 power devices on high thermal conductivity substrate. [ABSTRACT FROM AUTHOR]

This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron–phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simulation predictions reveal that a very noticeable effect of the HITR of Si/M0 at front end of line (FEOL) and back end of line (BEOL) interface (FEOL/BEOL) is that the hot-spot location is shifted into the channel away from drain depletion region, which affects the device SHE and degrades device performance. The impact of nanosheet width (WNSH) and sheets stacking number (N) on device SHE and drive current degradation with and without HITR effect are also studied. It is revealed that wider nanosheets with lower HITR can be a better device design choice for heat mitigation in high performance logic transistors. [ABSTRACT FROM AUTHOR]

We have observed and analyzed the 1/ƒ1+α noise in transient leakage current through a metal–insulator–metal stacked high-k capacitor of TiN–ZrO2–TiO2–TiN. The ZrO2 and TiO2 films, formed by atomic layer deposition, are polycrystalline and show geometrical variety at interfaces (i.e., grain boundaries). Two types of transient leakage current are observed: 1) the monotonically decreasing component with power law dependence and 2) the uneven component having power law dependence. To analyze the uneven component in time domain, we assumed that the power law decay occurs due to a gradual change in the redistribution of electrons between interfaces of ZrO2–TiN and ZrO2–TiO2. The frequency-domain analysis shows that the 1/ƒ1+α noise comes from the transient leakage of direct tunneling and trap-assisted tunneling (α > 0). In particular, the noise in the uneven component, the random telegraph noise part ((α ~ 1), relates to local trap states in a grain boundary affected by phonon scattering. In addition, the analytical method we developed in this article shows an excellent agreement with various measurements of the transient gate leakage current. [ABSTRACT FROM AUTHOR]

This article reports on the extraction of the electron velocity as a function of gate bias from N-polar GaN deep recess high-electron-mobility transistors (HEMTs) designed for mm-wave power amplification. Bias-dependent small-signal S-parameter measurements are used to obtain small-signal equivalent circuit parameters, which are applied to a transit delay model. The model accounts for fringing capacitance to arrive at an electron velocity associated with the transit of the physical gate length. A peak electron velocity of 1.4 × 107 cm/s was obtained at a drain current of 700 mA/mm corresponding to a channel charge density of 0.3 × 1013 cm−2. At higher current, the velocity slowly decreased with the electron velocity crossing below 107 cm/s at 1.8 A/mm. This behavior was found to be in good agreement with a previously proposed model based on optical phonon scattering at the source injection point. An analysis of the delay components is used to provide guidance for the factors influencing the device performance. [ABSTRACT FROM AUTHOR]

In this article, we performed gated four-probe measurements on amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) to extract their intrinsic mobility and contact resistance as functions of gate voltage and temperature. The abnormal degradation of field-effect mobility was observed in a-IGZO TFTs both at high gate voltage and at high temperature. Results showed that contact resistance played a major role in mobility degradation at high gate bias, whereas band-like transport (phonon scattering) accounts for mobility degeneration at high temperature. We proposed a novel method, which exposed the contact regions to ultraviolet (UV) ozone. The mobility was boosted from 23 to 30 cm2/Vs, nearly 40% increment at high gate bias. [ABSTRACT FROM AUTHOR]

We propose two different designs of p-type piezoelectric (PE) FinFETs (PE-FinFETs) covering low-power (LP) and high-performance (HP) operation modes. LP mode PE-FinFETs achieve a lower OFF-current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) and HP mode PE-FinFETs result in a larger ON-current (${I}_{ \mathrm{\scriptscriptstyle ON}}$). These two different modes are achieved by simply changing the outer PE-gates bias. The advanced nonequilibrium Green’s function (NEGF) approach self-consistent with six-band ${k}\cdot {p}$ method including phonon scattering is used to investigate the device performance. The gate voltage-controlled strain is analytically derived from the principle of PE effect. The HP and LP PE-FinFETs are studied, respectively, and the impacts of channel material, device orientation, and phonon scattering on both HP and LP PE-FinFETs are comprehensively investigated. The simulation results show that Ge is superior to Si for both LP and HP PE-FinFETs. With a supply voltage of 0.5 V, ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ of Ge LP mode PE-FinFETs is reduced by 18 times, and Ge HP mode PE-FinFETs obtain 50% ON-current enhancement. ${I}_{ \mathrm{\scriptscriptstyle ON}}$ (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) is unchanged for LP (HP) mode PE-FinFETs. Phonon scattering not only causes a large ${I}_{ \mathrm{\scriptscriptstyle ON}}$ degradation but also changes the optimal device orientation for both Si and Ge HP mode PE-FinFETs compared to their counterparts without phonon scattering. [ABSTRACT FROM AUTHOR]

We study the noncoherent transport due to electron–phonon (e-ph) interaction in graphene nanoribbon (GNR) field-effect transistors (GNRFETs) using nonequilibrium Green’s function method in mode space. Phonon dispersion calculations in conjunction with the e-ph interaction computations show that in an armchair GNR, only a small number of phonon modes are coupled to the carriers. Our simulation shows that under a threshold gate voltage, the drain–source current is diminished by the low-energy phonons such as acoustic phonon modes and radial-breathing-like phonon modes, while at great biases of the gate, the current drop is essentially due to high-energy optical phonon modes. The effect of drain voltage on scattering process is discussed, which shows that at higher drain voltages, the ballisticity decreases. We also explore the phonon scattering dependence on the dimensions of GNRFET channel. In larger width ribbon, the impact of phonon scattering decreases. The channel with a length of 30 nm is ballistic up to 90%, and only when its length is increased to approximately 180 nm, transport becomes semiballistic, which infers to an effective mean free path of ~200 nm. [ABSTRACT FROM AUTHOR]

A new nonballistic analytical model for the intrinsic channel region of MOSFET-like single-walled carbon-nanotube FETs (CNTFETs) with ohmic contacts has been developed which overcomes the limitations of existing models and extends their applicability toward high bias voltages needed for analog applications. The new model comprises an improved description of the electron–phonon scattering mechanism, considering the accumulation of electrons at the bottom of conduction subband due to back scattering by optical phonons. The model has been justified by a Boltzmann transport equation solver. The simulation results are found to be in agreement with the experimental data for highly doped CNTFETs. [ABSTRACT FROM PUBLISHER]

Electron transport in Si double-gate junctionless transistors (JLTs) is simulated on the basis of the multisubband Monte Carlo method, considering acoustic phonons, intervalley phonons, ionized impurities (IIs), and surface roughness (SR) scattering. It is demonstrated that JLTs can actually minimize the mobility degradation caused by SR scattering and improve the current drivability. On the other hand, II scattering is confirmed to degrade the current drivability compared with conventional MOSFETs with an intrinsic channel. However, the performance degradation in JLTs due to II scattering is shown to be insignificant, owing to the screening effect of free carriers and the forward scattering properties of high-speed carriers. Furthermore, by extracting a backscattering coefficient, the screening effect and the forward scattering properties are shown to more mitigate II scattering as the gate voltage increases. [ABSTRACT FROM AUTHOR]

This paper investigates electrothermal aspects of high-k material as well as silicon-on-insulator (SoI) technology in the nanoscale nMOSFET by the numerical simulation of dual-phase-lag (DPL) heat conduction model under the effect of self-heating phenomenon. Three types of MOS devices including bulk, SoI, and high-k MOSFETs are considered. All of the electrothermal parameters are considered temperature-dependent, and three solution schemes including drift-diffusion (DD), hydrodynamic models, and the Monte Carlo method are compared. Consequently, the DPL-DD model is detected suitable to model the device with 100-nm gate length and \({\rm Kn}=3\) . The reason lies in low computational cost and high ability of the DPL–DD model to combine the advantages of the DPL-based thermal equation with the semiconductor equations to model the nanoscale phonon transport in the transistor. The temperature-jump boundary condition is applied on all boundaries to consider the boundary phonon scattering phenomenon. The output characteristics along with the temperature field are presented, and the effect of using high-k material on the electrothermal behavior of the transistor has been investigated. It is found that by changing the high-k gate dielectric material, the hotspot temperature decreases, and consequently, the thermal performance of the device increases. [ABSTRACT FROM PUBLISHER]

We assess the analog/RF intrinsic performance of graphene FETs (GFETs) through a semiclassical transport model, including local and remote phonon scattering as well as band-to-band tunneling generation and recombination, validated by comparison with full quantum results over a wide range of bias voltages. We found that scaling is expected to improve the fT , and that scattering plays a role in reducing both the fT and the transconductance also in sub-100-nm GFETs. Moreover, we observed a strong degradation of the device performance due to the series resistances and source/drain to channel underlaps. [ABSTRACT FROM PUBLISHER]

The ultimate scaling limit of double-gate molybdenum disulfide (MoS2) field-effect transistors (FETs) with a monolayer thin body is examined and compared with ultrathin-body Si FETs by self-consistent quantum transport simulation in the presence of phonon scattering. Modeling of phonon scattering, quantum mechanical effects, and self-consistent electrostatics allows us to accurately assess the performance potential of monolayer MoS{2} FETs. The results revealed that monolayer MoS{2} FETs show 52% smaller drain-induced barrier lowering (DIBL) and 13% smaller subthreshold swing (SS) than 3-nm-thick-body Si FETs at a channel length of 10 nm with the same gating. With a requirement of DIBL <100~mV/V, the scaling limit of monolayer MoS{2} FETs is assessed to be 8 nm, comparing with 10 nm of the ultrathin-body Si counterparts due to the monolayer thin body and higher effective mass, which reduces direct source-to-drain tunneling. By comparing with the international technology roadmap for semiconductor (ITRS) target for high performance logic devices of 2023; double-gate monolayer MoS{2} FETs can fulfill the ITRS requirements. [ABSTRACT FROM AUTHOR]

This paper extends the analysis of the companion paper by presenting a comparative analysis of the impact of interface traps on the I-V characteristics of InAs nanowire tunnel FETs or MOSFETs with a spatially random distribution of traps. The physical mechanisms behind the effects of traps in either tunnel FETs or MOSFETs are compared and, furthermore, traps are also investigated as a possible source of device variability. Our results show that, in MOSFETs, an aggressive oxide thickness scaling can effectively counteract the degradation of the subthreshold slope (SS) possibly produced by interface traps. Tunnel FETs are instead more vulnerable to traps, which are probably the main hindrance to the experimental realization of tunnel FETs with an SS better than 60 mV/decade. [ABSTRACT FROM AUTHOR]

We discuss the performances of (001) and (110) oriented gate-all-around silicon nanowire (Si NW) transistors within a nonequilibrium Green's functions framework, taking surface roughness and phonon scatterings into account. We show, in agreement with previous studies, that uniaxial tensile (respectively, compressive) strains can significantly improve the mobility of electrons (respectively, holes) in the channel. This does not, however, necessarily result in a comparable enhancement of the device performances. Indeed, the current in short channels is limited by both the scattering and the number of sub-bands available for carrier transport in quantum confined systems (intrinsic “ballistic” resistance). The dependence of the mobility and ballistic resistance on strains can be different, which calls for a careful design of the devices. We show, in this respect, that (110) Si NWs provide the best opportunities for strain engineering in ultimate short channel transistors. [ABSTRACT FROM AUTHOR]

This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band \bf k \cdot \bf p Hamiltonian within the nonequilibrium Green function formalism. Our model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the band structure. The effect of acoustic- and optical-phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in n-type InAs tunnel FETs induce a remarkable enhancement of Ion with a small degradation of the subthreshold slope, as well as large improvements in the Ioff versus Ion tradeoff for low Ioff and VDD values. Hence, an important widening of the range of Ioff and VDD values where tunnel FETs can compete with strained silicon MOSFETs is obtained. [ABSTRACT FROM AUTHOR]

Phonon-limited mobilities of electrons and holes in Si nanowires (NWs) with \langle \001\rangle, \langle \110\rangle, and \langle \111\rangle orientations are calculated in a fully atomistic framework for diameters up to 10 nm. Electron–phonon scattering rates are computed with an sp^3d^5s^\ast tight-binding model for electrons and a valence-force field model for phonons. The Boltzmann equation is then solved exactly for the low-field mobility. Compared to bulk Si, the electron mobilities are strongly reduced, but the hole mobilities can be enhanced in \langle \111\rangle and \langle \110\rangle NWs with diameters around 3.5 nm. The mobility, however, rapidly decreases with carrier concentration > \10^19\ \cm^-3. [ABSTRACT FROM PUBLISHER]

We study the effect of surface roughness (SR) at the \Si/SiO2 interfaces on transport properties of quasi 1-D and 2-D silicon nanodevices by comparing the electrical performances of nanowire (NW) and double-gate (DG) field-effect transistors. We address a full-quantum analysis based on the 3-D self-consistent solution of the Poisson–Schrödinger equation within the coupled mode-space nonequilibrium Green function (NEGF) formalism. The influence of SR scattering is also compared with phonon (PH) scattering addressed in the self-consistent Born approximation. We analyze transfer characteristics, current spectra, density of states, and low-field mobility of devices with different lateral size, showing that the dimensionality of the quasi 1-D and 2-D structures induces significant differences only for thin silicon thicknesses. Thin NWs are found more sensitive to the SR-induced variability of the threshold voltage with respect to the DG planar transistors. [ABSTRACT FROM PUBLISHER]

A comprehensive study, which is presented in two parts, is performed to assess the radio-frequency (RF) performance potential of array-based carbon-nanotube field-effect transistors (CNFETs). In Part I, which is presented in this paper, the time-dependent Boltzmann transport equation is solved self-consistently with the Poisson equation to study the impact of nanotube phonon scattering on different aspects of intrinsic (single-tube, contact-independent) CNFET operation, including the attainable drive current and transconductance per tube, the intrinsic cutoff frequency, the intrinsic y-parameters, and the small-signal equivalent circuit for the intrinsic transistor. These intrinsic results are used to assess the tube-to-tube distance (pitch) that would be required in a multitube array-based structure to meet the drive current and transconductance requirements of the International Technology Roadmap for Semiconductors for the year 2015, which we use as a benchmark for CNFET technology going forward. In Part II of our paper, we elaborate on the results of Part I by adding the effects of extrinsic (contact-dependent) parasitics, thus providing an overall performance assessment of array-based structures. [ABSTRACT FROM AUTHOR]

Quantum confinement in nanoscale MOSFETs based on silicon-on-insulator FinFET architecture will affect the effectiveness of strain engineering. This is because energy valley splitting due to quantum confinement may weaken the strain effect. In this paper, we investigate this phenomenon by an in-house quantum transport simulator, Schrödinger equation Monte Carlo in three dimensions, which can provide the quantum transport simulation of nanoscale 3-D MOSFET geometries such FinFETs, as well as take various scattering processes into account. Our simulation results indicate that the strain effect is more significant for devices with a \langle\110\rangle channel orientation than those with a \langle\100\rangle channel orientation. In addition, we also found that the strain effect is more notable when the scattering effect is considered in the quantum transport simulation. This result indicates that the scattering of hot carriers still plays a role in the carrier transport and, thus, the drain current of the nanoscale MOSFETs. [ABSTRACT FROM AUTHOR]

The performance prediction of double-walled carbon nanotube (DWCNT) array-built field-effect transistors (DWCNTFETs) is performed theoretically. The charge densities and surface potentials of double walls are solved in a self-consistent manner with the effects of wall screening among the DWCNT array treated appropriately. Some comparisons are made between our method and the nonequilibrium Green's function approach, with good agreement obtained. The influences of phonon scattering, doping resistances, Schottky barrier resistances, screening effects, and parasitic capacitances on DWCNTFET performance are examined in detail for different array geometries. It is found that, although its intrinsic channel part has no speed advantage over the single-walled counterpart, the overall speed performance can be better with low array densities and large diameters of the DWCNTs. The delay and cutoff frequency of the DWCNTFET can be decreased by 15% and increased by 30%, respectively. In particular, its better on current property can be utilized in the design of nanodevices with high-power-handling capability. [ABSTRACT FROM AUTHOR]