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Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Flexible, highly sensitive, easy fabricating process, low-cost pressure sensors are the trend for flexible electronic devices. Despite the tremendous progress in recent years, it is still challenging to prepare pressure sensors with high sensitivity, high stability, and fast responsiveness. In this study, we report a simple and low-cost method for the preparation of novel pressure sensors. Inspired by the pomegranate structure, a 3-D porous structure consisting of polystyrene (PS) microspheres filled with reduced graphene oxide (rGO) paper is proposed. This pressure sensor has high linear sensitivity (1.41 kPa−1 in the pressure range of 0–50 kPa), high stability (1000 cycles), and quick response time (~20 ms). Furthermore, a robotic arm interacting control system based on pressure sensor arrays is constructed, which demonstrates the far-reaching potential of pressure sensors in human–machine interaction. Therefore, this work provides a low-cost and effective method for preparing high linear sensitivity pressure sensors. [ABSTRACT FROM AUTHOR]

Technology computer-aided design (TCAD) is an integral part of the development process of semiconductor technologies and devices, a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resulting devices often have an intricate 3-D structure and contain various specifically designed materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (material properties, interfaces, defects, and so on), to nanometric (quantum confinement, non-bulk properties, tunneling, ballistic transport, and so on), to full-chip dimensions (strain, heat transport, and so on), and time scales from femtoseconds (scattering, ferroelectric switching time, and so on) to seconds (trapping times, degradation, and so on). Voltages, currents, and charges have been scaled to such low levels that statistical effects and process variations have a strong impact. Devices based on new materials (e.g., 2-D crystals) and physical principles (ferroelectrics, magnetic materials, qubits, and so on) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools, and are often too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead, a TCAD tool chain is required which can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles, and the ensuing large-scale simulations and that make use of artificial intelligence for well-chosen (sub)routines to decrease the overall simulation time. This Special Issue features six invited and 18 regular papers that address these problems. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

Presents the table of contents for this issue of the publication. [ABSTRACT FROM AUTHOR]

Over the past 10 years, 3-dimensional (3-D) wafer-level stacked backside Illuminated (BSI) CMOS image sensors (CISs) have undergone rapid progress in development and performance and are now in mass production. This review paper covers the key processes and technology components of 3-D integrated BSI devices, as well as results from early devices fabricated and tested in 2007 and 2008. This article is divided into three main sections. covers wafer-level bonding technology. covers the key wafer fabrication process modules for BSI 3-D wafer-level stacking. presents the device results. [ABSTRACT FROM AUTHOR]

The evolution of CMOS image sensors and their prospects using advanced imaging technologies are promising candidates to improve the quality of life. With the rapid advent of parallel analog-to-digital converters (ADCs) and back-illuminated (BI) technology, CMOS image sensors currently dominate the market for digital cameras, and stacked CMOS image sensors continue to provide enhanced functionality and user experience in mobile devices. This article reviews the latest achievements in stacked image sensors with respect to the evolution of image sensor architecture for accelerating performance improvements, extending sensing capabilities, and integrating edge computing with various stacked device technologies. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

Presents the table of contents for this issue of the publication. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

We have developed a bonded CMOS image sensor using a gallium oxide (Ga2O3)/polycrystalline selenium (c-Se)/nickel oxide photodiode and a Se–Se bonding process. These photodiodes can amplify the signal by avalanche amplification when a high electric field is applied, thus realizing a high-sensitivity image sensor. The Se–Se bonding process has many advantages, including the ability to handle high-temperature processing, no sputtering damage to the p-n junction interface, and no need for high-precision alignment. In this study, we have shown that the application of a high-temperature process to crystallize Ga2O3 improves the orientation of the c-Se, which is the photosensitive layer, and reduces the dark current. In addition, the Se–Se bonding process reduces the sputtering damage at the Ga2O3/c-Se interface, improving film quality. By applying the developed bonding process, we successfully realized a high-sensitivity CMOS image sensor with a threefold increase in magnification. [ABSTRACT FROM AUTHOR]

This article presents a low-power column-parallel $\Sigma \Delta $ analog-to-digital converter (ADC) with shared operational transconductance amplifiers (OTAs) for CMOS image sensors (CISs). Through the proposed time division multiplexing of OTAs, the power consumption of the modulator achieves a reduction of about 40%. The proposed structure alleviates the layout requirement of OTAs, enabling implementation of a high-resolution low-power image sensor in advanced CMOS technology nodes. As the coupled noise introduced by the proposed column-shared scheme is suppressed to a lower level than the inherent crosstalk of adjacent pixels, the proposed structure only contributes a negligible inter-column coupled noise from the ADCs. Moreover, a compact digital decimation filter with a single-bit-bit-wise-inversion (BWI) topology is also proposed, which can reduce chip area significantly. The prototype sensor is fabricated in a 40-nm standard CMOS technology with 256 $\times256$ pixel array and 256 proposed column-parallel $\Sigma \Delta $ ADCs. Each $\Sigma \Delta $ ADC occupies a core area of 4.5 $\mu \text{m}\,\,\times $ 310 $\mu \text{m}$ , while consuming a power of 58.8 $\mu \text{W}$. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.49/−0.65 LSB and +5.1/−4.8 LSB, respectively. Measurement results show a dynamic range of 79.9 dB and an effective-number-of-bit (ENOB) of 11.4 bit. This work achieves a figure of merit (FOM) of 97.2 fJ/step. [ABSTRACT FROM AUTHOR]

The quanta image sensor (QIS) is a photon-counting image sensor that has been implemented using different electron devices, including impact ionization-gain devices, such as the single-photon avalanche detectors (SPADs), and low-capacitance, high conversion-gain devices, such as modified CMOS image sensors (CIS) with deep subelectron read noise and/or low noise readout signal chains. This article primarily focuses on CIS QIS, but recent progress of both types is addressed. Signal processing progress, such as denoising, critical to improving apparent signal-to-noise ratio, is also reviewed as an enabling coinnovation. [ABSTRACT FROM AUTHOR]

Realization of laser-induced graphene (LIG) by ablating laser on several substrates, like polyamide (PI), has gained huge attention. Generally, a CO2 laser, with a 10.6- $\mu \text{m}$ wavelength, has been reported to form LIG. However, higher build area, the requirement of a higher power, limited LIG conductivity values, infrared wavelength, and cost are several drawbacks of the CO2 laser-based process. Herein, a 3-D printer, loaded with a low-power (2.8 W) blue (450 nm) laser diode, has been demonstrated to create such LIGs with higher conductivity on PI sheets. The LIGs, with varying conductivity values, have been fabricated by diversified laser parameters achieving maximum conductivity of 2572.19 S/m, which was more than seven times higher than the one achieved by a CO2 laser. Subsequently, such LIG was transferred to a lamination sheet, named T-LIG, using a laminator. Finally, T-LIG based microfluidic device was developed with a microchannel and three integrated electrodes for electrochemical detection of folic acid, achieving a limit of detection of $10 ~\mu \text{M}$. Similarly, a microfluidic fuel cell was developed using T-LIG which provided a maximum power density of $5.06 ~\mu \text{W}$ / cm2 with a maximum open-circuit voltage of 50 mV. Overall, such T-LIG-based microfluidic devices have huge potential for diverse applications. [ABSTRACT FROM AUTHOR]

The article discusses information related to submission of a manuscript, review process, and open access for the authors of the periodical.

A year has gone by since the publication, in December 2020, of my last editorial devoted to thanking our reviewers. Another year (hopefully, the last one) where the persisting COVID pandemic has restricted our possibility to interact with people and to operate in a normal environment. I am happy to remark that, despite this, the review process of the papers submitted to the IEEE Transactions on Electron Devices (TED) was again virtually unaffected, even in the presence of an increasing submission count. [ABSTRACT FROM AUTHOR]

After six years on the IEEE Transactions on Electron Devices (T-ED) Editorial Board, Prof. Siddharth Rajan, Ohio State University, Columbus, OH, USA (compound semiconductor devices) has stepped down from his Editor position. [ABSTRACT FROM AUTHOR]

It is my sincere pleasure and honor to introduce the eighth Special Issue of the IEEE Transactions on Electron Devices on Solid-State Image Sensors. Previous special issues were published in February 1976, August 1985, May 1991, October 1997, January 2003, November 2009, and January 2016. In the six years since the last Special Issue, solid-state image sensors have continued to demonstrate impressive performance improvements and developments in a diverse set of technology areas. The areas include process modules, wafer-level stacking, single-photon counting, ultra-wide dynamic range, alternate detector materials, time-of-flight 3-D imaging, and device simulation. Solid-state image sensors also achieved continued growth in existing markets such as camera phones, automotive cameras, security and industrial cameras and medical/scientific cameras. New applications and markets, such as the Internet-of-Things, 3-D imaging, artificial intelligence, augmented reality, biometrics, and others, are driving further growth and technology development. Solid-state image sensors are now key components in a vast array of consumer and industrial products. [ABSTRACT FROM AUTHOR]

This article discusses complementary FET (CFET)-based static random access memory (SRAM) to achieve next-generation bitcell area scaling and performance gain in advanced CMOS technology nodes. SRAM bitcell area reduction, lower SRAM parasitic resistance, and higher drive strength are mandatory to continue SRAM scaling with technology advancement. The CFET reduces the SRAM bitcell area by folding nMOS over pMOS and making SRAM cross-coupled connections in the middle end of line (MEOL). The compact bitcell offers large area scaling combined with lowering bitline and wordline resistance. Lower parasitic resistance improves SRAM write margin and performance. The CFET SRAM cell area, write margin, read margin, and performance are evaluated and compared with FinFET (FF)-based SRAM. The CFET 111 and 122 SRAM provides up to 43.75% and 35% area gain w.r.t. FF 111 and 122 SRAM, respectively. Moreover, the CFET 122 SRAM has 11% faster read operation than FF 122 SRAM, respectively. [ABSTRACT FROM AUTHOR]

The article offers information related to submission of a manuscripts, pre-submission editorial service, and submission procedure for the authors of the periodical.

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM AUTHOR]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM AUTHOR]