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A high-efficiency ${D}$ -band monolithically integrated GaN frequency doubler based on a pair of antiseries four-anode planar GaN Schottky barrier diodes (SBDs) has been successfully fabricated. Unlike the traditional hybrid integrated circuit technology, the monolithic integrated circuit technology has been used in the design and fabrication of GaN SBD-based frequency doubler circuits to achieve good alignment and low conversion losses. At room temperature, the experiments show that the peak conversion efficiency reaches 17.0% at 115.6 GHz under a continuous wave (CW) driving which is a critical requirement for many practical applications. The efficiency of 17.0% is the highest efficiency of GaN SBD-based multipliers at present under CW driving mode. This monolithically integrated doubler also exhibits a broadband high efficiency characteristic of more than 4.7% (−5.58 dB from 17%) across a 10% band from 109 to 121 GHz. In addition, high CW power handling capability of the proposed frequency doubler is verified. The experiments show that the frequency doubler can endure a maximum CW input power of 0.5 W. [ABSTRACT FROM AUTHOR]

The 6-in gate commutated thyristor (GCT) is suitable for hybrid dc circuit breaker (HDCB) application with its large chip area and high maximum controllable current (MCC), compared with traditional 4-in GCTs. P+ base doping dispersion control is of vital importance in the 6-in GCT chip. Based on the strong correlation between P+ base doping and the gate-cathode breakdown voltage (${V}_{\text {gbr}}$), P+ base doping dispersion is characterized through ${V}_{\text {gbr}}$. Test results show that ${V}_{\text {gbr}}$ dispersion in the 6-in GCT sample with etched depth of around $10~\mu \text{m}$ is about 2 V with the average ${V}_{\text {gbr}}$ of around 22 V. While ${V}_{\text {gbr}}$ dispersion in the sample with etched depth of above 20 $\mu \text{m}$ is above 6 V with the average ${V}_{\text {gbr}}$ of around 27 V. These are consistent with the 2-D simulation results. Then, P+ base doping parameter design is optimized through experiment. Both turn-on and turn-off characteristics of 6-in GCT samples with different P+ base doping parameter designs are compared with HDCB application. The final optimized 6-in GCT chip has no difficulty in turning on under a low dc-link voltage below 100 V and it can turn off 13 kA with the overvoltage of about 4.5 kV successfully, which shows potential in HDCB application. [ABSTRACT FROM AUTHOR]

Nanoelectromechanical (NEM) switches offer the advantages of zero OFF-state leakage current, abrupt switching characteristics, nonvolatile (NV) operation, and relatively low ON-state resistance as compared with CMOS transistors predominantly used for digital computing today. NEM switches can be implemented using metallic interconnect layers formed in the back-end-of-line (BEOL) steps of a standard CMOS IC manufacturing process, in order to enable compact implementation of hybrid CMOS-NEM circuits. In this article, a release-etch method is developed for realizing BEOL NV-NEM switches with $\leq 100$ -nm contact gaps. A functional array of BEOL NV-NEM switches is used to implement a hybrid CMOS-NEM IC for data search applications. NV-NEM switch design optimization to minimize the programming voltage and accelerate switching speed is discussed. A scaled NV-NEM technology is projected to be advantageous for high-speed, low-power reconfigurable computing applications. This projection is validated with experimental data for a BEOL NV-NEM switch implemented with a conventional 16-nm CMOS IC manufacturing process. [ABSTRACT FROM AUTHOR]