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The function of conductive particles on the insulator for a simple case is analyzed in this paper. In a certain insulator containing conductive particles, the electric dipoles in the conductive particles are induced by the external electric field, and the polarization orientation is along the direction of electric field. Macroscopically, the insulator containing conductive particles can be equivalent to a high-permittivity (εeff) insulator. Meanwhile, the maximum electric field (Emax) in the insulator containing conductive particles is enhanced. The εeff and Emax are determined not only by the geometric shape, size, and the packing modes of conductive particles. This paper presents several packing modes of conductive particles in the insulator. Simulation results indicate that when cubic conductive particles with side length 2R are stacked in the form of cubic close packing, the εeff and the Emax of the insulator containing conductive particles at R/d = 0.495 (d is the distance between the centers of the mass of closet conductive particles) are increased to 67.1 times and 97.5 times, respectively, compared with the insulator without conductive particles inside. [ABSTRACT FROM AUTHOR]

With lots of interest in negative capacitance field-effect transistors for ultralow-power complementary metal-oxide-semiconductor technology, negative capacitance thin-film transistors (NCTFTs) have also received much attention. Although previous studies on NCTFTs were done, the NC effect in organic-based TFTs was not studied yet. In this paper, P(VDF-TrFE) ferroelectric-gated P3HT semiconductor channel TFTs are experimentally demonstrated with solution-based fabrication process. Especially, this paper shed light on the NC effect in the organic based TFTs. The step-up current-voltage characteristics are repeatedly and reliably observed in diverse TFTs, and then, with the results, transconductance (gm) amplification implemented by the negative capacitance was delved. Moreover, with the aid of ferroelectric polarization switching, super steep-switching characteristic of the organic-based TFT was experimentally confirmed. These experimental results and discussion would be helpful in understanding NC effects in TFTs. [ABSTRACT FROM AUTHOR]

In this paper, we analyze the impact of length scaling on the ON-state operation of the two classes of double-gate negative capacitance transistors: metal–ferroelectric–metal–insulator–semiconductor (MFMIS) and metal–ferroelectric–insulator–semiconductor (MFIS). We show that for long-channel structures, MFMIS configuration shows a higher ON current than the MFIS due to a lower drain saturation voltage of the latter. For short-channel cases, we compare these negative capacitance field effect transistors (NCFETs) under two scenarios: equal flat band voltages (iso- ${V}_{\textsf {FB}}$) and equal OFF currents (iso- ${I}_{ \mathrm{\scriptscriptstyle OFF}}$). In iso- ${V}_{\textsf {FB}}$ condition, a higher negative differential conductance (NDC) effect in the MFMIS suppresses its ON current below that of the MFIS. However, the MFMIS provides a higher ON current than the MFIS for all the channel lengths under iso- ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ condition. We further investigate the influence of quantum mechanical effects and velocity saturation of carriers on the electrical characteristics of short-channel NCFETs. We also explore the impact of inner and outer spacer fringings in NCFETs. We find that the ferroelectric voltage gain in NCFETs with spacers increases with the channel length scaling, which provides a further improvement in the ON current contrary to those without spacers. Moreover, increase in the spacer permittivity also boosts both the ON current and the NDC. [ABSTRACT FROM AUTHOR]

In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation. [ABSTRACT FROM PUBLISHER]

Negative capacitance ferroelectric (FE) field-effect transistor (FeFET) is promising to address the issue of the increasing power density in digital circuit by realizing sub-60 mV/decade subthreshold swing. This inspires us to evaluate its applications in analog circuit. In this paper, the evaluation is performed based on the equivalent circuit model and through device- and circuit-level benchmarking against MOSFET counterpart. It is found that the selection of FE thickness is important to balance current amplification and saturated output characteristics. As compared with MOSFET, FeFET exhibits a larger current, transconductance, and current-to-transconductance generation efficiency. Its output resistance is smaller in the linear region and larger in the saturation region. It also has less variation in threshold voltage with temperature. When implementing FeFETs into various analog circuit applications, we find that a node capacitor could be discharged within shorter time to increase circuit speed; A better analog switch consisting of complementary FeFETs exhibits a lower and more linear on-resistance; Differential amplifier provides larger voltage amplification to small input signal; Current mirror transfers a more precise output current to the reference one. [ABSTRACT FROM PUBLISHER]

We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau–Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET. [ABSTRACT FROM PUBLISHER]

Ferroelectric field effect transistors (FeFETs) based on ferroelectric hafnium oxide (HfO2) thin films show high potential for future embedded nonvolatile memory applications. However, HfO2 films besides their recently discovered ferroelectric behavior are also prone to undesired charge trapping effects. Therefore, the scope of this paper is to verify the possibility of the charge trapping during standard operation of the HfO2-based FeFET memories. The kinetics of the charge trapping and its interplay with the ferroelectric polarization switching are analyzed in detail using the single-pulse ID – VG technique. Furthermore, the impact of the charge trapping on the important memory characteristics such as retention and endurance is investigated. [ABSTRACT FROM AUTHOR]

Ferroelectric tunnel junction (FTJ) is a promising low power nonvolatile memory for beyond-CMOS applications. In this paper, Co/BaTiO3/SrRuO3 FTJs are fabricated, simulated, and their electrical characteristics are measured by capacitance–voltage (${C}$ – ${V}$), current–voltage (${I}$ – ${V}$), and high-frequency S-parameter measurements. Ferroelectricity of the ultrathin BaTiO3 (~3.2 nm) film is first verified by a butterfly shaped hysteresis ${C}$ – ${V}$ profile, from which saturation polarizations are calculated in the ON state and OFF state as ${P}_{ \mathrm{ON}}=+ {20}\,\,\mu {C} / {\text{cm}}^{ {2}}$ and ${P}_{ \mathrm{OFF}}=- {25}\,\,\mu {C}/{\text{cm}}^{ {2}}$ , respectively. The numerical simulation of the FTJ device is performed using experimental electronic band parameters of the heterostructure. The device structure was optimized for ON/OFF ratio, ${I}_{ \mathrm{ON}} / {I}_{ \mathrm{OFF}}= {75}$ for a depolarization field, ${E}_{{dpol}} < { {10}}^{ {6}}~{V} / {\text{cm}}$. The calculated tunnel currents of $ {250}\,\,{nm}\times {250}\,\,{nm}$ FTJ in ON state (${I}_{ \mathrm{ON}}= {250}\times {250}^{- {250}}\,\,{A}$) and OFF state (${I}_{{OFF}}={{1.75}\times {250}}^{{-9}}\,\,{A}$) match with experimental values. From the S-parameters of RF measurements, the high-frequency small-signal device model of the FTJ in ON state (${C}_{ \mathrm{ON}}= {250}\,\,{fF},{R}_{ \mathrm{ON}}={0.8}\,\,{M}\Omega$) and OFF state (${C}_{ \mathrm{OFF}}={ {250}}\,\,{fF},{R}_{ \mathrm{OFF}}= {250}\,\,{M}\Omega$) is developed for a frequency range from 50 MHz to 5 GHz. The extracted capacitor model of Co/BaTiO3/SrRuO3 FTJ is useful for high-frequency simulation of benchmark FTJ circuits. [ABSTRACT FROM AUTHOR]

The subthreshold behavior of floating-gate MOSFETs connected with ferroelectric capacitors (FeCs) was investigated experimentally and theoretically. We found that the subthreshold swing (SS) decreases with decreasing ferroelectric capacitance (i.e., with the decreasing FeC area), in contrast to the voltage dividing effect of regular dielectric capacitors. The ferroelectric polarization switching counteracts the effect of voltage dividing by introducing an additional charge onto the floating gate, which improves the SS and leads to the observed SS dependence. The SS improvement caused by the polarization switching is different from the negative capacitance effect, which is helpful to further understand the ferroelectric transistor. [ABSTRACT FROM AUTHOR]

Polarization engineering in 30-nm Pb (Zr,Ti) O3 (PZT)/AlGaN/GaN high-electron-mobility transistors (HEMTs) is demonstrated. The coupling between ferroelectric polarization and 2-D electron gas (2DEG) showed a remarkable increase in transconductance during the down-sweep process; this can be attributed to the switching of ferroelectric polarization. With the increase in maximum gate voltage, the transfer curve showed a positive shift; this is because of the increase in polarization charges induced by gate voltage. The drain electric field affected the polarization of ferroelectric layer, leading to different hysteresis behaviors and peak transconductance trends of transfer curves. To decrease the effect of drain electric field on gate, a small drain voltage was used to evaluate the characteristics of PZT/AlGaN/GaN. The variation in peak transconductance was used to estimate the recovery and pinning degree of polarization. The ferroelectric layer modulates the 2DEG in ferroelectric/AlGaN/GaN HEMTs; this mechanism provides guidelines for designing and electrically controlling ferroelectric/AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

In this paper, we propose and investigate the high-performance and low-power design space of nonhysteretic negative capacitance (NC) MOSFETs for the 14-nm node based on the calibrated simulations using an experimental gate-stack with PZT ferroelectric to obtain the NC effect. All necessary parameters are extracted by carefully characterizing experimentally fabricated ferroelectric capacitors, to ensure realistic simulation results. The ferroelectric thickness obtained by the proposed approach leads to the maximum enhancement in the nonhysteretic operation of NC transistors. We report a clear and significant double improvement in: 1) subthreshold swing and 2) gate overdrive, using the NC effect. Simulations using Silvaco TCAD coupled with a realistic Landau model of ferroelectrics demonstrates that a 14-nm node ultrathin body and box fully depleted silicon-on-insulator FET can operate at 0.26 V instead of 0.9 V gate voltage using the NC effect, with an average subthreshold swing of 55 mV/decade at room temperature. The double-gate structure is proposed to overcome the large mismatch between the ferroelectric and MOS capacitor to enhance the NC effect and reduce the ferroelectric’s optimized thickness. A 14-nm node double-gate negative capacitance FET can operate at 0.24 V gate voltage with an average subthreshold swing of 45 mV/decade. [ABSTRACT FROM PUBLISHER]

As compared with Si as the substrate, ferroelectric (FE) HfZrOx with orthorhombic phase on Si0.56Ge0.44 substrate was found to demonstrate improved FE characteristics. Through the incorporation of Ge into the silicon substrate, remanent polarization (${P}_{r}$) can be further enhanced by 58% magnitude to $15~\mu \text{C}$ /cm2. Moreover, devices on Si0.56Ge0.44 show significant reliability enhancement in terms of negligible ${P}_{r}$ degradation up to 107 cycles under ±4 MV/cm with 10-kHz bipolar stress and desirable retention up to 104 s arising from smaller imprint effect against time at 85°C. The major role of Ge introduction into the substrate is to suppress the formation of the interfacial layer (IL) between HfZrOx/substrate and further reinforce the quality of the IL. The suboxide IL of the enhanced quality can be explained by the fact that it is too thin to trap charges while less vulnerable to defect generation due to stronger bonding with fewer oxygen vacancies. The results suggest that as the technology advances from Si into SiGe platform, HfZrOx-based devices possess more reliable ferroelectricity for metal–FE–semiconductor (MFS) gate-stack for the next-generation FeFET. [ABSTRACT FROM AUTHOR]

We fabricate, characterize, and establish the critical design criteria of Hf0.5Zr0.5O2 (HZO)-based ferroelectric field effect transistor (FeFET) for nonvolatile memory application. We quantify ${V}_{\textsf {TH}}$ shift from electron (hole) trapping in the vicinity of ferroelectric (FE)/interlayer (IL) interface, induced by erase (program) pulse, and ${V}_{\textsf {TH}}$ shift from polarization switching to determine true memory window (MW). The devices exhibit extrapolated retention up to 10 years at 85 °C and endurance up to $5\times 10^{6}$ cycles initiated by the IL breakdown. Endurance up to 1012 cycles of partial polarization switching is shown in metal–FE–metal capacitor, in the absence of IL. A comprehensive metal–FE–insulator–semiconductor FeFET model is developed to quantify the electric field distribution in the gate-stack, and an IL design guideline is established to markedly enhance MW, retention characteristics, and cycling endurance. [ABSTRACT FROM AUTHOR]

Recently, negative-capacitance FETs (NCFETs) have been proposed to reduce subthreshold slope and help continue supply-voltage scaling alongside channel-length scaling. We investigate the high-frequency switching behavior of NCFETs using the Landau–Khalatnikov equation to model ferroelectric materials. Multidomain interactions in the ferroelectric are considered, resulting in strong agreement with experimental measurements. Operation of NCFETs at gigahertz frequencies is investigated with this experimentally validated multidomain model. We find that the effectiveness of the voltage amplification in NCFETs is strongly dependent on the viscosity coefficient $\rho $ of the ferroelectric, and that a low \rho $ ( <0.1~\Omega \cdot \text {m} ) is required for the operation at the high gigahertz frequencies. [ABSTRACT FROM PUBLISHER]

In recent years, several experimental approaches have been adopted to study and understand the mechanism and improve the ferroelectricity of fluorite-type hafnia-based ferroelectric materials. In this regard, significant efforts have been made to elucidate the role of top electrode and bottom electrode (TE and BE) materials in defining the ferroelectricity in such systems, especially in terms of induced mechanical tensile stress by these materials during the process of annealing. However, the effect of the electrode material was not investigated both at TE and BE, and despite numerous efforts, there is still a lack of accurate and systematic understanding. In this report, we have carried out a systematic investigation on the effect of TE and BE materials having different coefficient of thermal expansion (CTE), by changing the electrode material one at a time, both at the top and bottom. The influence of the TE was confirmed using [TE/Hf0.5Zr0.5O2(HZO)/TiN] structure in which the BE was fixed as TiN, and the influence of the BE was confirmed using [TiN/HZO/BE] structure by fixing TiN as the TE. As revealed by polarization versus electric field and residual stress analysis, smaller CTE of the electrode was found to result in higher tensile stress in the HZO films during the annealing process, facilitating the formation of higher ferroelectric o-phase and thereby resulting in greater ferroelectricity. Although the influence of TE and BE on the ferroelectric property of HZO films was found to show similar trends according to the CTE value of the electrodes, the influence of TE on the ferroelectric property of the HZO capacitors is found to be mainly due to the variation in the induced mechanical tensile stress; pulse switching measurement and X-ray photoelectron spectrometer (XPS) analysis suggest that in case of BE, both the induced mechanical tensile stress and the interfacial dead layer were found to play a significant part. As a result, BE was found to have a greater influence on ferroelectricity of the HZO capacitors when compared with that of TE. The highest remnant polarization of 48.2 and 58.7 μC/cm2 was obtained for W with the lowest of CTE of 4.5 × 10-6/°C in both the configurations. The results obtained in this article are expected to provide a new way out to optimize the interface quality and ferroelectricity in HZO-based capacitors. [ABSTRACT FROM AUTHOR]

Heterogeneous stacked electronics are one of the major topics in flexible electronics applications, which require high performances. At the same time, P(VDF-TrFE)-based polymers with unique characteristics, e.g., ferroelectric and flexible properties, also bring attention to heterogeneous stacked device applications. Since the interfacial characteristic has strong effects with performance and reliability, therefore, it becomes one of the key issues in P(VDF-TrFE)-based heterogeneous stacked devices. In this article, a mechanism of an interface trap charge-induced low-k interfacial layer was proposed and examined by experimental methods. To analyze the low-k interfacial layer effects, both general-doping (few 1015 cm−3) p-type and n-type silicon substrate were used. These experimental results showed that different types of silicon substrates have distinct interface properties. Then, different interface trap density (1.75 × 1012–4.1 × 1011 eV−1 cm−2) silicon substrates were fabricated to further analyze the low-k interfacial layer. These showed the substrate with the lowest interface trap density has less low-k interfacial effect than other substrates do. Based on these experimental verifications, the mechanism of interface trap charge-induced low-k interface characteristic was proposed. As a consequence, this interface trap–charge-induced behavior is a necessary consideration for applications of heterogeneous stacked devices. [ABSTRACT FROM AUTHOR]

Ferroelectric field effect transistors (FeFETs) are being actively investigated with the potential for in-memory computing (IMC) over other nonvolatile memories (NVMs). Content addressable memories (CAMs) are a form of IMC that performs parallel searches for matched entries over a memory array for a given input query. CAMs are widely used for data-centric applications that involve pattern matching and search functionality. To accommodate the ever expanding data, it is attractive to resort to analog CAM for memory density improvement. However, the digital CAM design nowadays based on standard CMOS or emerging NVMs (e.g., resistive storage devices) is already challenging due to area, power, and cost penalties. Thus, it can be extremely expensive to achieve analog CAM with those technologies due to added cell components. As such, we propose, for the first time, a universal compact FeFET-based CAM design, FeCAM, with search and storage functionality enabled in digital and analog domains simultaneously. By exploiting the multilevel-cell (MLC) states of FeFET, FeCAM can store and search inputs in either digital or analog domain. We perform a device-circuit codesign of the proposed FeCAM and validate its functionality and performance using an experimentally calibrated FeFET model. Circuit level simulation results demonstrate that FeCAM can either store continuous matching ranges or encode 3-bit data in a single CAM cell. When compared with the existing digital CMOS-based CAM approaches, FeCAM is found to improve both memory density by 22.4× and energy saving by 8.6 ×/3.2× for analog/digital modes, respectively. In the CAM-related application, our evaluations show that FeCAM can achieve 60.5×/23.1× saving in area/search energy compared with conventional CMOS-based CAMs. [ABSTRACT FROM AUTHOR]

Ferroelectric materials are characterized by two stable polarization states that can be switched from one to another by applying an electrical field. As one of the most promising effects to realize nonvolatile memories (NVMs), the application of ferroelectrics in NVMs has been studied since the 1950s. In principle, three different ways to read out the ferroelectric polarization are known: measuring the charge-related current that flows during switching of the ferroelectric, measuring the polarization-dependent tunneling current in very thin ferroelectric layers, and measuring the threshold voltage shift of a ferroelectric field effect transistor caused by the polarization change of the ferroelectric integrated into the gate stack. While early attempts used bulk ferroelectric crystals, the first commercial success was reached when the concept was integrated into a MOS process. However, all materials that were known to exhibit ferroelectricity had a very complicated structure, thus making the integration troublesome and leading to a very slow scaling and limiting its application to niche markets. With the discovery of ferroelectricity in hafnium oxide in 2011, the new impetus came into the field for all three variants described above. This article will describe the history of ferroelectric memories and its current status both with respect to the commercialization of ferroelectric memories based on traditional ferroelectric materials and the ongoing research and development activities employing the more recently discovered ferroelectricity in hafnium oxide. This finally leads us to an outlook of the future challenges for ferroelectric memories. [ABSTRACT FROM AUTHOR]

Ferroelectric-doped HfO2-based ferroelectric field-effect transistors (FeFETs) are being actively explored as emerging nonvolatile memory (NVM) devices with the potential for in-memory computing. In this two-part article, we explore the feasibility of the FeFET-based 3-D NAND architecture for both in situ training and inference. To address the challenge of erase-by-block in a NAND-like structure, we propose and experimentally demonstrate the drain-erase scheme to enable the individual cell’s program/erase/inhibition, which is necessary for individual weight updates in in situ training. We described the device characterization of different drain-erase conditions and results in Part I. The array-level design for this drain-erase scheme for both AND-type and NAND-type array is addressed in this Part II. A 3-D vertical channel FeFET array architecture is proposed to accelerate the vector-matrix multiplication (VMM). 3-D timing sequence of the weight update rule is designed and verified through the 3-D-array-level SPICE simulation. Finally, the VMM operation is simulated in a 3-D NAND-like FeFET array. [ABSTRACT FROM AUTHOR]

This brief exploits the fusion of low-power logic and nonvolatile memory inside the emerging ferroelectric FETs (FeFETs) and proposes a new nonvolatile D flip-flop (nvDFF) through the device-circuit co-design. Compared with existing FeFET-based nvDFFs with on-demand control of backup and restore (B&R), the area overhead is lowered by half, and the routing cost is reduced with embedded backup control into the supply voltage. Circuit simulations show below 5% energy-delay overhead in the normal mode and femtojoule B&R energy. This new nvDFF promises area- and energy-efficient nonvolatile computing for power-gating and energy-harvesting applications. [ABSTRACT FROM AUTHOR]

Static Landau theory has been widely used to confirm negative capacitance ferroelectric MOSFET (FeFET) as a low power switch with sub-60-mV/decade subthreshold swing. However, dynamic switching considering damping effect in ferroelectrics is rarely evaluated. Based on Landau–Khalatnikov theory, dynamic FeFET characteristics are obtained. For experimentally extracted Pb(Zr0.2Ti0.8)O3 (PZT) damping constant $\xi _{{\text {FE}}} = 75\Omega \cdot \text {m}$ , the amplified gate capacitance induced by negative capacitance occurs when frequency is below a few MHz for large $\xi _{{\text {FE}}}$ . For transient simulation, $I_{{\text {DS}}} exhibits a slow response to the rapid change of VG so that the hysteretic I{\text {DS}} – VG curve is generated. Furthermore, inverter prediction with complementary FeFETs shows that the dynamic short circuit switching power is much higher than the static one. These results are attributed to the large PZT response time in comparison with the operation period. For a guidance on ferroelectric selection and improvement, a wide range of damping constants are used to predict the corresponding maximum operation frequency, within which the dynamic and static responses of FeFETs are the same. It indicates that the ferroelectrics with low damping constant are essential to utilize FeFET advantages in high-frequency circuit applications. [ABSTRACT FROM AUTHOR]