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The article invites, papers from authors for a special issue of the journal "IEEE Transactions on Electron Devices" on "Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices."

The article presents the invitation of the journal to interested individuals to submit papers and articles on memory, logic and CMOS devices.

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

The article offers information on electronics devices, complementary metal–oxide–semiconductor (CMOS) logic, power and memory. Topics discussed include electronics devices with features related to experimental results and theoretical model; include advanced transitory with features of self-heating effect and variability; and discusses power devices like the metal–oxide–semiconductor field-effect transistor (MOSFET) and insulated-gate bipolar transistor (IGBT).

It is my great pleasure to introduce the Seventh Special Issue of the IEEE TRANSACTIONS ON ELECTRON DEVICES on Solid-State Image Sensors. Previous special issues were published in February 1976, August 1985, May 1991, October 1997, January 2003, and November 2009. During the six-year interval since the last special issue, significant changes have occurred in the field of solid-state image sensors. This is due, in particular, to the drive for low-power, high integration, compact imaging systems. Now that the speed of pixel shrinkage is slowing down, various new technologies are being developed to increase the functionality of the sensors, to make them more compact, to make them faster, to increase their dynamic range, etc. Papers reflecting these trends in the image sensor technology are well represented in this special issue. [ABSTRACT FROM AUTHOR]

A foreword to "IEEE Transactions on Electron Devices" is presented.

A transient and static hybrid-triggered active clamp is proposed in this paper. By skillfully incorporating different detection mechanisms, the proposed clamp achieves enhanced static electrical overstress protection capability over the transient one. Furthermore, the proposed clamp achieves improved electrostatic discharge reaction speed in both human body model and charged device model events over the static one. Moreover, the superior transient-noise immunity of the proposed clamp over traditional transient ones is essentially revealed in this paper. The proposed clamp is successfully verified in a 65-nm bulk CMOS process. In addition, the design flexibility of the proposed clamp for other processes is also deeply discussed in this paper. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of quantum capacitance on the intrinsic inversion-capacitance ( C\mathrm{ inv}) characteristics of high-mobility multigate III–V-on-insulator nMOSFETs through a numerical simulation corroborated by the theoretical calculation. Nonmonotonic C\mathrm{ inv} characteristics stemming from the energy dependence of 1-D density-of-states and significant C\mathrm{ inv} degradation due to quantum capacitance have been found in trigate In0.53Ga0.47As and InAs devices based on the ITRS 2018–2024 technology nodes. This paper indicates that, to compensate the excess inversion-charge ( Q\mathrm{ inv} ) loss due to quantum capacitance, the needed mobility gain of the trigate InGaAs and InAs devices (against the Si counterparts) should be at least $\sim 3\times $ and $\sim 4\times $ , respectively. This paper also suggests that the quantum-capacitance-induced Q\mathrm{ inv} loss can be mitigated by raising the fin aspect ratio of the III–V multigate device. [ABSTRACT FROM AUTHOR]

To effectively solve the crosstalk issue in high-density crossbar array (CBA), high rectifying characteristics should be introduced in the resistance random-access memory (ReRAM) device, and in-depth understanding of the affecting factors on rectifying properties is essential for the large-scale application of ReRAM. In this paper, a high-performance self-rectifying device with CMOS compatible Pd/HfO2/TaOx/Ta structure was demonstrated in a 1-kb CBA. Forming-free, self-compliance, and high uniformity characteristics were successfully achieved. By modulating the thickness of the HfO2 rectifying layer, the rectifying ratio of device could be achieved as high as $\sim 2\times 10^{\textsf {3}}$ under ±3 V at low-resistance state (LRS). It was also experimentally confirmed that the selected unit cell in high-resistance state (logically the “ OFF” state) was stably readable when it was surrounded by unselected LRS (logically the “ ON” state) cells, in an array of up to $32 \times 32$ cells. Furthermore, a model based on interfacial barrier modulation and defects trapping/detrapping was proposed to elucidate the impact of the dielectric thickness on the self-rectifying characteristics of the device. The results presented in this paper provide a great potential for selector-free high-density memory applications. [ABSTRACT FROM AUTHOR]

This paper analyzes the performance of mosaic nonimaging passive infrared (PIR) sensors fabricated by the CMOS–SOI–MEMS technology. The elementary sensor, forming a subpixel, is a thermally isolated nanomachined CMOS transistor, dubbed TMOS, operating at subthreshold. The mosaic uncooled PIR sensors are composed of several TMOS subpixels, which are electrically connected, either in parallel or in series as well as a combination of both options. These mosaic sensors, which are manufactured by nanofabrication methods, exhibit enhanced performance and robust manufacturing on wafer level. The overall figures of merit of these sensors, which are modeled in this paper, indicate why they are most suitable for consumer electronics, including smart homes, wearables, Internet of Things as well as mobile applications. [ABSTRACT FROM AUTHOR]

This paper revisits the physics of current filamentation in grounded-gate NMOS (ggNMOS) devices and presents new physical insights which were not addressed in earlier works. A clear distinction between electrical and thermal instabilities is presented. Moreover, filament dynamics under electrical and thermal instability in both silicided and silicide blocked devices is discussed while highlighting observations which contradict with established theory of current ballasting. Interplay between electrical and thermal instabilities and its dependence on the presence or absence of silicide blocking is explored further. Filament spreading in ggNMOS devices and it is dependence on silicide blocking is discussed. Finally, while using the developed physical insights, missing correlation between TLP and HBM extracted failure current of silicided ggNMOS device is explained. [ABSTRACT FROM AUTHOR]

In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with L\mathrm{ eff}= 36 nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized layout scheme is proposed to reduce the gate parasitic resistance and capacitance in this paper, and the proposed layout exhibits improved RF behaviors for fT , f\mathrm {\mathrm {MAX}} , and NFmin at 26 GHz up to ~13%, ~24%, and ~18% compared with the reference layout scheme, respectively. [ABSTRACT FROM PUBLISHER]

In this paper, a ZnO-based semiconductor thin film memristor (300 nm in thickness) device is fabricated using metallic top and bottom electrodes by direct-current reactive magnetron sputter. The memristive characteristics of the device were completed by time-dependent current--voltage (I--V-t) measurements, and the typical pinched hysteresis I--V loops of the memristor were observed. This paper is continued with the designing memristor emulator circuit, which has only four MOS transistors. The proposed circuit is suitable both for emulating the fabricated memristor and for using general memristor-based applications. Any circuit blocks such as a multiplier or active element are not used in the circuit to obtain memristive characteristics. All results of the proposed memristor emulator circuit are compatible with general characteristics of the fabricated semiconductor device. The MOSFET-based proposed memristor emulator circuit is laid out in the Analog Design Environment of Cadence Software using 180-nmTSMC CMOS process parameters and its layout area is 366 μm². So as to show its performance, the dependences of the operating frequency and process corner as well as effects of radical temperature changes have been investigated in the simulation results section. [ABSTRACT FROM AUTHOR]

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip. [ABSTRACT FROM PUBLISHER]

Wafer-scale, CMOS compatible graphene transfer has been established for device fabrication and can be integrated into a conventional CMOS process flow back end of the line. In Part I of this paper, statistical analysis of graphene FET (GFET) devices fabricated on wafer scale is presented. Device yield is approximately 75% (for 4500 devices) measured in terms of the quality of the top gate, oxide layer, and graphene channel. Statistical evaluation of the device yield reveals that device failure occurs primarily during the graphene transfer step. In Part II of this paper, device statistics are further examined to reveal the primary mechanism behind device failure. The analysis from Part II suggests that significant improvements to device yield, variability, and performance can be achieved through mitigation of compressive strain introduced in the graphene layer during the graphene transfer process. The combined analyses from Parts I and II present an overview of mechanisms influencing GFET behavior as well as device yield. These mechanisms include residues on the graphene surface, tears, cracks, contact resistance at the graphene/metal interface, gate leakage as well as the effects of postprocessing. [ABSTRACT FROM PUBLISHER]

A bond-pad charging protection design for charging-free reference transistor test structures was examined. This paper concludes that truly charging-free reference transistors cannot be realized with the one conventional bond-pad charging protection design of protecting transistor gates only. This, however, can be achieved by simultaneously protecting all terminals of the reference transistors. The simulations, in this paper, reconfirm the earlier important experimental conclusion that placing protection device(s) at transistor gates may inflict severe damage to transistor gate oxides instead of protecting them. The implication of the above suggests that attention may be required in a circuit layout design stage for those transistors which gates begin to connect, at high metal layers, to highly efficient leakage paths, such as protection devices, n-type source/drain diffusion regions, and VSS bus lines, which tend to pull transistor gates to low potentials during a backend integrated-circuit manufacturing process. This paper proposes an optimum bond-pad charging protection design for the truly charging-free reference transistor test structures by considering a minimum usage in a layout space and minimum gate oxide stress in the fuse zap-off process. [ABSTRACT FROM AUTHOR]

An eight-FinFET fully differential SRAM cell is proposed in this paper to achieve stronger data stability and enhanced write ability. The p-type transistors are used for data access during read operations and transmission gates are employed to force new data into the cell during write operations. At the nominal process corner, the proposed SRAM cell enhances the read data stability, write voltage margin, and write data transfer speed by up to $2.7\times $ , 15.8%, and 76%, respectively, while consuming similar leakage power as compared with the previously published six-FinFET fully differential SRAM cells in 15-nm FinFET technology. Under isodata stability, the proposed SRAM cell allows the lowering of the power supply voltage by up to 44.3% as compared with the other SRAM cells that are investigated in this paper. [ABSTRACT FROM AUTHOR]

Oxide semiconductors are highly attractive for fabrication of large-area thin-film electronics because of their high electrical performance, low process temperature, high uniformity, and ease of industrial manufacturing. n-type oxide semiconductors, such as InGaZnO, are highly developed and have already been commercialized for backplane drivers of flat-panel displays. To date, developing CMOS technology is still an urgent issue in order to build low-power electronic circuits based on oxide semiconductors. In this paper, various CMOS circuits, including inverters, NAND, NOR, XOR, d-latches, full adders, and 7-, 11-, 21-, and 51-stage ring oscillators (ROs), are fabricated based on sputtered p-type tin monoxide and n-type InGaZnO. The inverters show rail-to-rail output voltage behavior, low average static power consumption of 8.84 nW, high noise margin level up to ~40% supply voltage, high yield of 98%, and high uniformity with negligible standard deviation. The NAND, NOR, XOR, d-latches, and full adders show desirably ideal input–output characteristics. The performances of ROs indicate small stage delay of $\sim 1~\mu \text{s}$ , extremely high uniformity and high yieldwhich are essential for large-area thin-film electronics. This paper may inspire constructions of low power, large area, large scale, and high-performance transparent/flexible CMOS circuits fully based on oxide semiconductors for applications beyond flat-panel displays. [ABSTRACT FROM AUTHOR]

In this paper, several fundamental pseudo-CMOS digital circuits with n-type indium tin oxide-stabilized ZnO thin-film transistors (TFTs) were implemented and investigated. The optical transmittance of circuits varied from 77% to 92% throughout the visible wavelength band. Electrically, the operation frequency of inverters, nor gates, nand gates, D latches, and D flip flops were all found to exceed 10 kHz with a supply voltage of 10 V. Besides, 13-stage ring oscillators could be operated at 42 kHz with a propagation delay time of $0.92~\mu \text{s}$ when the supply voltage was set as 20 V. Among the state-of-the-art transparent designs, these proposed circuits based on the ITO-stabilized ZnO TFTs exhibited high-speed performance, which were promising as building blocks for transparent electronics with moderate frequency requirements. [ABSTRACT FROM AUTHOR]

This paper reports the fabrication of MEMS-based guided two-beam piezoelectric energy harvester for low-frequency operation. A highly c-axis-oriented zinc oxide thin film of 2.5- $\mu \text{m}$ thickness covered with 0.5- $\mu \text{m}$ plasma-enhanced chemical vapor deposition SiO2 is sandwiched between the aluminum electrodes to form split electrodes on the two beams. A pyramidal-shaped seismic mass that gives a higher electric potential is realized by bulk micromachining using CMOS compatible 25 wt% tetramethyl ammonium hydroxide wet etching. The thickness of the beams is optimized using deep reactive-ion etching to achieve a low-frequency operation. COMSOL Multiphysics has been used to study the stress distribution to optimize the dimension and placement of the split electrodes. The optimized split electrodes give a reduced resonance frequency by 4.2% when compared with previously used electrode pattern ensuring maximum electric potential generation for guided two-beam structure. The resonance frequency of the device measured experimentally using laser Doppler vibrometer comes to be 466 Hz. The packaged device exhibits a maximum sensitivity of 1.5089 mV/m/s2 in the frequency range from 160 to 1000 Hz. [ABSTRACT FROM AUTHOR]

With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator (SOI) and double-gate (DG) metal–ferroelectric–insulator–semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications. [ABSTRACT FROM AUTHOR]

In this paper, we report on the assessment of self-amplified silicon–oxide–nitride–oxide–silicon (SONOS) memory device architecture for sub-50-nm gate length (${L}_{g}$) through calibrated simulations. Self-amplification (SA) effect in tunnel field-effect transistor-based SONOS (T-SONOS) memory device has been analyzed. Results show that memory window ($\Delta {W}$) in T-SONOS cell increases as buried oxide thickness increases due to capacitive coupling between the front and back gates. Although the enhanced $\Delta {W}$ can also be achieved in inversion-mode SONOS (I-SONOS) device, its performance is deteriorated when the gate length is scaled down. We have compared the performance of I-SONOS and T-SONOS memory devices for ${L}_{g}$ varying from 100 to 25 nm. Results highlight that I-SONOS device cannot be programmed at ${L}_{g} ={25}$ nm and thus deteriorate the memory operation. However, SA T-SONOS at ${L}_{g} = {25}$ nm achieves ${W} \sim {6}$ V. In addition, the effect of underlap on the performance of T-SONOS cell has been analyzed, and it is shown that memory operation of 25-nm T-SONOS device can further improved with a drain side underlap of 20 nm. This paper provides new opportunities to design SA T-SONOS memory device for the next-generation nonvolatile memories. [ABSTRACT FROM AUTHOR]

The application of capacitive deep trench isolation (CDTI) as a shared vertical transfer gate (VTG) in a back-side-illuminated CMOS image sensor pixel is investigated using 3-D device-level simulations. The parasitic capacitance existence between CDTI and deeply buried pinned photodiode (BPD), and also between CDTI and floating diffusion (FD) region, makes the charge transfer process more difficult. In order to design a lag-free pixel and obtain complete charge transfer from BPD to FD, various considerations regarding the device-level design should be taken into account which is discussed in this paper. A CDTI neighboring two pixels can be functionalized as a shared VTG. Using CDTI as shared VTG facilitates pixel miniaturization and can result in more circuit integration at the pixel surface. This paper proposes a ${2}\,\,\mu \text{m} \times {2}\,\,\mu \text{m}$ pixel with CDTI as shared VTG, an equilibrium full-well capacity of 4605 e−, and a complete charge transfer from BPD to FD. [ABSTRACT FROM AUTHOR]

4H-silicon carbide (SiC) is a suitable candidate for high-temperature and radiation prone applications, due to its superior electrical and material properties. Several researchers have demonstrated small-scale logic circuits, entirely in 4H-SiC; however, to build a complete electronic module in 4H-SiC, a memory component is yet to be developed. This paper presents for the first time the design, optimization, and performance analysis of a 4H-SiC-based bipolar memory column including a static random access memory cell and peripherals, designed for voltages as low as 5 V. The memory column has average noise margins of 2 V and delays in the range of few nanoseconds at room temperature. The proposed memory architecture also demonstrates robust operation across a wide range of temperatures (27 °C–500 °C) with stable noise margins and speeds. This paper validates the potential of developing memory architectures in 4H-SiC, which operates reliably for varying conditions, paving the way to build complete electronic systems entirely based on 4H-SiC. [ABSTRACT FROM AUTHOR]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

Performance limitations of superjunction (SJ) devices due to charge imbalance (CI) are analyzed in this paper. It is demonstrated that in the presence of CI, the specific on-resistance has a quadratic dependence on blocking voltage, similar to a conventional drift region. We also show that by designing the SJ structure with an optimally modified pillar doping, we can achieve better performance under conditions of CI. The design guidelines presented in this paper are applicable to any semiconductor, although all calculations are based on silicon carbide. [ABSTRACT FROM AUTHOR]

The purpose of this paper is to present the main results of an electrostatic discharge (ESD) protection for advanced CMOS technology with electromagnetic (EM) field effect and Lorentz Force (LF) contributions during fast transient and high-current surge. To address this goal, the first step is building a tool to simulate fast transient conditions with all participating physical mechanisms included. The relevant equations describing these mechanisms are: 1) the charge transport equations and 2) the Maxwell equations to describe the EM fields. The LF is also included using an extended formulation of the current-continuity equations. An integrated approach is followed to simulate the full structure (metal connections $+$ silicon device) during the ESD surge and to compare the results between ElectroMagnetic Lorentz Force simulations and transmission line pulse measurements. Obviously, in general, this paper and tool can be used to address electromagnetic compatibility topics and more. [ABSTRACT FROM AUTHOR]

In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and $5\times $ improvement in the electrostatic discharge robustness are reported experimentally. [ABSTRACT FROM PUBLISHER]

This paper discusses improvements to a lateral bipolar device capable of integration into the existing CMOS process flow. With the help of simulations, we demonstrate that the emitter transit time limits the cutoff frequency of a lateral bipolar device. We show that with the introduction of a heterojunction and a partially depleted base, we can decrease the emitter transit time and increase the current gain and the cutoff frequency ( ft) of the device. For a balanced design, our simulations indicate an n-p-n device with an ft of 812 GHz and an fmax of 1.08 THz; and a p-n-p device with an ft of 635 GHz and an fmax of 1.15 THz. The collector current at cutoff frequency for both n-p-n and p-n-p devices is $\sim 0.03$ mA—roughly 100 times lower than commercial vertical heterojunction bipolar transistors. [ABSTRACT FROM AUTHOR]

In this paper, asymmetric underlap double-gate (AUDG) MOSFET is studied to analyze the influence of high- k spacer on the intrinsic device parameters. The AUDG-MOSFET architecture offers better device performance, particularly, drain-induced barrier lowering in contrast to the conventional double-gate (DG)-MOSFET. However, the ON current and the distributed resistances for the device increase considerably. The analysis of the device presented here shows that the detrimental effects of the device can be effectively eliminated using high- k spacers. To evaluate the device performance and to study the improvement associated with the use of high- k spacers, different intrinsic parameters are analyzed. These parameters include transconductance ( , transconductance generation factor ( g_{m} / I_{d}) , intrinsic gain ( gmro) , intrinsic capacitance ( Cgd , Cgs) , resistance ( Rgd , Rgs) , transport delay ( \tau m) , inductance ( Lsd) , cutoff frequency ( fT\!) , and the maximum frequency of oscillation ( fmax) , gain bandwidth product, and inverter delay. [ABSTRACT FROM AUTHOR]

In this paper, we use an automated tool flow in a 14 nm CMOS fin-shaped field-effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statistical variabilities. A 22 nm FinFET CMOS technology is used to illustrate the sensitivity to process-induced fin shape variation and to motivate this paper. Predictive Technology Computer Aided Design (TCAD) simulations have been carried out to evaluate the transistor performance ahead of silicon. Draft-diffusion simulations calibrated to the ensemble Monte Carlo simulation results are used to explore the process and the statistical variability space. This has been enabled by the automation of the tool flow and the dataset handling. The interplay between the process and the statistical variability has been examined in details. A two-stage compact model strategy is used to capture the interplay between process and statistical variability. To close the DTCO loop, the static noise margin and write noise margin sensitivity to cell design parameters and variability in FinFET-based SRAM designs are studied in details. [ABSTRACT FROM AUTHOR]

Random walk (RW)-based local search algorithms are highly popular for solving combinatorial optimization problems such as the satisfiability (SAT) problem. The RW algorithm tries to solve the SAT problem by flipping a randomly chosen variable to minimize the number of unsatisfied clauses for a given problem. In this paper, we propose a biased RW (BRW) based on stochastic magnetization switching dynamics of nanomagnets in the presence of thermal noise. The controllable stochastics witching behavior of nanomagnets is used to flip the current state of the variable of interest based on the assigned probability. Here, the flipping probabilities are assigned to the variables responsible for unsatisfied clauses (instead of deterministic flipping in traditional algorithms). The stochasticity of individual units of the proposed hardware SAT solver based on a magnetic tunnel junction lying on top of a heavy metal layer enables parallel search of the solution space, which results in rapid convergence in comparison to the baseline RW algorithm. A device-circuit-algorithm cosimulation framework (benchmarked to experimental measurements of a magnetic stack) is used to assess the efficiency of the proposal. In comparison to the baseline RW algorithm, stochastic magnetization switching-driven BRW achieves ~94% reduction in search time while consuming ~30 pJ energy per iteration. [ABSTRACT FROM AUTHOR]

In this paper, a 1.1-μm-pitch 33-Mpixel 240-fps backside-illuminated 3-D-stacked CMOS image sensor with three-stage cyclic-cyclic-successive-approximation-register (SAR) analog-to-digital converters (ADCs) is developed. The narrow-pitch interconnection technology that connects the pixels and arrayed ADCs inside the pixel area is described. The 3-D-stacked architecture, constructed using the interconnection technology, makes it possible to place a 1932 (H) × 4 (V) correlated-double-sampling/ADC array underneath the pixel area. Furthermore, the pipelined and parallel operation of the three-stage cyclic-cyclic-SAR ADC architecture effectively reduces the conversion time period and power consumption and achieves 12-b precision within one horizontal scan time of 0.92 μs. As a result, the interconnection technology and ADC architecture achieved a high frame rate of 240 fps in 33 Mpixels. Random noise of 3.6 e- and low power consumption of 3.0 W were attained at an extremely high pixel rate of 7.96 Gpixel/s. A good figure of merit is achieved compared with recently developed image sensors. [ABSTRACT FROM AUTHOR]

In this paper, we present an effective switching current model ( I\textsf {eff} ) for inverter followed by a transmission gate structure (Inv-Tx) based on its switching trajectory. Unlike an inverter or NAND/NOR gates, where I\textsf {eff} depends only on nMOSFET (pMOSFET) current for a falling (rising) transition, it is a function of both nMOSFET and pMOSFET currents for an Inv-Tx cell. The proposed model is verified against HSPICE simulations for a wide range of supply voltages and fan-outs at different technology nodes (e.g., 180, 130, and 65 nm). The model predicts the transition delay values with an average (maximum) error of 7% (11%) compared with HSPICE simulations. Synopsys TCAD Sentaurus simulations at 32-nm technology node are also used to validate the basic model assumptions. To demonstrate the utility of our model, design of some representative circuits while incorporating layout-dependent effects and inverse-narrow-width effect is presented. Finally, we show that a 256X1 multiplexer and a static D-flip-flop, with their transistor sizes and layout, optimized using the proposed model improves the performance of these circuits significantly over the conventional design methodologies. [ABSTRACT FROM PUBLISHER]

The metal–semiconductor interface is fundamental to any semiconductor device and the success of advanced technology nodes critically depends upon the minimization of the contact resistance at the interface. In this paper, we calculate the electronic structure of a metal–semiconductor interface (TiGe/Ge contact) within the framework of first-principles density functional theory simulations. We report the modulation of the Schottky barrier height with respect to the different phases of TiGe metal and different crystallographic orientations of Ge substrate. We further compute the I – V characteristics of the TiGe/Ge contact with nonequilibrium Green’s function formalism, using a two-terminal device configuration. The calculated transmission spectrum allows us to extract the contact resistance at the metal–semiconductor interface. Furthermore, the onset of Ohmic contact for p-doped TiGe/Ge interface is identified by studying the I – V characteristics as a function of increasing active carrier concentration. We find that a doping concentration of 1e21 is sufficient to transform the Schottky contact into Ohmic and thereby achieve a least possible contact resistance at the interfaces. Our paper thus provides useful physical insights into the nanoscale details of the TiGe/Ge interfaces and can guide further process development to minimize the contact resistance. [ABSTRACT FROM PUBLISHER]

In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. [ABSTRACT FROM PUBLISHER]

This paper presents an analytical model of the full well capacity (FWC) in pinned photodiode (PPD) CMOS image sensors. By introducing the temperature dependence of the PPD pinning voltage, the existing model is extended (with respect to previous works) to consider the effect of temperature on the FWC. It is shown, with the support of experimental data, that whereas in dark conditions the FWC increases with temperature, a decrease is observed if FWC measurements are performed under illumination. This paper also shows that after a light pulse, the charge stored in the PPD drops as the PPD tends toward equilibrium. On the basis of these observations, an analytical model of the dynamic behavior of the FWC in noncontinuous illumination conditions is proposed. The model is able to reproduce experimental data over six orders of magnitude of time. Both the static and dynamic models can be useful tools to correctly interpret FWC changes following design variations and to accurately define the operating conditions during device characterizations. [ABSTRACT FROM AUTHOR]

An electron multiplying CMOS images sensor (emCMOS) enables electron multiplication inside the pixel by the use of high voltage ( \(hv\) ) phase(s) under gate(s). Different possible implementations of \(hv\) gates dedicated to impact ionization require specific multiplication patterns and therefore new excess noise formulation. This paper presents a rigorous mathematical approach to the calculation of the excess noise factor for all electron multiplying CMOS pixel structures in the framework of the branching processes and the compounding theorem of the probability generating function. Validation of the model is performed by computing the variance formula for one pixel structure and its corresponding Monte Carlo simulation of the stochastic processes. The signal over noise ratio including the readout noise, SNRro, is introduced to evaluate the possible extreme low light imaging performance as a function of the multiplication parameters. [ABSTRACT FROM AUTHOR]

In this paper, we present a complete study of the drain and gate current local variability in high- k /metal gate-stack 14-nm fully depleted silicon-on-insulator CMOS transistors. A thorough experimental characterization of both drain and gate current mismatch was performed. In addition, we developed, for the first time, models of the drain and gate current mismatch, valid in all operation regions. Finally, we demonstrate the universal validity of our models through Monte Carlo simulations. [ABSTRACT FROM AUTHOR]

This paper presents a 512-column linear CMOS image sensor (CIS) with 32-stage digital time-delay integration (TDI) operation. A signal processing architecture consists of analog-front-ends, analog-to-digital converters (ADCs), and digital accumulators (DAs) are designed with optimization of timing, area, and power efficiency. An eight-column-shared 10-b successive approximation register ADC with data prediction switching technique and 11-b DA are proposed to achieve a data depth of 15 b after 32-stage TDI. The achieved signal-to-noise ratio boost is 14.84 dB after 32-stage TDI operation. The proposed linear TDI sensor is implemented in 0.11- \mu \textm TSMC backside illumination CIS technology with a line time of 104~\mu \texts , a pixel pitch of 7.5~\mu \textm , and a power consumption of 153.2~\mu \textW /column. [ABSTRACT FROM AUTHOR]

In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas. [ABSTRACT FROM PUBLISHER]

The proposed chord-fractal pattern has a significant impact on IC capacitor, increasing the capacitance within a limited chip area. To reduce the device area, this paper presents a modified fractal algorithm. This proposed algorithm uses various initiators to perform chord iteration on the unit cell. The iteration procedure automatically generates an area-saving fractal layout of IC capacitor. To verify the proposed algorithm, an area-saving device of chord-fractal is fabricated using UMC 0.18- \mu \textm CMOS technology. [ABSTRACT FROM PUBLISHER]

In this paper, Ge nanowire (NW) CMOS devices and circuits are analyzed in detail. Various experiment splits are studied, including device geometry parameters such as the channel lengths ( L\mathrm{ ch} ) from 100 to 40 nm, a NW height ( H\mathrm{ NW} ) of 10 nm, the NW widths ( W\mathrm{ NW} ) from 40 to 10 nm, and the dielectric equivalent oxide thicknesses (EOTs) of 2 and 5 nm, and four types of device operation modes of accumulation mode (AM) and inversion mode (IM) n-type MOSFETs and p-type MOSFETs. Benefited from the NW structure with scaled EOT, subthreshold swing (SS) as low as 64 mV/dec and maximum transconductance ( g\max ) as high as 1057~\mu \textS/\mu \textm are obtained on the Ge NW nMOSFETs. The NW pMOSFETs are also realized on the same common substrate. Furthermore, hybrid Ge NW CMOS with AM nMOSFET and IM pMOSFET is demonstrated for the first time on a Si substrate. The highest maximum voltage gain reaches 54 V/V in the Ge NW CMOS inverters. [ABSTRACT FROM PUBLISHER]

Inverter delay is often evaluated as $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ , where ${C}$ is the load capacitance, ${V}_{\text {dd}}$ is the supply voltage, and ${I}_{\text {eff}}$ is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The ${I}_{\text {eff}}$ model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (~15%) is the main reason for wide application of $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ delay metrics. However, $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ expression produces large errors when applied to another two important basic circuits: NAND and NOR. This is because NAND and NOR circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in NAND/NOR circuits is provided. The model for NAND/NOR effective drive current (denoted as ${I}_{\text {stack}}$) developed in this paper maintains simplicity of the original ${I}_{\text {eff}}$ expression. It requires only one additional measurement of the linear current. Model accuracy was assessed by comparing to extensive SPICE delay simulations of NAND and NOR circuits designed using state-of-the-art MOS technologies. Comparison results show that $\textit {CV}_{\text {dd}}/{I}_{\text {stack}}$ equation provides ~15% accuracy for NAND/NOR circuits in line with $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation. [ABSTRACT FROM AUTHOR]

A new generation of thermal sensors based on a suspended thermal transistor MOS (TMOS), fabricated in the standard CMOS-SOI process, released by postetching, has been recently developed. One of the important features of TMOS is its high responsivity due to the transistor built-in amplification and subthreshold operation enabling a wide range of battery applications. This paper focuses on a new gas sensor, dubbed GMOS, based on the TMOS. The GMOS is a catalytic gas sensor (pellistor-like), and as such detects combustible gases in air. The CMOS-SOI technology combined with tungsten metallization enables operation at very high temperatures (450 °C was tested). The sensors and readout are processed with the same CMOS-SOI technology. Accordingly, the GMOS sensor, processed in low-cost CMOS-SOI technology, promises to become the widely accepted gas sensing approach for mobile applications, including wearables, smart homes, as well as smartphones. [ABSTRACT FROM AUTHOR]

This paper presents the detailed physical insights into the silicon-controlled rectifier (SCR) phenomena in planar equivalent Fin SCR devices. The complexity and roadblocks for SCR triggering in FinFET technology are explored. Implication of contact silicidation on Fin SCR turn- ON is discussed in detail. Device design approaches are discussed for efficient Fin-enabled SCRs. In this direction, a novel contact engineering scheme in Fin technology is disclosed for improved SCR action. Moreover, a novel Fin SCR is presented, which offers area-efficient electrostatic discharge current carrying capability. [ABSTRACT FROM AUTHOR]

In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts. [ABSTRACT FROM AUTHOR]

In this paper, bias modulated synapse transistor based on ultrathin molybdenum disulfide (MoS2) was fabricated. By applying positive and negative pulses, the device can imitate the excitation and inhibition behaviors of natural synapse, respectively. The baseline and change percentage of postsynaptic current (PSC) can be tuned by the back-gate bias, enabling the reconfiguration of the weight profile in machine learning. The PSC change tendency between single pulse and multiple pulse tests is opposite, which is very useful to mimic natural synapse recovery feature. Besides, as MoS2 is utilized as channel materials, the device can be vertically scaled down to 2 nm, which is very hard for traditional materials. [ABSTRACT FROM AUTHOR]