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This paper reports on the control of the direct-contact La-silicate/Si interface structure with the aim of achieving scaled equivalent oxide thickness (EOT) and small interface state density. The interface state density at the direct-contact La-silicate/Si interface is found to be reduced to 1.6 × 1011 cm-2eV-1 by annealing at 800 °C for 30 min in forming gas ambient, whereas excess silicate reaction concurrently induced a significant increase in EOT. By utilizing metal-inserted poly-Si (MIPS) stacks and their annealing at high temperature, the increase in EOT is drastically suppressed. At the same time, a superior interfacial property is obtained because the Si layer in the MIPS stacks prevents the excess oxygen diffusion from the atmosphere during the annealing process. As a result, the effective electron mobility of 155 cm2/V·s at 1 MV/cm and an EOT of 0.62 nm are successfully achieved by utilizing direct-contact La-silicate/Si structure. This result is comparable with the recorded effective electron mobility achieved by utilizing Hf-based oxides/Si structure. This demonstrates the advantage of our proposed method to realize the scaled EOT with a superior interfacial property for state-of-the-art metal-oxide-semiconductor field-effect transistors.

In this paper, we investigate the performance potentials of silicon nanowire (SNW) and semiconducting graphene nanoribbon (GNR) MOSFETs by using first-principles bandstructures and ballistic current estimation based on the ?top-of-the-barrier? model. As a result, we found that SNW-MOSFETs display a strong orientation dependence via the atomistic bandstructure effects, and SNW-MOSFETs provide smaller intrinsic device delays than Si ultrathin-body MOSFETs when the wire size is scaled smaller than 3 nm. Furthermore, GNR-MOSFETs are found to exhibit promising device performance if the ribbon width is designed to be larger than a few nanometers and a finite band gap can be established.

In this paper, we demonstrate CMOS characteristics on a Si(110) surface using surface flattening processes and radical oxidation. A Si(110) surface is easily roughened by OH- ions in the cleaning solution compared with a Si(100) surface. A flat Si(110) surface is realized by the combination of flattening processes, which include a high-temperature wet oxidation, a radical oxidation, and a five-step room-temperature cleaning as a pregate-oxidation cleaning, which does not employ an alkali solution. On the flat surface, the current drivability of a p-channel MOSFET on a Si(110) surface is three times larger than that on a Si(100) surface, and the current drivability of an n-channel MOSFET on a Si(100) surface can be improved compared with that without the flattening processes and alkali-free cleaning. The 1/f noise of the n-channel MOSFET and p-channel MOSFET on a flattened Si(110) surface is one order of magnitude less than that of a conventional n-channel MOSFET on a Si(100) surface. Thus, a high-speed and low-flicker-noise p-channel MOSFET can be realized on a flat Si(110) surface. Furthermore, a CMOS implementation in which the current drivabilities of the p-channel and n-channel MOSFETs are balanced can be realized (balanced CMOS). These advantages are very useful in analog/digital mixed-signal circuits.

This paper reports that the low-frequency noise in p-channel MOSFETs fabricated on [110] and (100) crystallographic oriented silicon is related to the microroughness of the silicon surface. Since the conventional RCA cleaning process makes the surface rough, especially in the case of [110] orientation, the authors developed the so-called 5-step room temperature cleaning process that does not use alkaline solution. The combination of this new cleaning process with the microwave-excited high-density plasma oxidation process for the formation of the gate oxide, instead of the standard 900/spl deg/C thermal oxidation process, leads to a reduction of the microroughness and a drop in the 1/f noise level of more than one decade. Furthermore, this reduction is not only observed for the [110] orientation but also seen, albeit to a much lesser extent, for (100) if it is treated in the same way.

This paper focuses attention on electrical properties of ultra-thin silicon nitride films grown by radial line slot antenna high-density plasma system at a temperature of 400/spl deg/C as an advanced gate dielectric film. The results show low density of interface trap and bulk charge, lower leakage current than jet vapor deposition silicon nitride and thermally grown silicon oxide with same equivalent oxide thickness. Furthermore, they represent high breakdown field intensity, almost no stress-induced leakage current, very little trap generation even in high-field stress, and excellent resistance to boron penetration and oxidation.

International audience; This paper presents a unified physical formulation for the avalanche effect in silicon-germanium heterojunction bipolar transistors (SiGe HBTs) at different injection levels. Based on an analytical description of the resulting electric-field distribution, a closed-form analytical expression for the multiplication factor is derived and has been implemented in the HICUM compact model. The model accuracy close to and beyond the common-emitter breakdown voltage BV CEO has been assessed over a wide temperature range in comparison to measurements of SiGe HBTs with different collector doping profiles and emitter geometries. Index Terms-Avalanche, compact model, high injection, impact ionization, kirk effect, safe operating area (SOA), silicon-germanium heterojunction bipolar transistors (SiGe HBTs).