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This paper presents a low-cost high-performance H.264/AVC SVC decoder with multi-symbol prediction context-based adaptive variable length coding (CAVLC) for advanced T-DMB receiver. Proposed multi-symbol prediction CAVLC mainly consists of a simple arithmetic operation unit with reduced look-up tables and a leading zero detector. We also propose a multi-symbol run_before decoder and it decodes more than 2.5 symbols in a cycle. Gate count of a H.264/AVC SVC decoder is about 1,300K gates when synthesized with 0.18 um CMOS process and it can be operated at 120 MHz clock frequency. For the verification of a H.264/AVC SVC decoder chip, prototype mobile movie player systems have been implemented using a 7 inch LCD and USB controller.

There has been an increased demand for realistic audio services because of the recent developments in multimedia techniques and contents. In addition, the rapid growth in wireless communications has brought about a new era of wireless multimedia applications and services such as the transmission of video, images, and data over wireless broadband access networks. Accordingly, orthogonal frequency division multiple access (OFDMA) modulation technique based on time division duplex (TDD) scheme is an attractive wireless communication technology for high data rate wireless access with multi-channel real sound system. For modulation and de-modulation of the OFDMA, inverse fast Fourier transform (IFFT) and FFT processor are used and these are most energy consuming operation in OFDMA communication systems. In this paper, we proposed a two input radix 23 single delay feedback (TIR23SDF) method to simultaneously use the IFFT and FFT in one FFT processor. We also described the architectures and the control signals for the proposed TIR23SDF. The experimental results show that the FFT processor based on proposed TIR23SDF reduce about 43.3% of the hardware complexity in the FPGA implementation.

The delivery of digital multimedia data over wireless networks enables many useful consumer applications such as home entertainment. However, there are many performance-related issues associated with the delivery of time-sensitive multimedia content over current wireless communication systems such as those using the IEEE 802.11 standards. Among the most significant issues are the high error rates, because of the media characteristics, and signal attenuation with distance. In this paper, we present a robust digital baseband processor using hybrid channel estimation for wireless home audio-video receivers operating on an IEEE 802.11g wireless local area network (WLAN). The proposed hybrid channel estimation is a combined decision-directed and pilot-assisted method for perfect channel state information (CSI). Experimental results show that the proposed method increases system performance by about 3 dB over the least squares (LS) scheme at 100-ns root mean square (RMS) delay.

To achieve better sound quality and to improve data reception, digital radio mondiale (DRM) offers a worldwide initiative to bring analog amplitude modulation (AM) radio into the digital era. DRM systems use coded orthogonal frequency division multiplexing (COFDM) modulation with a multilevel coding scheme to get high resistance to the multipath padding and interference. The bandwidth of a DRM passband signal is less than 20 kHz and the number of carriers used in orthogonal frequency division multiplexing (OFDM) modulation is relatively small. For this reason, DRM systems use non-power-of-two Fast Fourier Transforms (FFT) for OFDM demodulation, such processing gives way to more speed and power consumption in critical paths in DRM receivers. In this paper, we propose a mixed radix-2n and prime factor FFT algorithm for portable DRM receivers. Using the proposed architecture, we can reduce the processing time and energy consumption compared to conventional digital signal processor (DSP) based DRM receivers.

In this paper, a highly reliable embedded biometric smart card system with cryptography engine is proposed. We explain the system architecture of portable embedded biometric smart card reader to strengthen security for various consumer applications such as mobile cash card. Proposed biometric smart card system is embedded with 75 MHz 32-bit RISC, 6 channel smart card controller and advanced encryption system (AES) cryptography accelerator. It is devised to communicate with smart card with encrypted biometric data using international standard ISO-7816 and provides system peripherals such as LCD display controller and USB host interface. The proposed implementation shows a 70% performance improvement for decryption of protected biometric data compared to the software based smart card chipset and it is verified using 0.35 um CMOS process.

Wireless broadband (WiBro) systems can provide high data rate wireless Internet access with personal subscriber station under the stationary or mobile environment. It is the orthogonal frequency division multiple access (OFDMA) in time division duplex (TDD) system with 768 useful subcarriers over a nominal bandwidth of 8.75 MHz at 2.3 GHz band and each frame is composed of 42 OFDM symbols, corresponding to 5 ms. For modulation and demodulation in the WiBro communication system, the fast Fourier transform (FFT) processing is the most speed and power consumption critical path. In this paper, we describe 4096 points FFT and inverse FFT processor for mobile in-car entertainment systems. To obtain low complexities, small computation power and distributed memory, partially operated over-sampling architecture is developed to meet the requirement of non-stopping and high-speed data throughput. From experiment results, we can show that our methods reduce the complexity about 37.8% and it is suitable to implementation in mobile devices for WiBro consumer application which is required small area and low-power such as multimedia data service.

This paper presents a time synchronized forwarding protocol for remotely controlling home appliances connected to wireless sensor networks (WSNs) that have extremely large latency for transferring data to another node. The protocol basically uses distributed time division multiple access (TDMA) and provides scalability by a self-organization function based on a virtual sensor line. Time synchronized forwarding and self organization protocols using virtual sensor lines achieve not only low latency but also low power consumption for future consumer applications .

Power line communications provide a convenient and cost-effective solution for data transmission, because power mains are the most popular and widely distributed medium in the world. However, the time-variant and unpredictable channel environment for communication poses a major challenge. In this regard, we propose a robust power line modem based on adaptively signal detection techniques for networked home appliances. The modulation scheme used in this research is a chirped spread spectrum with a separate matched filter based on an adaptive threshold decision technique. In addition, we propose an adaptive retransmission technique based on flexible carrier frequency selection using a ram based look-up table (LUT) for improving carrier sense multiple access with collision avoidance (CSMA/CA) media access protocol. The proposed power line transceiver is realized in 0.35 mum CMOS technology and verified with networked various consumer electronic devices. The results show that the proposed power line communication modem is well qualified as a communication device for home automation .

Digital multimedia broadcasting (DMB) is a reliable multi-service system for mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using coded orthogonal frequency division multiplexing modulation (COFDM) and unequal error protection (UEP) scheme. For error correction of portable DMB receivers, punctured convolutional code and viterbi decoder is developed but it needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for viterbi decoder. This paper proposes a combined add-compare-select (ACS) and path metric normalization (PMN) unit using pre-computation technique for DMB system. The proposed PMN unit reduces the critical path by applying fixed value selection algorithm using the comparison tree properties. We also propose an ACS structure using the decomposition and pre-computation technique for reducing the complexity of the adder, comparator and multiplexer. Simulation results shows that area, gate delay and power consumption are reduced about 3.78%, 23.80%, and 12.22%, respectively.

In this paper, we present a wireless sensor node processor for emotional lighting system. Proposed wireless sensor node processor consists of an 8-bit embedded microcontroller, media access control (MAC) accelerator and digital baseband based on adaptive threshold adjustment (ATA) for enhancing the pseudo noise (PN) code acquisition. We fabricate a wireless sensor node processor using 0.18 mum CMOS technology and organize wireless sensor network for emotional lighting system. These results show it can be successfully applied in wireless sensor networks for further emotional consumer applications

In this paper, we propose embedded face recognition (FR) to use in intelligent image system. For efficient FR VLSI design, we use a feature selection and feature extraction method based on Gabor wavelets using a fast genetic algorithm (FGA). Many FR systems are based on Gabor wavelet due to its desirable characteristics of spatial locality and orientation selectivity. However, the process of searching for features with Gabor wavelet is computationally expensive and has an unusual sensibility for variations such as illumination. To overcome these problems and use in real-time applications, we optimize Gabor wavelet's parameters of translation, orientations and scales, which make it approximates a local image contour region by the use of hardware oriented FGA. From experimental results, we certify that our method shows recognition rate of over 97.27 % for FERET dataset, which exceeds the performance of the other popular methods