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This paper presents a smart and embedded multi-touch system for consumer electronics. The infrared (IR) camera is utilized to capture the coordinate of the IR blob from IR stylus or human finger in an emitted IR field. This system allows the consumer to easily convert large surface, projector screen, or conference table into multi-touch interface. The keystone distortion of IR camera is compensated by using homography. To improve the user experience, the calibration of homography is automatically triggered by accelerometer sensor. The special purpose (SP) processor with the parallel COordinate Rotation Digital Computer (CORDIC) architecture computes the observation-to-track association, and the computation result updates the motion status of each tracked trajectory. These motion data support the multi-touch tracking system to evaluate the sliding window of each tracked trajectory for reducing the tracking error. Additionally, the motion data are reused by the adaptive trajectory estimation (TE) system to smooth the touch trajectory and mitigate the measurement noise. This research presents multiple autonomous functions to provide a user-friendly multi-touch interface for consumer electronics. These include the automatic calibration system, the multi-touch tracking architecture with motion estimation system, and the adaptive TE system. [ABSTRACT FROM AUTHOR]

This paper presents hardware-friendly algorithm for Gini-index (GI) cooperative-spectrum-sensing (CSS) algorithm for the data-fusion based cooperative cognitive-radio network. It simplifies the complex computations of sample-covariance-matrix (SCM) elements and test-statistics value of the conventional GI-based CSS algorithm. It delivers excellent detection performance under the realistic scenario of non-uniform dynamical noise and signal-power. Based on GI-based CSS algorithm, three different VLSI architectures are proposed for the cooperative spectrum sensor (CSR): CSR-VLAR1, CSR-VLAR2, and CSR-VLAR3. Here, CSR-VLAR1 is the first-time reported CSR-architecture for the conventional GI-based CSS algorithm. Subsequently, CSR-VLAR2 represents hardware-architecture of the proposed hardware-friendly GI-based CSS algorithm. Eventually, additional architectural optimization has been applied to CSR-VLAR2 that is transformed into the most hardware-efficient VLSI-architecture of CSR, referred as CSR-VLAR3, which is ASIC chip-fabricated in UMC 130 nm-CMOS technology node. Furthermore, both CSR-VLAR1 and CSR-VLAR2 are synthesized and post-layout simulated in the same technology node. Our ASIC-chip of CSR-VLAR3 occupies 0.35 mm2 of core-area and consumes 8.31 mW of total power at 88.8 MHz of maximum clock frequency, when the supply voltage is 1.2 V. Our CSR ASIC-chip has been functionally verified with the aid of real-world signals, using USRPs and FPGAs based test-setup of cooperative cognitive-radio network. Measured results of our design are compared with reported implementations where the proposed CSR is $4.52\times $ hardware-efficient and $2.8\times $ power-efficient than the state-of-the-art CSR-implementations. Thus, our work addresses the key challenge of designing hardware-efficient CSR that delivers excellent detection performance in the real-world scenario. [ABSTRACT FROM AUTHOR]

Digital signal processing (DSP) kernels-based intellectual property cores are important components of modern consumer electronics. However, hardware threats such as reverse engineering and Trojan insertion have raised serious concerns about the protection of DSP kernels. Structural obfuscation is one of the protection mechanisms that make DSP design architecture un-obvious to interpret, thereby making it harder to reverse engineer. A novel methodology is presented in this paper called “hologram-based structural obfuscation” for protection of DSP kernels. The proposed hologram-based obfuscation integrates two DSP kernel architectures in a camouflaged fashion without change of functionality of each DSP kernel, such that it becomes complex and un-interpretable to an adversary. This approach of simultaneous protection of two DSP kernels via hologram obfuscation is presented first time in the literature. We propose multiple robust obfuscation algorithms in this paper to design hologram-based obfuscated designs and demonstrate using popular DSP kernels. Proposed approach is compared with a recent work on protecting DSP kernels and experimental results indicate that proposed approach yields significantly lesser area and stronger obfuscation. Results of proposed obfuscation on DSP kernels achieve approximately 33.5% reduction in gate count and ~14 times stronger obfuscation than recent work. [ABSTRACT FROM AUTHOR]

In this paper, a novel low bit-depth representation-based motion estimation approach with its hardware architecture is presented. The low bit-depth representation of pixels in the proposed method is constructed by choosing them from the gray-coded bit planes in an efficient way. Additionally, a new matching creation is also presented to improve the motion estimation accuracy. Thanks to the proposed binarization approach, the computation load is considerably reduced compared to filtering-based low bit-depth representation motion estimation methods. A novel hardware architecture for the proposed method is also presented in this paper. Experimental results revealed that the proposed motion estimation method and its hardware architecture provides a good balance between motion estimation accuracy and hardware resources especially for consumer electronics applications. [ABSTRACT FROM AUTHOR]

This paper presents a new cloud computing model for context-aware Internet of Things services. The proposed computing model is hierarchically composed of two layers: a cloud control layer (CCL) and a user control layer (UCL). The CCL manages cloud resource allocation, service scheduling, service profile, and service adaptation policy from a system performance point of view. Meanwhile, the UCL manages end-to-end service connection and service context from a user performance point of view. The proposed model can support nonuniform service binding and its real-time adaptation using meta-objects. Furthermore, it supports intelligent service-context management using a supervised and reinforcement learning-based machine learning framework. We implemented a lightweight prototype of the proposed computing model. Evaluations confirm that the proposed computing model offers enhanced performance compared with legacy uniform computing models. [ABSTRACT FROM AUTHOR]

The emergence of the Internet of Things (IoT) has led to increasing data volumes, which are expected to grow exponentially. The IoT has great potential to positively change society but also presents challenges regarding privacy. In practice, Smart community public housing projects involving tens of thousands of households have recently been implemented. This study proposed a privacy-preserving smart home system, which connects a single home controller with data-hiding capabilities through community networking and integrates the data to a hierarchical architecture on a cloud platform for a data analytical access control mechanism. In addition, this paper outlines a variety of smart home data applications through data collected from a smart community environment with the developed privacy protection mechanism. The monitoring and protecting mechanism combines privacy-enhancing technologies with a privacy-preserving strategy from the initial system-designing stage through to full data lifecycle management. The types of smart home data that can be obtained from a community hierarchy, such as identification values, sensitive data, and non-sensitive data, were collected and classified. Through a combination of empirical application and sophisticated exploration of theoretical knowledge, this paper substantially contributes to the home automation field. The proposed system architecture is expected to enable both easy understanding for users and compliance for analytical service providers regarding the operation, procedure, limitation, and benefits of smart home data analysis, thereby providing a solution that ensures both privacy and data availability. [ABSTRACT FROM PUBLISHER]

In recent years, various mobile terminals equipped with NFC (Near Field Communication) have been released. The combination of NFC with smart devices has led to widening the utilization range of NFC. It is expected to replace credit cards in electronic payment, especially. In this regard, security issues need to be addressed to vitalize NFC electronic payment. The NFC security standards currently being applied require the use of user's public key at a fixed value in the process of key agreement. The relevance of the message occurs in the fixed elements such as the public key of NFC. An attacker can create a profile based on user's public key by collecting the associated messages. Through the created profile, users can be exposed and their privacy can be compromised. In this paper, we propose conditional privacy protection methods based on pseudonyms to solve these problems. In addition, PDU (Protocol Data Unit) for conditional privacy is defined. Users can inform the other party that they will communicate according to the protocol proposed in this paper by sending the conditional privacy preserved PDU through NFC terminals. The proposed method succeeds in minimizing the update cost and computation overhead by taking advantage of the physical characteristics of NFC1. [ABSTRACT FROM PUBLISHER]

Low power realization of high efficiency video coding (HEVC) standard, which has found widespread application in mobile devices, tablets, and high-definition televisions, calls for an efficient approximation of discrete cosine transform (DCT) technique. In this paper, a novel algorithm is proposed to determine the minimum number of low-frequency DCT coefficients required for transform and quantization block in HEVC. Moreover, it introduces hardware efficient 1-D architectures for 4, 8, 16, and 32-point DCT, that make use of the proposed algorithm and conform to the HEVC standard. When these architectures are extended to the HEVC test model (HM), it leads to a minor reduction of PSNR (<0.15 dB) and a slight increase in bitrate (<1.5%). The encoding time of HM encoder is reduced up to 16.02% and produces the rate-distortion performance comparable to the reference algorithm. A new memory efficient addressing scheme for transpose memory is presented for 2D-DCT. The proposed 2D-DCT architecture has a low power dissipation and energy consumption of 8.62 mW and 1.77 pJ respectively and can process at least sixty 8K ($7630\times 4830$) frames/s. Such architecture with low power and energy characteristics can be integrated into a real-time HEVC encoder for portable consumer electronic products. [ABSTRACT FROM AUTHOR]

Given the large amount of devices in the Internet of Things (IoT), a major challenge is to efficiently find services that meet specific requirements. The proliferation of standards and protocols precludes the existence of a common nomenclature to describe IoT devices, and hence hinders device interoperability. In the previous work, we had proposed the Swarm, a framework to create a common interface for IoT devices. The Swarm provides a software agent to facilitate the decentralized communication and interaction of devices, constituting a step toward interoperability in the IoT. Semantic technologies have been successfully used for service discovery in business applications, and more recently are being used to solve interoperability problems in the IoT. This paper aims to propose a framework to enable semantic discovery in the Swarm. We provide an architecture and describe a reference implementation, based on open Web technologies. We also provide a method to validate our results and propose future directions of this paper. [ABSTRACT FROM AUTHOR]

This paper presents a novel architecture designed for low power consumption, in which low computational complexity and reliability have also been important design constraints. It is suitable for sensor-actuator systems, is based on IEEE 802.15.4 and constitutes a more lightweight alternative than Zigbee. We provide a vision of how we have solved some problems that are out of the scope of IEEE 802.15.4 like addressing scheme, topology control, multi-hop synchronization, tasks scheduling, application data model, and other points related to software and hardware considered to extend the battery life. We have designed a centralized method for scheduling the beacon transmission time. Unlike the distributed one used by Zigbee, our method avoids beacon overlapping in any case and does not require the publication of information in the beacon payload. The proposed addressing scheme also does not require the publication of the depth of coordinators. Both methods allow us to implement efficient algorithms, reduce the memory used to store the network tables, and shorten the beacon payload, what entails a significant energy saving. These solutions together with others presented in this paper allow us to reach a battery life longer than 31 months for sensors and 42 months for actuators. [ABSTRACT FROM AUTHOR]

Motion Estimation (ME) is the most power consuming module in the video encoder due to its high computational complex operations. So designing an efficient ME hardware without losing coding performance is a major challenge. This paper proposes a low-bit-depth ME technique based on Gray-Coded bit-planes and its hardware implementation using Binary Content Addressable Memory (BCAM). The proposed method significantly reduces the computational burden due to its low-bit-depth representation. The novel BCAM based ME hardware provides faster results because of its on-chip memory computation without compromising other performance parameters. It can process 8K @53.71 fps operated at maximum frequency of 155 MHz with 152.78K NAND equivalent gate count using 90 nm technology library. [ABSTRACT FROM AUTHOR]

Motion Estimation (ME) is the most computationally intensive block in high efficiency video coding (HEVC) due to its complex partition schemes. It consumes a large amount of power in the encoder. So designing a ME module on hardware platform imposes significant challenges. Many hardware oriented integer ME (IME) algorithms have been proposed in the literature to meet the challenges but suffer from coding efficiency degradation. In this paper we propose a low complexity IME algorithm and its hardware implementation. The proposed algorithm has been shown for two different pattern structures (PS) with 38 search points. It achieves bjontegaard bitrate (BD-BR) of 0.5% decrease and 0.077% increase for two PSs compared to test zone search (TZS) in HM 16.8. It results 8.725% and 9.072% saving in encoding time respectively. The proposed architecture supports all the HEVC partitions. It provides real time encoding of 4096 $\times $ 2160 @60 fps operated at the maximum frequency of 353 MHz with 1591 K NAND equivalent gate count and 8.32 kB on chip memory using 90 nm technology library. Therefore, it can be used in consumer electronics applications such as security surveillance, video recording systems etc. that require high efficient HEVC encoder. [ABSTRACT FROM AUTHOR]

Today, an ever-increasing number of devices has networking capability. The main implication of this fact is that such devices are often left fully powered yet idle just to maintain their network presence, hence leading to large energy waste. This ultimately results in higher electricity cost for consumers. This paper tackles an effective mechanism to reduce energy waste of consumer electronics, by boosting the usage of lowpower states available in most devices. The main concept is to delegate background networking routines to home gateways, which are today available in most homes and offices. The paper describes the functionality and the software architecture to be implemented by home gateways and consumer electronics, reports performance evaluation on a working prototype, and provides estimation of potential benefits for consumers. [ABSTRACT FROM AUTHOR]

This paper aims to design an efficient mixed serial five-stage pipeline processing hardware architecture of deblocking filter (DBF) and sample adaptive offset (SAO) filter for high efficiency video coding decoder. The proposed hardware is designed to increase the throughput and reduce the number of clock cycles by processing the pixels in a stream of 4 \times 36 samples in which edge filters are applied vertically in a parallel fashion for processing of luma/chroma samples. Subsequently these filtered pixels are transposed and reprocessed through vertical filter for horizontal filtering in a pipeline fashion. Finally, the filtered block transposed back to the original orientation and forwarded to a three-stage pipeline SAO filter. The proposed architecture is implemented in field programmable gate array and application specific integrated circuit platform using 90-nm library. Experimental results illustrate that the proposed DBF and SAO architecture decreases the processing cycles (172) required for processing each 64 \times 64 or large coding unit compared with the state-of-the-art literature with the increase of gate count (593.32K) including memory. The results show that the throughput of the proposed filter can successfully decode ultrahigh definition video sequences at 200 frames/s at 341 MHz. [ABSTRACT FROM PUBLISHER]

Data compression is commonly used in NAND flash-based solid state drives (SSDs) to increase their storage performance and lifetime as it can reduce the amount of data written to and read from NAND flash memory. Software-based data compression reduces SSD performance significantly and, as such, hardware-based data compression designs are required. This paper studies the latest lossless data compression algorithm, i.e., the Lempel-Ziv (LZ)4 algorithm which is one of the fastest compression algorithms reported to date. A data compression FPGA prototype based on the LZ4 lossless compression algorithm is studied. The original LZ4 compression algorithm is modified for real-time hardware implementation. Two hardware architectures of the modified LZ4 algorithm (MLZ4) are proposed with both compressors and decompressors, which are implemented on an FPGA evaluation kit. The implementation results show that the proposed compressor architecture can achieve a high throughput of up to 1.92 Gb/s with a compression ratio of up to 2.05, which is higher than all previous LZ algorithm designs implemented on FPGAs. The compression device can be used in high-end SSDs to further increase their storage performance and lifetime. [ABSTRACT FROM PUBLISHER]

As Internet Protocol Television (IPTV) has become one of the major Internet applications, IPTV users increase rapidly and hundreds of channels emerge to satisfy users' demands. However, the increased number of channels makes users difficult to find their desired channels. Along with this problem, the channel zapping time of IPTV incurs serious user-perceived delay. To alleviate these problems, this paper presents hybrid schemes that combine channel prefetching and reordering schemes. Specifically, adjacency and popularity based prefetching schemes are combined with popular channel reordering schemes and their performances are simulated under various conditions. Experimental results show that the proposed schemes reduce the channel seek time by up to 44.7% when up-down channel selection interfaces are used. [ABSTRACT FROM AUTHOR]

In this paper, efficient optimal post-process/in-loop filtering in video coding is presented by applying two separate one-dimensional filters to significantly decrease the computational load of the optimal filtering process at the expense of only a slight quality loss. Furthermore, the compression of filter coefficients is evaluated using a Golomb-Rice (GR) coding approach together with differential encoding. Experimental results show that the proposed one-dimensional processing approach reduces the computational complexity by at least 4 times compared to the formerly proposed two-dimensional optimal filtering case and enables real-time implementation. It is furthermore shown that, the filter coefficients can be compressed by up to 40% if GR coding is used together with differential encoding. [ABSTRACT FROM AUTHOR]

This paper describes a framework for establishment of UWB multi-hop ad hoc networks to improve the efficiency of standard-based multi-hop extension by constructing child or neighbor piconets. Bridge devices (BDEVs) are selected from usual devices with one single network interface by a bridge selection protocol. BDEV is a member of each interconnected piconet. Then, BDEVs are used to build the multi-piconet networks. Each piconet associated with a BDEV follows the 802.15.3 standard. Furthermore, distributed and centralized scheduling schemes are proposed to improve the performance of the scatter ad hoc networks. The distributed schemes are simple and flexible. However, the centralized scheme could achieve better scheduling efficiency. Through simulations, the proposed BDEV scheduling schemes are shown to be effective to extend network coverage in UWB home networks'. [ABSTRACT FROM AUTHOR]

This paper proposes the architecture of multiple ensemble service in DAB network, in which they can transmit and receive more than one ensemble through multiple transmitters, which covers the same service area. Using this architecture, ensemble providers and transmission network providers can have more flexible management environment of DAB networks as well as they can accommodate more than 1.5 Mbps data capacity limit of one ensemble. [ABSTRACT FROM AUTHOR]

Versatile video coding (VVC) will be the next generation video coding standard, which is expected to replace HEVC in CE devices, such as tablets, smartphones, and TV sets beyond 2020. The new standard will still be based on transform, quantization, and entropy coding, but a multiple transform selection scheme has been proposed, involving three different types of 2-D Discrete Sine/Cosine transforms (DCT-II, DCT-VIII, and DST-VII), and the transform unit sizes range from $4\times 4$ to $64\times 64$. To handle the computational complexity of these algorithms, it is useful to explore hardware solutions that could be employed as accelerators. In this paper, a high performance architecture to implement the aforementioned 2-D transform types for $4\times 4$ , $8\times 8$ , $16\times 16$ , and $32\times 32$ sizes is proposed. The design has been synthesized for low, medium, and high-end FPGA chips, being able to process up to 23 fps@ $3840\times 2160$ for $32\times 32$ transform sizes and up to 86 fps@ $3840\times 2160$ for pictures containing an even distribution of the four block sizes. Moreover, these performance results have been obtained with a moderate consumption of hardware resources. [ABSTRACT FROM AUTHOR]

The increasing growth of Internet of Things (IoT) applications induces the need for easy integration of third-party peripherals, which is restricted in present IoT devices. In this paper, we present a novel plug-and-play (PnP) solution for the above stated problem. The proposed PnP solution, named SensPnP, is the combination of embedded hardware and firmware that has the capability of integrating third-party embedded sensors with the IoT devices without any prior information about the sensors and the Internet. We present an architecture of a PnP-enabled IoT device, which supports heterogeneous embedded peripheral communication protocols. A novel embedded protocol detection approach for enabling seamless integration of sensor with IoT device is proposed. To enable sensor communication, we propose an algorithm for automatic driver management of the connected sensor with an IoT device. This is achieved through a low-cost and low power switching and identification hardware with a light-weight identification and driver management firmware stack. To show the effectiveness of the proposed solution, we practically implemented a prototype in a real test-bed. The analysis of the PnP time, protocol identification time, the memory footprint, lifetime, and overall cost of the proposed PnP solution under different operating conditions establishes superiority of its circuitry and firmware. Experimental results show that SensPnP requires minimal memory footprint, reduced energy consumption, and reduced PnP time compared to the existing solutions. Additionally, the overall cost analysis shows that the cost of SensPnP is noticeably less compared to existing solutions. Thus, the cost-efficiency of SensPnP makes it more acceptable to the consumers when compared with existing solutions. [ABSTRACT FROM AUTHOR]

In the home cloud environment, the storage performance of home cloud servers, which govern connected devices and provide resources with virtualization features, is critical to improve the end-user experience. To improve the storage performance of virtualized home cloud servers in a cost-effective manner, caching schemes using flash-based solid state drives (SSD) have been widely studied. Although previous studies successfully narrow the speed gap between memory and hard disk drives, they only focused on how to manage the cache space, but were less interested in how to use the cache space efficiently taking into account the characteristics of flash-based SSD. Moreover, SSD caching is used as a read-only cache due to two well-known limitations of SSD: slow write and limited lifespan. Since storage access in virtual machines is performed in a more complex and costly manner, the limitations of SSD affect more significantly the storage performance. This paper proposes a novel SSD caching scheme and virtual disk image format, named sequential virtual disk (SVD), for achieving high-performance home cloud environments. The proposed techniques are based on the workload characteristics, in which synchronous random writes dominate, while taking into consideration the characteristics of flash memory and storage stack of the virtualized systems. Unlike previous studies, SSD is used as a read-write cache in the proposed caching scheme to effectively mitigate the performance degradation of synchronous random writes. The prototype was evaluated with some realistic workloads, through which the developed scheme was shown to allow improvement of the storage access performance by 21% to 112%, with reduction in the number of erasures on SSD by about 56% on average. [ABSTRACT FROM AUTHOR]

High Efficiency Video Coding (HEVC) intra mode decision algorithm has very high computational complexity. Therefore, in this paper, a computation and energy reduction technique is proposed for reducing the amount of computations performed by Sum of Absolute Transformed Difference (SATD) calculations in HEVC intra mode decision, and therefore reducing the energy consumption of HEVC SATD calculation hardware without any PSNR loss and bit rate increase. The proposed technique reduced the energy consumption of HEVC SATD calculation hardware up to 64.6%. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder. [ABSTRACT FROM PUBLISHER]

High-quality videos like high-definition (HD) and ultra HD became an essential requirement in recent applications such as security surveillance, television system, etc. However, due to increase in resolution of the videos, the volume of visual information data increases significantly, which became a challenge for storage, transmission and processing the HD video data. The new video compression standard, high efficient video coding (HEVC), achieved two-fold video efficiency improvements as compared to H.264/AVC using efficient compression techniques. Motion estimation (ME) is one of the computationally intensive blocks in video CODEC. In HEVC, the complexity of ME further increases due to a large processing unit and flexible partitioning of the prediction unit (PU). In this paper, we proposed a low power ME algorithm and architecture of the HEVC for consumer applications. The proposed algorithm and architecture utilizes sub-sampling, data reuse, pixel truncation and adaptive search range techniques for reducing the computational power. Simulations result shows that the proposed ME algorithm requires an average of 53.82% fewer search points as compared to the reference software HM with a small degradation in PSNR and little increment in bit-rate. The proposed architecture is simulated and synthesized using standard 90 nm technology. The proposed ME architecture can process $3840\times2160$ @ 30 fps video sequences with only 4.5193 mm2 of the area and 8.192 KB of SRAM. The operating frequency of the proposed architecture is 250 MHz with 151.7619 mW of power. [ABSTRACT FROM AUTHOR]

A novel approach for obfuscated JPEG compression/decompression (CODEC) IP core design methodology, suitable for use in re-usable IP core designs, is presented. This incorporates structural obfuscation for architecture or structure hiding from an adversary in order to maximize the complexity against reverse engineering. Additionally, the proposed methodology performs the entire compression and decompression through a single dedicated hardware IP core. To obtain a lightweight (low cost version) of the proposed obfuscated JPEG CODEC IP, particle swarm optimization driven design space exploration is employed. Results of the proposed low cost, obfuscated JPEG CODEC IP core design when compared to un-protected (un-obfuscated) design yielded enhancement in strength of obfuscation of 76%, as well as reduction of 5% compared to un-optimized design. [ABSTRACT FROM AUTHOR]

Future video coding (FVC) will be the next generation video coding standard. Yet in the first stages of the standardization process, it is expected to replace high efficiency video coding beyond 2020. One of the enhancements in discussion is the adaptive multiple core transform, which uses five different types of 2-D discrete sine/cosine transforms (DCT-II, DCT-V, DCT-VIII, DST-I, and DST-VII) and up to 64 \times 64 transform unit sizes. This schema, increases the computational complexity of both, encoder and decoder. In this paper, a deeply pipelined high performance architecture to implement the five transforms for 4 \times 4 , 8 \times 8 , 16 \times 16 , and 32 \times 32 sizes is proposed. The design has been described in VHDL and it has been synthesized for different Field-programmable gate array chips, being able to process up 182 fps @ 3840\times2160 for 4 \times 4 transform sizes. Up the best of our knowledge, this is the first implementation of an architecture for the FVC Adaptive Multiple Core Transform supporting 4 \times 4 , 8 \times 8 , 16 \times 16 , and 32 \times 32 sizes. [ABSTRACT FROM PUBLISHER]

In order to render 3-D graphics efficiently, rasterization techniques have been developed. Traditional clipping techniques using six-planes of view volume are complicated and not cost-effective. This paper develops a novel cost-effective strategy for primitives with regard to clipping in rasterization. Throughout the process, no expensive clipping action is required and no extra clipping-derived polygons are produced. It also presents the architecture of a 200-MHz multicore, multi-thread 3-D graphics SoC in 65nm 1P9M process with a core size of 4.97mm2 and 153.3mW for power consumption. The proposed clip-less architecture in rasterization processes the valid screen space region of each primitive in eight cycles, with a gate-count of only 20k. In addition, the throughput can achieve up to 25 M Triangles/Sec. [ABSTRACT FROM PUBLISHER]

According to the recent studies on the smartphone performance analysis, the primary performance bottleneck of smartphones is storage systems rather than wireless networks or processors. The key reason behind this undesirable result is the journaling function of a lightweight database library used by various smartphone applications. This paper quantifies the overhead of journaling on the performance of smartphones and presents a novel storage architecture that eliminates this overhead by using nonvolatile memory technologies. Specifically, the proposed architecture adopts a new journaling scheme that provides high storage performance of smartphones without any loss of reliability. The prototype of the proposed architecture has been implemented on the mobile platform based on Linux. Measurement studies with smartphone benchmarks show that the proposed journaling architecture improves the storage performance by 20-278% compared to original journaling. Performance studies with real applications such as internet games, video players, and web browsers also show that the performance improvement is in the range of 23-69%. [ABSTRACT FROM PUBLISHER]

In many consumer electronics such as digital camcorders, notebooks, and tablet PCs, hard disk drive (HDD) has been replaced with NAND flash memory based solid state disk (SSD) because of its fast speed and low power consumption. However, since SSD inherits the limitations of NAND flash memory such as erase-before-write architecture and asymmetric read, write, and erase speeds, it may result in severe performance degradation to implement a B-tree on SSD. To address these problems, several methods exploiting the buffer have been proposed so far. However, they have faced with the recovery problem because all index data in the buffer are lost when a sudden power-off occurs. In this paper, we introduce a method called RMSS (recovery management scheme on SSD) that supports an efficient recovery mechanism when a B-tree is built on SSD. Since RMSS flushes all index data and creates a checkpoint whenever updating the root node, it can stably restore the index structure into up-to-date and consistent state. Consequently, RMSS efficiently implements a B-tree on SSD by using a buffer, and also recovers the original B-tree when a power failure occurs. We show the performance of RMSS on SSD through various experiments1. [ABSTRACT FROM PUBLISHER]

Remote home care, enabled by Information and Communication Technologies, plays an important role in the delivery of pervasive health services. One of the most challenging drivers in the deployment of pervasive health care solutions is the population ageing phenomenon. In this paper, we present a wireless, home-centered, health monitoring system architecture that can efficiently manage medical devices in a blind manner, i.e. with very little or no action required by the user, in such a way as to be possibly targeted to elderly people. The Open Services Gateway initiative (OSGi) framework is used for constructing the service oriented architecture, according to a Declarative Services paradigm. The proposed architecture has been deployed in a prototype implementation, and some preliminary results are herein discussed. [ABSTRACT FROM AUTHOR]

The paper describes a Software Defined Radio architecture that simultaneously demodulates all radio stations in the Frequency Modulated (FM) band, and is intended as a preprocessor for content and metadata indexing applications. The system, which contains an overlap-add type channelizing filterbank and a massively parallel frequency demodulation block, is implemented in a single Field- Programmable Gate Array, thus offering the possibility of replacing more traditional media indexing installations containing tens of individual receivers. It is believed to be the first single chip full-band channelization system intended for consumer broadcast media indexing applications. Chip resource utilization details and experimental results from the developed system are also presented. [ABSTRACT FROM AUTHOR]

Flash memory is widely used in mobile consumer electronics devices due to its good properties such as small size, shock resistance, and low-power consumption. However, the cost of flash memory is still high to accommodate ever-growing mobile applications and multimedia contents. Using MLC (multilevel cell) technologies is an efficient solution to extend the storage capacity, but it degrades the performance of flash memory significantly compared to the original storage based on SLC (single-level cell) technologies. To bridge the characteristics of the two technologies, this paper presents a new buffer cache management scheme that uses both MLC and SLC together and considers their heterogeneous characteristics. By allocating cache space based on the characteristics of each storage media as well as I/O operation types and reference history of buffered blocks, the proposed scheme improves the I/O performance of mobile systems by 24% on average and up to 180% compared to the CLOCK algorithm. Moreover, it guarantees high reliability of file data by adopting recently emerging non-volatile RAMs in a certain portion of the buffer cache. [ABSTRACT FROM AUTHOR]

VNC (virtual network computing) is a popular tool for sharing an application, allowing users to access graphic displays remotely. In mobile VNC systems, it has been challenging to increase screen update rate by fast screen image encoding. In this paper, we implement a prototype system for mobile VNC, and several works are done for improving screen update rate. At first, a number of video encoders are integrated into a prototype system, and we investigate what is the most suitable codec for mobile VNC. The existing RFB protocol is extended straightforwardly to integrate video codecs. Next, the overall system architecture is modified from serial operation to parallel. Finally, we propose a modified region coding to further reduce the encoding time of screen images. The proposed methods are implemented into our prototype mobile VNC system, and practical performances are widely evaluated. We report that JPEG is the most suitable for mobile VNC in terms of both complexity and compression ratio. In addition, the proposed modified region coding can decrease encoding time, and consequently increase screen update rate. [ABSTRACT FROM AUTHOR]

Recent advance in per-cell bit density and semiconductor technology for NAND flash memories have led to significant cost reduction in non-volatile storage implementation. However, the reliability of data stored in flash memory has dramatically decreased, requiring an efficient mechanism to detect and correct bit errors during read and write operations of the data. For this purpose, when user data are often written into a flash page, an Error Correction Code (ECC) for the data is generated and stored in the spare area of the page. ECCs tend to become longer to correct more bit errors, sometimes beyond what is affordable by the spare area. In order to cope with this problem, there have been many attempts to keep ECCs in the data area, as opposed to the spare area of the flash memory. However, an additional mapping mechanism is required to locate ECCs for a given data page, and the program time and cycle are increased due to reading/storing the ECCs. In this paper, we present a novel ECC management mechanism with an assist from PCM for NAND flash storage systems. This technique uses PCM as a temporal storage to store ECCs for the data in log blocks. Later, the pages in log blocks are merged into data blocks with their ECCs kept in the PCM. Our experimental results show that the overhead from ECC management has been improved by 57% and 69% over previous attempts in BAST and FAST mapping schemes, respectively. [ABSTRACT FROM PUBLISHER]

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose high performance systolic hardware architectures for 1BT based fixed block size (FBS) single reference frame (SRF) ME, variable block size (VBS) SRF ME, and multiple reference frame (MRF) ME. The proposed FBS-SRF ME hardware performs full search ME for 4 Macroblocks in parallel and it is faster than the 1BT based ME hardware reported in the literature. In addition, it uses less on-chip memory than the previous 1BT based ME hardware by using a novel data reuse scheme and memory organization. The proposed VBS-SRF ME hardware is also faster and uses less on-chip memory than previous 1BT based VBS-SRF ME hardware. The proposed MRF ME hardware is the first 1BT based MRF ME hardware in the literature. In order to trade-off ME performance and computational complexity, the proposed MRF ME hardware is designed as reconfigurable in order to statically configure the number and selection of reference frames based on the application requirements. The proposed hardware architectures are implemented in Verilog HDL. They are capable of processing 83 1920x1080 full High Definition frames per second. Therefore, they can be used in consumer electronics products that require real-time video processing or compression. [ABSTRACT FROM AUTHOR]

This paper introduces a lightweight architectural solution for discovery, monitoring and management of nodes, services and resources in smart spaces composed of low capacity nodes. A wireless sensor network software architecture is used as the baseline and is extended to a scalable smart space architecture. Discovery, monitoring and management tasks are realized by means of a Resource Manager that acts as just another node. The proposed architecture is deployed on physical wireless sensor nodes. Experimental results show that the proposed smart space architecture is indeed lightweight and suitable for very low capacity nodes. [ABSTRACT FROM AUTHOR]

Recently PRAM (Phase-change RAM) is emerging as a promising next generation non-volatile memory device, because it supports fast byte-level access capability and in-place update (no erase-before-program constraint) unlike traditional NAND Flash. Although this PRAM technology is not matured yet, in terms of capacity and write performance, we expect that using this PRAM with traditional NAND Flash enables us to design high-performance and low cost storage for consumer electronics. So in this paper, we introduce a PRAM and NAND hybrid storage design as a practical approach. To this end, we first define a hybrid storage architecture, and then design a hybrid FTL (Flash Translation Layer) and a hybrid FAT filesystem. Finally, we demonstrate that our proposed hybrid storage solution enhances the storage performance 6 times faster and lifetime 6.4 times longer, on the average. [ABSTRACT FROM AUTHOR]

There has been an increased demand for realistic audio services because of the recent developments in multimedia techniques and contents. In addition, the rapid growth in wireless communications has brought about a new era of wireless multimedia applications and services such as the transmission of video, images, and data over wireless broadband access networks. Accordingly, orthogonal frequency division multiple access (OFDMA) modulation technique based on time division duplex (TDD) scheme is an attractive wireless communication technology for high data rate wireless access with multi-channel real sound system. For modulation and de-modulation of the OFDMA, inverse fast fourier transform (IFFT) and FFT processor are used and these are most energy consuming operation in OFDMA communication systems. In this paper, we proposed a two input radix 23 single delay feedback (TIR23SDF) method to simultaneously use the IFFT and FFT in one FFT processor. We also described the architectures and the control signals for the proposed TIR23SDF. The experimental results show that the FFT processor based on proposed TIR23SDF reduce about 43.3% of the hardware complexity in the FPGA implementation. [ABSTRACT FROM AUTHOR]

The practical applications of wireless sensor networks require the sensor devices to be high in computation ability, low in power consumption, small in size, as well as competitive in cost. In addition, there are other particular attributes which require special consideration in sensor device design. These include, for example, the capabilities in protecting the embedded program from foreign intrusion and supporting efficient air-programming, which are very common requirements in many large-scale applications. In this paper, we describe the system architecture and design methodology of an ASCI-based sensor network device to meet those attributes for a class of applications. Compared with existing works, the unique features of the sensor device include: (1) a module- based extensible processor and co-processor cooperation architecture is designed with application-specific components to accelerate the signal collection, processing, and networking via hardware-software co-design to balance computation efficiency and design flexibility; (2) a program protection mechanism is developed based on unresemble coder algorithm to protect the program data from being read out by system intruders so as to improve the security of the sensor device; (3) an air- programming component is proposed to enable an efficient remote programming which is a very common requirement in network deployment and maintenance. In this paper, we present the design, implementation, and evaluation of the prototype sensor device based on a general configurable FPGA platform for developing next-generation sensor devices. Initial results of the first version of prototype chip will also be introduced. [ABSTRACT FROM AUTHOR]

In this paper, we present a unified architecture that can perform Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform (IDCT), DCT domain motion estimation and compensation (DCT-ME/MC). Our proposed architecture is a Wavefront Array-based Processor with a highly modular structure consisting of 8×8 Processing Elements (PEs). By utilizing statistical properties and arithmetic operations, it can be used as a high performance hardware accelerator for video transcoding applications. We show how different core algorithms can be mapped onto the same hardware fabric and can be executed through the pre-defined PEs. In addition to the simplified design process of the proposed architecture and savings of the hardware resources, we also demonstrate that high throughput rate can be achieved for IDCT and DCT-MC by fully utilizing the sparseness property of DCT coefficient matrix. [ABSTRACT FROM AUTHOR]

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose high performance systolic hardware architectures for 1BT based fixed block size (FBS) and variable block size (VBS) ME. The proposed ME hardware architectures perform full search ME for 4 Macroblocks in parallel and they are faster than the 1BT based ME hardware reported in the literature. They use less on-chip memory than the previous IBT based ME hardware by using a novel data reuse scheme and memory organization. The proposed VBS ME hardware is the first 1BT based ME hardware implementing VBS ME. The proposed hardware architectures are implemented in Verilog HDL. The FBS ME and VBS ME hardware consume %34 and %49 of the slices in a Xilinx XC2VP30-7 FPGA, respectively. They can work at 113 MHz in the same FPGA and are capable of processing 49 1920x1080 full High Definition frames per second. Therefore, they can be used in consumer electronics products that require real-time video processing or compression. [ABSTRACT FROM AUTHOR]

Variable block-size motion estimation (VBSME) has become an important technique in H.264/A VC to improve video quality. In this paper, we propose a scalable VLSI architecture for VBSME in H.264/A VC based on a full-search motion estimation algorithm. A new scan order is introduced to re-use the sum of absolute differences (SAD) values of smaller sub-blocks on an "as-early-as-possible" basis, thus the complexity of the required hardware resources, such as registers, multiplexers, and controls is reduced. It also spreads the timing for the final SAD outputs so that the number of output buses is reduced. The architecture is flexible and scalable with regard to the size of the searching windows and PE arrays. Compared to the conventional approaches, the architecture shows higher throughput rate with less hardware. After logic synthesis using DongbuAnam 0.18 μm standard cell library, the number of gates is 39K (16 PEs) in two-input equivalent NAND gates and the maximum operating clock frequency is 416 MHz (256 fps@CIF). [ABSTRACT FROM AUTHOR]

This paper presents an efficient architecture for computing the eight-point ]-D scaled DCT (Discrete Cosine Transform) with a new algorithm based on a selected Loeffier DCT scheme whose multiplications are placed in the last stage. The proposed DCT architecture does not require any scaling compensation in the computation. Furthermore, a multiplication approximation method is developed, which is more efficient than traditional CORDIC (Coordinate Rotation Digital Computer) -based algorithms. Compared to the latest work [8], the proposed approach can save 14% addition operations for the same precision requirement and the path delay can be significantly reduced as well. [ABSTRACT FROM AUTHOR]

In recent years, Zigbee has become one of the most promising protocols for wireless home networking. Consequently, interoperation with Zigbee-enabled home network devices such as wireless sensors and appliances is an essential functionality in home gateway systems. This paper describes the design and implementation of an effective architecture for dynamic integration of Zigbee home networks into OSGi-based home gateways, where ad hoc Zigbee devices are represented by device proxy services. Further, such proxy services can be automatically downloaded, installed, and registered in the OSGi service registry by the dynamic device integration manager as the corresponding devices join the Zigbee network. Thus, home network applications can discover proxy services for the required Zigbee devices, and access the devices through the common proxy service interfaces without concern for the specific access protocols and libraries of the device. [ABSTRACT FROM AUTHOR]

This paper describes a compact display system with a network interface designed to receive video signals from an external server device such as a PC. This system has been built on a small printed circuit board (PCB) with an embedded DSP&CPU chip, and has been integrated into our prototype portable projector. With this PCB, the projector is capable of displaying multiple PC desktop screens from remote PCs connected through a network on a single projector screen. In addition, using the DSP's ability to decode compressed audio and video signals, the projector can be used to display network video streaming. In order to minimize its size the network interface is made detachable by using a network adaptor on a USB port. This architecture makes it highly configurable and easy to change its functions according to customers' needs. Following the description of its hardware and software architecture, we set forth the method introduced to debug the system software with the final prototype board using the wireless network connection established through the USB wireless LAN network adaptor. [ABSTRACT FROM AUTHOR]

This paper introduces a promising property in which the transmitter of an OFDM system can utilize an N-point IFFT operation to build the time-domain symbols of a KN-point IFFT operation. Based on this property, we propose a flexible OFDM structure. This structure will support uplink applications which include many transmitters using different numbers of subcarriers and one receiver with just one IFFT/FFT module with the subcarriers of least common multiple (LCM) for the number of subcarriers of all the transmitters. Therefore it reduces the design complexities of the receiver and increases the compatible characteristics for consumer electronics (CE). Compared with the original OFDM system, the proposed system improves the performance of the packet error ratio (PER) and the bit error ratio (BER) performance by using the appropriate K. In addition, the proposed structure can be designed to enlarge the bandwidth efficiency of the system and improve the performance of channel estimation compared, with the OFDM/TDM system. [ABSTRACT FROM AUTHOR]

VBSME (Variable Block Size Motion Estimation) is adopted in the MPEG-4 AVC /H.264 standard. In order to increase the hardware utilization for VBSME with FSBMA( full search block matching algorithm), this paper proposed a new high-performance reconfigurable VLSI architecture to support "meander"-like scan form at for a high data reuse of search area. The architecture can support the three data flows of the scan format through a reconfigurable computing array and a memory of the search area. The computing array can achieve 100% processing element (PE) utilization and can reuse the smaller blocks' SADs to calculate 41 motion vectors (MVs) of a 16×16 block in parallel. The design is implemented with TSMC 0.18µm CMOS technology. Under a clock frequency of 180 MHz, the architecture allows the real-time processing of 1280x 720 at 45fps in a search range [-16, +16]. [ABSTRACT FROM AUTHOR]

The conventional architecture of smart home is usually server-centric and this may cause many problems. The distributed architecture presented in this paper is based on multiple OSGi (Open Service Gateway Initiative) platforms. Relative home appliance services which are compliant with R-OSGi middleware for the home network system are also developed. The important aspect of R-OSGi is that it offers distribution transparency and uses the natural boundaries between software modules to establish the potential boundaries for distribution of the application. Experimental results obtained from the demo room show that the architecture is practical and reliable. [ABSTRACT FROM AUTHOR]

This paper presents a system architecture of an acquisition, compress ion and rendering system for 3D- TV and free-viewpoint video applications. We show that the proposed system yields two distinct advantages. First, it achieves an efficient compression of 3D/multi-view video by extending a standard H.264 encoder such that near backward compatibility is retained. Second, the proposed system can efficiently compress both 3D-TV and free-viewpoint multi-view video datasets using the single proposed system architecture. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of a home monitoring system based on hybrid sensor networks. The system follows a three-layer architecture which combines hybrid-node networking with web access. An enhanced sensor node has been designed and fabricated to add controlled mobility to wireless sensor networks. The mobile node is capable of simple planar motions and is easy to be controlled through different user interfaces. A testbed including the static nodes as well as the mobile node has also been created for validating the basic functions of the proposed hybrid sensor network system. Network repair and event tracking capabilities of the mobile sensor node were tested. Stability of the proposed system in longtime home monitoring tasks was also verified. [ABSTRACT FROM AUTHOR]