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Network-based signature generation (NSG) has been proposed as a way to automatically and quickly generate accurate signatures for worms, especially polymorphic worms. In this paper, we propose a new NSG system-PolyTree, to defend against polymorphic worms. We observe that signatures from worms and their variants are relevant and a tree structure can properly reflect their familial resemblance. Hence, in contrast to an isolated view of generated signatures in previous approaches, PolyTree organizes signatures extracted from worm samples into a tree structure, called signature tree, based on the formally defined "more specific” relation of simplified regular expression signatures. PolyTree is composed of two components, signature tree generator and signature selector. The signature tree generator implements an incremental signature tree generation algorithm from worm sample clustering, up-to-date signature refinement to efficient tree construction. The incremental signature tree construction gives insight on how the worm variants evolve over time and allows signature refinement upon a new worm sample arrival. The signature selector chooses a set of signatures for worm detection from a benign traffic pool and the current signature tree constructed by the signature tree generator. Experiments show that PolyTree cannot only generate accurate signatures for polymorphic worms with noise, but these signatures are well organized in the signature tree to reflect the inherent relations of worms and their variants.

The preceding paper proposed a general-purpose digital computer structure consisting of many small iteratively connected sequential machines. A set of machine instructions was presented and a programming example of synchronous machine operation was given. This paper examines some of the problems associated with asynchronous operation of this iteratively structured digital computer. A solution is presented enabling the many small sequential machines which constitute the large iterative computer to communicate asynchronously. The instruction set outlined in the previous paper is maintained and a pictorial example of asynchronous operation is presented.

An asynchronous unit delay is an n input n output asynchronous sequential circuit in which the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. This paper considers the problem of determining when a fundamental mode flow table is realizable as a feedback-free connection of asynchronous unit delays. It is shown that such a realization exists if and only if the flow table is asynchronous definite, where the asynchronous definite property is a modification of the definite property of synchronous sequential machines. A straightforward method of realizing asynchronous definite flow tables without critical races by feedback-free circuits of asynchronous unit delays and combinational gates is developed. The use of asynchronous unit delays for definite tables avoids complicated secondary assignment problems, results in circuits with very simple structure, and brings closer the theories of synchronous and asynchronous sequential machines.

A method of network synthesis for general combinational functions that uses a number of fixed threshold logic units not greatly in excess of the theoretical minimum is described. It can be used with adaptive logic in which case a minority of the interconnections are simply adapted once according to the rule originally suggested by Hebb. This network on its own has no capacity for ``generalization,'' and if used for pattern recognition must therefore be operated in conjunction with a suitable property filter, such as that of the previous paper.[1] In this case the present network could perform as a trainable ``categorizer.''

—The operation speed of a one-dimensional, unilateral, iterative switching network with strictly combinational cells is often drastically limited by the propagation delays of carry variables. In this paper an attempt is made to extend to other iterative networks the scheme of a fast carry-propagation circuit proposed by several authors for parallel adder. The class of the networks which are realizable according to this scheme is small but contains many networks of practical interest.

These three papers, based upon the first author's Ph. D. dissertation, are concerned with the problem of assignment and sequencing of computations on multiprocessor or parallel computer systems. Although individually the papers suffer from the usual abstracting difficulties, the results are significant and warrant serious study by readers interested in computer system modeling and analysis.

This paper is basically concerned with determining readback distortion in magnetic recording. This determination is obtained, not by closed-form analysis, but by simulation of the readback system, consisting of the head and load. The simulation environment allows the author to avoid two limiting assumptions of the past. In this case, he is able to treat a head of finite permeability and a nonzero load. The load considered is a rather standard and adequate parallel RC network. For the finite permeability head, an RL series equivalent circuit is used in which the resistance and inductance are frequency dependent and determined experimentally. The argument is made that the open-circuit readback voltage (zero load) is linear with the input (variation of flux in the storage medium). This fact allows superposition to be applied, and the actual readback voltage computed at the various harmonics of the input. Since R and L vary with frequency, a different equivalent circuit of the head applies for each harmonic. The analysis and superposition of the linear network responses for each network is performed digitally. Finally, some digital filtering is performed in an attempt to offset the effects of distortion, to no avail.

With this paper the authors are announcing development in progress on a simulation programming language which they have named SODAS ( Structure Oriented Description and Simulation). Motivation for the development is provided by an opening discussion of desirable attributes of a language for general system design. A brief description of SODAS syntax and semantics follows, and then a SODAS program for simulation of a highway traffic control system, a fairly detailed example of how the language fulfills the desired objectives.

Second generation computing systems rarely had an aggregate of peripheral devices with high enough data transfer rates to tax memory speed or to degrade central processor ( CP) performance. Whenever they did, there was no attempt to overlap transfer with computing, and the CP remained idle. But in many third generation systems, there are several processors-both I/O devices and arithmetic units-operating asynchronously and independently, each of which has a high transfer rate to main memory. Thus, the question of designing sufficient bandwidth into memories and buses is significant. Experience with some of the commercial multiprocessing systems (e. g., UNIVAC 1108 or IBM 360/67) shows, however, that sufficient bandwidth is not enough. The system must be organized so that the full bandwidth, or at least a large fraction of it, can be used effectively. It is this problem to which the author has ably addressed his paper.

This paper is an introduction which presents only the first layer of the makeup of graphics. While this layer is explained sufficiently and clearly, as in many tutorial papers, value judgements are studiously avoided. The primary purpose, therefore, of this review will be to place in perspective some of the alternatives presented.

The paper by Smith is representative of a class of spacecraft-guided simulation problems wherein the body dynamics of the spacecraft are eliminated by assuming that the inertia of the body is zero. Thus rotational accelerations become infinite and attitude system-response times are taken to be zero. The simulation of such problems is most generally performed entirely on digital equipment because the rate of change of the guidance function is generally of the same order as the rate of change of the trajectory parameters.

The purpose of this paper is to develop design equations for switched positive-resistance digital-to-analog converters. The authors state that no synthesis method heretofore has existed for the design of this type of ladder network. The problem to which the paper addresses itself is the following

Recent studies have shown that many noise processes in sequential networks can be described as either a multinomial process, a Markov process, or a linearly-dependent process. This paper extends the results of those studies to show how the statistics of any sequence selected from processes of this type can be calculated. Through the use of z-transform techniques, it is shown that the characteristic roots of the characterization matrix which describe the process are useful in categorizing the statistical properties of the process. It is also shown that the logical combination of two or more linearly-dependent sequences is another linearly-dependent sequence. The relationship between the characterization matrices of the input sequences to a sequential machine, and the characterization matrix of the output process is derived.

—This paper treats the problem of finding efficient secondary assignments for synchronous sequential circuits. It presents a straightforward approach which identifies codes resulting in the least number of memory elements and sets of simple next-state functions, expressed in the sum-of-product form.

This paper proposes an approach to improving the regularity of computer logic for the more effective use of LSI which has been limited by the number of pins and wiring layers.

This paper combines a useful review of progress during the past year, a description of present programs and immediate goals, and some forecasts of ultimate goals. Although the author, as director of Texas Instruments' semiconductor research and development laboratories, deals primarily with programs and points of view at TI, he makes enough references to work at other companies to build up a reasonably comprehensive picture of the large-scale integration field. Four main areas are covered: bipolar chip technology, full-slice technology, MOS technology, and hybrid technology.

Howe has included a variety of valuable information in this paper, the unifying thread being the improvement of precision in analog devices, a topic in which he has long been a leader and innovator. This paper describes 1) precise means of implementing with hardware nonlinear mathematical models involving function generation, multiplication, and division, and 2) techniques of scaling the mathematical model so as to obtain full benefit of the precision available in the analog devices. It is unfortunate that the details of this latest work are somewhat obscured by several errors in the published paper.

With the growing abundance of time-sharing systems we begin to hear more and more about text editors. These programs were originally designed to satisfy the common need for creating and modifying source language programs for the various programming language processors found in a time-sharing system. Soon it became obvious that editors could be used in many other situations, for example, in data preparation, report generation, manuscript editing, and in some cases even as the programming language itself. This paper describes a text editor, QED, which has been in use in the Berkeley time-sharing system for the SDS-930 and which has benefited from two and a half years of user experience.

—This paper deals with theoretical and experimental aspects of estimating correlation functions of signals generated by nonstationary processes. The estimation process is based on approximation of the expectation or ensemble average definition of the correlation function. The assumption of stationarity regarding the signals under analysis need not be made. Emphasis is placed on off-line analysis, where immediate readout of a correlation-function estimate is not required. Hybrid or digital computation may be used for off-line analysis, resulting in drift-free, repeatable results. The estimation procedure is developed with the aid of filtering theory. Three different solutions for estimation are presented: two-dimensional filtering, one-dimensional filtering, and one-dimensional filtering with deficient a priori data. Experimental results obtained from the digital computer are presented for the latter solution.

This paper describes work carried out by the author while working for his Ph.D. degree. The work was done at the University of Arizona, Tucson, under the supervision of Prof. G. Kron, using Arizona Statistical Repetitive analog Computer (ASTRAC II). The ultra-high speed of ASTRAC II permitted the author of obtain Monte Carlo solutions of partial differential equations at a much higher rate than previously reported and to continuously display these solutions.

This paper is addressed to people who utilize hybrid computation facilities for the simulation of control systems and other applications invoking the stability of a closed loop. It could also be useful to anybody, with or without an available hybrid facility, who is concerned with the problems introduced by discontinuities and fixed time delays in control and feedback systems.

—This paper describes a computer program for analyzing a class of transmission line configurations which arise in the design of memory arrays. The systems analyzed by the program consist of interconnected pairs of mutually coupled distributed parameter transmission lines driven and terminated by linear lumped element networks. A brief discussion of the mathematical model and its implementation is given and applications of the program to the design of 2½D and 3D memory arrays are described. The applications illustrate how the program can be used to evaluate pulse propagation characteristics and noise generation mechanisms within a memory array.

This paper describes an Integrating Analog-to-Digital Converter whose principle of operation is as follows. The output of an analog integrator is monitored by two comparators for positive and negative overflows with respect to a given level q. The comparators drive a bidirectional counter. After every overflow, a pulse of current is added to the integrator input; the polarity, magnitude, and duration of this pulse are calculated to offset the output of the integrator by the amount q.

This paper describes a number of computing elements, each combining AD or DA conversion with one or more arithmetic operations or function generation. The elements, termed PHENOs, are claimed to have bandwidth-accuracy products equal to or better than the best linear analog computing components. The authors suggest that PHENOs may be put to good use in two areas. First, in general-purpose hybrid computation, where they represent a logical extension of the MDAC (multiplying digital-to-analog converter) in improving the AD interface. Second, in applications requiring miniaturization, the ability to function in an adverse environment, and the ease of interface with DDA (digital differential analyzer) components, as in airborne and shipboard devices. Both claims appear to be well-founded and merit further investigation by hardware experts in these two fields.

This is a somewhat discursive but informative article on the hybrid Apollo docking simulation. The authors do not identify their objective in writing the paper until the very last sentence of the concluding section, where they state: "It is hoped that some part of the description of the problems, solutions, and experiences will be useful to others who are now involved, or who may become involved, in simulations similar to the one described." With that as an objective,much of the detailed material on problem characteristics and specifications of the docking test device could have been condensed into an introductory or parenthetical paragraph. The discussion of why a hybrid computer was selected in preference to an all-analog or all-digital system, and of the way the problem was distributed between the analog and digital portions of the hybrid system, also adds little to the paper or to previously published material on these subjects.

The purpose of this paper is to explore the effect of multiple modules of memory together with multiple bus lines for providing effective communication between memory and processors or channel controllers. Apparently the study was undertaken to determine an optimum configuration of equipment for an installation to be made by a computer manufacturer to a university. It suffers from the necessary evil which abides in studying a particular system under specific limitations applying to that system. The author has made no attempt to generalize his results regarding priority and processor performance as effected by the number of modules and buses available. The special restrictions which apply are in terms of channel controller timing and drum unit datum acquisition.

The title of this paper is misleading. It should read "Suggestions for New Data Types and Manipulations for PL/I." It is not about programming without data, but about accessing highly structured data in a systematic way. The goal is to minimize the difficulty of changing the data structure at a late date in the programming cycle.

In analog computation there is a tendency not only to strive for the highest possible accuracy, but very often the ciiterion for accepting an analog scheme also requires minimizing the number of computer components and the duration of the problem preparation time. On the other hand, in analog or hybrid computation every sophistication intended to improve accuracy usually calls for more computer equipment, and every sophistication introduced to reduce comptuter equipment usually requires more time for problem preparation. Having this in mind, the method of Bessel function generation, discussed in Bingulac and Humol (Reference 5 in Hausner's paper), may be considered as the first degree of sophistication, since in developing this method the only criterion was to reduce the complexity of the analog computer scheme, thereby decreasing the number of computer components. Van Remoartere's method, 2 however, represents the second degree of sophistication because a) it divides the whole range of the independent vatiable into two subintervals, and b) in the first subinterval it approximates the solution by a Taylor series. This of course improves the accuracy but on the other hand, the number of analog computer components increases.

—Four-phase MOS circuits exhibit many peculiar features not observed in other families of logic circuits. In this paper, a mathematical model which characterizes the circuits is presented for logic simulation. It is shown that this model enables us to develop a computer program which can rapidly and efficiently verify and evaluate the logic design of the circuits.

Innumerable papers by Russian authors using probabilistic models for physical systems are prefaced by a comment explaining that the results obtained must follow from dialectic materialism, and therefore the same results could in principle be derived deterministically ll as statistically, save for mathematical convenience. A similarly political motivation may unconsciously underlie many papers in the computer field which explain that ever more elaborate executive programs are motivated exclusively by a desire to increase hardware efficiency and improve system economy

The author has chosen a somewhat inappropriate title for this paper; the file records he discusses are not "generalized," but rather tailored to predictable real world constraints, and the "management information systems" he considers form only a portion of the spectrum. Nevertheless, he presents an objective technique for file record design quite applicable in certain cases. Given 1) known and predictable data and basic interrelationships subject to 2) known and predictable use (processing/querying), then the design techniques presented by the author should certainly ease the designer's conscience, if nothing else, and will probably materially assist in "tuning" a record- oriented data management system. The analytic design techniques presented form one element in a suggested iterative design loop "of data collection, preliminary file design, simulate (sic), analyze (sic) results, . . . ." Additional consideraton of "tuning" a system might well lead to consideration of special instrumentation, special reduction for the data gathered by such instrumentation, adaptive systems which "tune" themselves for optimum performance, and other subjects. This article concentrates on the analytic design techniques, to the exclusion of the other aspects of the complex design cycle

This paper concerning two IBM programs was written by two IBMers for an IBM publication. This might given reason to question the objectivity of the paper and its value to the general community. In actuality, though, the two programs discussed are of sufficient general interest, if for no other reason than the popularity of the machines for which they have been implemented, and the authors have maintained sufficient perspective to warrant reading of the paper by all persons interested in continuous system stimulation

—This paper discusses a method of correcting almost unlimited errors1in a single channnel of an f-channel system. The method uses a two-dimensional variable-length code (2-DVL). The encoding and decoding systems are implemented by a parallel linear-feedback shift register (LFSR).

This paper describes an all-parallel DDA with electronic patchboard, high iteration rate (one million complete computation cycles per second), and reasonable word length (20 bits), built by Teledyne. It further describes the hybrid LSI packaging used (MEMA hybrid multichip flatpack), computer-aided methods of programming, and automatic methods of documenting the resultant coding.

—Adaptive control of complex manufacturing processes can provide significant improvements in production rate and product quality. To maximize these advantages, the adaptive control system must be capable of making accurate measurement of process per- formance. This paper describes the implementation of a general- purpose performance computer which makes use of a combination of two techniques: trainable pattern recognition and linear regression. The description covers the system concept, the training procedures or algorithms, and the detailed design.

—This paper deals with computer-aided design of digital systems and presents a formal method for designing a digital system via state tables. The steps of the design method can be summarized as follows: a) a system is described by a set of microprograms written in a "transfer language," b) the set of microprograms is translated into a set of flow tables by an algorithm, and c) the flow tables are converted into logical diagrams by synthesis procedures. The purpose of step a) is to aid the designer in describing the system; the result of step b) makes it possible to reduce the logical complexity of the system by using systematic techniques of the sequential network theory; and the result of step c) is a system of interconnected sequential networks, operating simultaneously which may include iterative asynchronous networks.

—The principal synthesis example of Schneider and Dietmeyer's paper [1] is examined by applying a new synthesis algorithm. The minimum NOR gate realization thus obtained is used to illustrate the nonoptimality of their approach and to question their definition of delay. Arguments are advanced for synthesis with simple modules.

This narrative comprises a rather subjective and limited summary of queuing analyses that are applicable to the design of computer scheduling algorithms. The queuing disciplines are all treated as priority disciplines, and are categorized according to priority dependence on running time, system state, external factors, or waiting time. A single-server system is assumed for most of the discussion, but a section on multiple-server systems is included at the end of the paper.

This paper gives a description of the "virtual machine" of MULTICS, the multiple-user computer system conceived at M.I.T. and implementedfdhuf on the General Electric Model 645 time-sharing computer. The virtual machine is the machine which is seen by the system "user," i.e., the application programmer working at the assembly language level. The MULTICS virtual machine has a number of salient features which distinguish it from conventional machines.

This paper describes a monitor system for a small display computer, attached as a satellite to the Berkeley SDS-940 time-sharing system. It describes some modifications made to the interrupthandling hardware of the small machine, a DEC PDP-8. It also gives details of a set of calls to the monitor, which allow multiprogramming of tasks in the satellite.

This paper should cheer both system programmers and application programmers. The authors describe the methods used to measure the performance of both the GE-625/ 635 GECOS II operating system nd the user programs running under the operating system. Anyone who works on computer operating systems or who is involved in computer system measurement and improvement would probably find this paper interesting.

—This paper describes the concept of a hardware sequential decision-making device consisting principally of an array or network of nodes which can support a plurality of connections among the nodes on a simultaneous basis. The connection "chains" the nodes together. The application of the device to a dynamic computer memory allocation system is described in the paper. In this use, each "node" would correspond to a word or a group of words in a storage device, the access to which is controlled by a control unit employing the node network. Thus, only one node needs to be selected to either load a record into the controlled memory unit, or to read the record from it.

This paper is worthy of attention. Written with the facility one has grown to expect from Prof. Dijkstra, this is an announcement of a new operating system designed and constructed at the Technologi-cal University at Eindhoven for the EL X8.

This paper describes a scheme for organizing and creating the control portions of an interactive graphical program. Since the response of such a program to some console input may depend on the history of previous inputs, the author structures his control programs as finite-state automatons. Thus state diagrams are used as the notation for defining the behavior of an interactive graphical program. Such notation does indeed add clarity and order to the description of this information.

In the ever-increasing trend to relieve man of time consuming menial tasks via automation, the digital logic designer's tasks have come under study. Various phases of this work are now being performed by computers. One of these phases, simulation of digital designs, is the topic of this paper.

This paper focuses attention upon the design of a processor and memory system which is structured to achieve a satisfactory balance of processor speed and memory speed when both the processor and input–output controller are simultaneously competing for memory service. A mathematical model is developed to investigate the degree to which the processor is capable of overlapping memory references with instruction execution as a function of respective cycle times, the number of instruction "look-aheads," the number of independent memory modules, and input–output traffic. Utilizing this model, design trade-offs and performance indices are graphically examined for a hypothetical system.

In this paper the possibility of removing in synchronous sequential machines some of the delay elements which store the internal state is discussed. Theorems and methods are given for eliminating all removable delay elements from a given realization of a synchronous machine and for selecting the assignments leading to a realization which requires the least number of delay elements. It is shown how the existence of these assignments is related to the existence of a pair of partitions on the set of states of the given machine. The internal performance of the sequential networks in which at least one but not all delay elements are removed is studied, and a "hybrid operating mode" is defined. A reclassification of sequential machines in terms of the algebraic structure of machines which relates to the number of removable delay elements is proposed. Sequential machines are, therefore, divided in three categories: synchronous, hybrid, and asynchronous, and some problems of decomposition for the three types of machines are discussed.

This paper constitutes a description of a potentially interesting class of analog-digital computing systems. Unfortunately, much of the discussion is devoted to nomenclature and to general comments which are too vague to permit a meaningful evaluation of the approach.

This paper discusses the problems of simulating systems in which some random behavior exists. The title refers to "discrete-event simulation," but this remains undefined and unemphasized throughout most of the paper. (The expression refers to svstems in which events, such as customer arrivals, occur at a countable set of points on the continuous time axis–this as opposed to a continuous-event simulation in which important properties of the system must be accounted for over a continuum in a given time interval.) The authors trace the elements of a typical experiment and identify the statistical problems along with a discussion of their possible solutions. They isolate a number of frequently overlooked considerations in the random input process, particularly the independence of adjacent samples. Similarly, in estimating system performance, the problem of correlated outputs must be solved. In short, in any simulation, the input data and the system structure must be understood and examined carefully.

A digital system design language, DDL, has been described and shown to provide a concise yet precise means of specifying the organization and operation of digital systems, regardless of timing mode or hardware types, at various levels of detail [2]. This paper defines a series of tasks that transform any DDL document to Boolean and next-state equations from which a system may be implemented. Each task of the transformation produces another DDL description of a system which uses fewer features of the language.