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The decreasing lifetime of NAND flash memory, as a side effect of recent advanced semiconductor process scaling, is emerging as one of major barriers to the wide adoption of SSDs in high-performance computing systems. In this paper, we propose Dynamic Erase Voltage and Time Scaling (DeVTS), an integrated approach to extend the lifetime (particularly, endurance) of NAND flash memory. DeVTS is motivated by our key observation that erasing a NAND block with a lower voltage or at a slower speed can significantly improve NAND endurance. However, using a lower erase voltage causes adverse side effects on the write performance and retention capability of NAND flash memory. In order to improve NAND endurance without affecting the other NAND requirements, we take advantage of idle times between write requests and variations of the retention requirement when writing data to a NAND block erased with a lower voltage. We have implemented a DeVTS-aware FTL, called dvsFTL, which exploits the tradeoff relationship between the endurance and erase voltages/times by accurately predicting the write performance and retention requirements. Our experimental results show that dvsFTL can improve NAND endurance by 94 percent, on average, over an existing DeVTS-unaware FTL while all the NAND requirements are preserved. [ABSTRACT FROM PUBLISHER]

Networks-on-chip (NoCs) have been increasingly adopted in recent years due to the extensive integration of many components in modern multicore processors and system-on-chip designs. At the same time, transistor reliability is becoming a major concern due to the continuous scaling of silicon. As the sole medium of on-chip communication, it is critical for a NoC to be able to tolerate many permanent transistor failures. In this paper, we propose uDIREC, a unified framework for permanent fault diagnosis and subsequent reconfiguration in NoCs, which provides graceful performance degradation with an increasing number of faults. Upon in-field transistor failures, uDIREC leverages a fine-resolution diagnosis mechanism to disable faulty components very sparingly. At its core, uDIREC employs MOUNT, a novel routing algorithm to find reliable and deadlock-free routes that utilize all the still-functional links in the NoC. We implement uDIREC's reconfiguration as a truly-distributed hardware solution, still keeping the area overhead at a minimum. We also propose a software-implemented reconfiguration that provides greater integration with our software-based diagnosis scheme, at the cost of distributed nature of implementation. Regardless of the adopted implementation scheme, uDIREC places no restriction on topology, router architecture and number and location of faults. Experimental results show that uDIREC, implemented in a 64-node NoC, drops 3 $\times$ fewer nodes and provides greater than 25 percent throughput improvement (beyond 15 faults) when compared to other state-of-the-art fault-tolerance solutions. uDIREC's improvement over prior-art grows further with more faults, making it a effective NoC reliability solution for a wide range of fault rates. [ABSTRACT FROM AUTHOR]

In modern SoCs embedded memories should be protected by ECC against field failures to achieve acceptable reliability. They should also be repaired after fabrication to achieve acceptable fabrication yield. In technologies affected by high defect densities, conventional repair induces very high costs. To reduce it, we can use ECC-based repair, consisting in using the ECC for fixing words comprising a single faulty cell and self-repair to fix all other faulty words. However, as we show in this paper, for high defect densities the diagnosis circuitry required for ECC-based repair may induce very large hardware cost. To fix this issue, we introduce a new family of memory test algorithms that exhibit a property we termed as “single-read double-fault detection”. This approach gains interest in ultimate CMOS and post-CMOS technologies, where the defect densities are expected to increase significantly, and/or in very-low power design, as very-low voltage sharply increases defect densities. [ABSTRACT FROM PUBLISHER]

In wireless local area networks (WLANs), link-layer multicast is a promising technology for many multimedia applications, e.g., video streaming, as multicast frames can reach multiple clients simultaneously. However, the efficiency of multicast in WLANs is usually low since multicast frames are transmitted at a basic data rate to reach clients with poor channel quality. Moreover, the reliability of multicast cannot be guaranteed either, as multicast transmissions are not acknowledged. Some recent works have utilized smart antennas to improve multicast performance. However, most of them require customized hardware and are not designed for the latest IEEE 802.11 standard, 802.11n WLANs. More importantly, these works did not consider the impact of AP association strategies on the performance of link-layer multicast. In this paper, we study the problem of link-layer multicast in large-scale 802.11n WLANs where each AP is equipped with a smart antenna that supports multiple antenna patterns. Based on channel gains of various antenna patterns from different APs, we choose the associated AP for multicast clients, partition associated clients of each AP into multiple groups, select an antenna pattern and data rate for each group of client, and transmit multicast frames to each group once. We first examine the limitation of multicast in 802.11n WLANs and the benefits of smart antennas to multicast via experiments. We then introduce the system model and formulate the problem into an optimization problem, and prove its NP-hardness. The objective is to minimize the time to transmit a multicast frame to all clients while guaranteeing high packet reception ratio (PRR) for each client. For generic WLANs where APs are sparsely deployed, we propose an optimal algorithm under the condition that the PRR of antenna patterns and data rates are known for every client. For generic large-scale WLANs, we further propose an on-line algorithm in which the AP association strategy, the partition of clients, the antenna pattern and data rate of each group are adapted dynamically, based on PRR reports from clients. We have implemented the on-line algorithm on off-the-shelf WLAN products, and conducted extensive experiments and simulations to evaluate the performance. The results show that the proposed algorithm can significantly improve multicast performance compared to other schemes, and at the same time guarantee high PRR for all clients. [ABSTRACT FROM PUBLISHER]