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A new flip-chip process using interlocking-bump joints, formed by inserting Cu bumps into Sn bumps, was investigated. Severe plastic deformation of Sn bumps occurred during formation of the interlocking-bump-joint structure. Contact resistance of the interlocking-bump joints was remarkably improved, compared to that of planar-bump joints. The average contact resistances below 17 mΩ/bump were obtained for the interlocking-bump joints processed with bonding forces larger than 7 N. The interface resistance between a Cu bump and a Sn bump in the interlocking-bump joints processed with a bonding force of 15N was evaluated as 11.2 mΩ/bump. Chip shear force was greatly improved from 0.14 N of the planar-bump joints up to 3.9 N for the interlocking-bump joints. [ABSTRACT FROM AUTHOR]

The trend toward finer pitch and higher performance integrated circuit devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermomechanical failure is one of the major bottlenecks in the development of Cu/low-k larger-die flip chip packages. This paper describes the optimization of the structural design of Chartered's C65nm 21mm x 21mm die size flip-chip ball grid array package incorporated with fully active and functional nine- metal Cu/low-k layers and 150 μm interconnect pitch. The low- k material used in this paper is nonporous SiCOH with a k value of 2.9. A parametric study using 2-D plane strain finite element analysis was performed to study the effect of various parameters on the reliability of the large-die package in order to arrive at an optimized design. In order to have a simple criterion to predict the reliability of the yet-to-be-built large-die package, reliability tests were carried out on some existing 15mm x 15mm die Cu/low-k flip chip packages which were identical to the 21 mm x 21mm die package except for the size. The packages were found to pass the reliability tests. 2-D plane strain finite element analyses were then performed on the 15mm x 15mm die. The computed delamination stresses at the low-k layer and the strain energy density dissipation per cycle in the critical solder (ΔW) were then used as a benchmark for the design of a larger flip chip package. The efficacy of the polymer encapsulated dicing lane technology was established. In this paper, the effect of the number of fluorosilicate glass layers, die thickness, substrate thickness, Cu post height, and underfill type on the delamination stresses in the low-k layer and ΔW were determined. Specimens of the optimized large-die package were then fabricated and subjected to reliability tests. They were all found to pass the reliability tests. From these reliability tests, new benchmark values of the delamination stresses at the low-k layer and ΔW are obtained, which can be used to aid in the design of large-die Cu/low-k flip chip packages. [ABSTRACT FROM AUTHOR]

In this paper, the effects of heating rate during anisotropic conductive film (ACF) curing proëesses on ACF material properties such as thermomechanical and rheological properties were investigated. It was found that as the heating rate increased, the coefficient of thermal expansion (CTE) of the ACF increased, and the storage modulus and glass transition temperature (Tg) of the ACF decreased. Variation of the ACF material properties are attributed to cross-linking density, which is thought to be related with the ACF density. In addition, as the heating rate increased, the minimum viscosity of the ACF decreased and the curing onset temperature increased during the curing process. The similar phenomenon was also found in in-situ contact resistance measurement. As the heating rate increased, contact resistance establishing temperature increased and the contact resistances of the ACF flip chip assemblies decreased. The decrease in contact resistance was due to larger conductive particle deformation which leads to larger electrical contact area. The effect of the heating rate of ACFs on thermal cycling (T/C) reliability of flip chip assemblies was also investigated. As the heating rate increased, the contact resistances of the ACF flip chip assembly rapidly increased during the T/C test. The T/C reliability test result was analyzed by two terms of shear strain and conductive particle deformation. Reduced gap of joints due to reduced ACF viscosity resulted in larger shear strain. Moreover, many cracks were observed at metal-coated layers of conductive particles due to larger deformation. [ABSTRACT FROM AUTHOR]

In the prediction of underfill flow in a flip-chip package, numerical methods are usually used for flow analysis and simulation since analytical methods cannot meet the requirement for predicting fluid distribution in a planar analysis. At present, there appears to be no simulation software commercially available that is able to provide adequate prediction for the underfill flow process driven by capillary force in a micro-cavity situation. In the study presented in this paper, a numerical model was proposed for the prediction of flip-chip underfill flow. In this model, the power-law constitutive equation was used to describe the non-Newtonian behavior Of encapsulant fluids and a time-dependent velocity boundary condition was used instead of the pressure boundary condition commonly used. The comparison between the model-predicted and experimental results indicated that this model can give a good prediction for the underfill flow in a micro-cavity. This model was implemented by a general-purpose commercially available software program ANSYS, which has a high reliability and wide accessibility. [ABSTRACT FROM AUTHOR]

For heterogeneous materials assembly, the thermal expansion mismatch between the chip and the substrate is a roadblock for flip chip bonding of ultrafine-pitch (⩽ 10 μm) and large diagonal devices (⩾ 20 mm). Residual strains in bumps and device warpage have been calculated to evaluate the thermomechanical limits of a conventional flip chip soldering process using micro bumping. As a solution to overcome these limits, this paper describes a new patented flip-chip technology representing a technological breakthrough compared to conventional methods such as soldering or bonding through conductive adhesives. Electrical connections are performed by the insertion of metallic micro-tips in a ductile material. As a low-temperature process and fluxless technology, this method is adapted to fine-pitch and large devices. As a proof of concept, we present the bonding results obtained on fine-pitch large arrays of daisy chains with 500 x 500 contacts and 30-μm pitch. The electrical contact has been demonstrated and characterized in terms of resistance and yield. [ABSTRACT FROM AUTHOR]

High-Q copper inductors were fabricated on low-cost and low-loss bismaleimide triazine (BT) and glass substrate using electroplating process. A differential LC voltage-controlled oscillator (VCO) circuit was designed using these high-Q inductors at 2.4 GHz. Flip chip and multichip module (MCM) technologies were applied to assemble the active chips on BT and glass substrate. The inductors exhibited Q-factor as high as 25 at 2.4 GHz. VCOs with copper inductors on BT and glass substrate had phase noise of-108 dBc/Hz at 600 kHz offset for a 2.4-GHz carrier, which is 6-dB improvement compared with the one with on-chip Al inductors. There was almost no substrate loss for inductors on BT and glass substrates. The effect of fabrication defect and solder joint resistance were also investigated. This technique can be extended to other building blocks, thus realizing integration of the whole RF system. [ABSTRACT FROM AUTHOR]

The current techniques for nondestructive quality evaluation of bumped solder joint connections in electronics packages are either incapable of detecting solder joint cracks, or unsuitable for inline inspection due to cost and throughput reasons. As an alternative, a novel solder joint inspection system is being, developed. The system projects short laser pulses onto specimen surface through optic fibers to induce structural vibration. The induced surface displacements are then measured by a laser Doppler vibrometer. A number of digital signal processing algorithms, such as error ratio and correlation coefficient, were used to analyze the vibration responses and identify defective specimens. This paper presents a systematic study of parameters such as error ratio, correlation coefficient, resonant frequency, electrical resistance, and the extension of solder joint cracks, to quantitatively characterize the relationships among them. These relationships verified that the laser ultrasound inspection system provides a reliable and efficient way to evaluate flip chip solder joint cracks nondestructively. [ABSTRACT FROM AUTHOR]

The effect of electromigration (EM) void formation arid the failure mechanism of flip chip ball grid array (FCBGA) packages under a current density of 1·104 A/cm² and an environmental temperature of 150 °C was investigated. Eight solder/substrate combinations of four lead-free solder systems with two substrates were examined to verify the failure modes. A conservative failure criterion was adopted to define and predict the failure of the package. scanning electron microscope (SEM) was employed to observe in situ microstructural changes, intermetallic compound (IMC) growth, and failure modes. All samples exhibited a similar failure, attributed mainly to void occupation along under bump metallization (UBM)/solder interfaces at the cathode chip side of the bumps with downward electron flow. Voids were initiated at the corner due to current crowding. Two specific void locations were identified at the IMC/solder and UBM/IMC interfaces, and they coexisted in the same specimen but in different bumps. No void coupling mode was found. Since the atom diffusion rate in the solder differs from that in the IMC layer, the voids can be formed between them. A current density of 1·104 A/cm² was sufficiently high to form a void pattern at the IMC/solder interface. However, the formation of voids at the UBM/IMC interface is generally induced by the consumption of UBM, since the high temperature of 150 °C crucially dominates the void morphology at the UBM/IMC interface. The difference among solder systems did not affect the failure modes nor dominate mechanisms. With respect to the differences of substrate surface finishes, more voids appeared at the cathode substrate side of the solders combined with Cu/Ni/Au pad than those combined with copper-organic solderabIe preservative (Cu-OSP) after long-term upward electron stressing. It suggested another possible failure at the substrate side when failure did not occur at the chip side in an EM test. [ABSTRACT FROM AUTHOR]

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUE) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 µm), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps. [ABSTRACT FROM AUTHOR]

In this paper, the effects of thermal cycling on material properties such as coefficient of thermal expansion (CTE), modulus, and glass transition temperature (Tg) of nonconductive pastes (NCPs) for flip chip applications were investigated. Using a thermomechanical analyzer, the dimensional changes of NCPs and an underfill material were measured. The dimensional changes of all materials during the first cycle rapidly increased near Tg. However, the rapid increase of dimensional change near Tg was not observed during the second and third cycles. Furthermore, using a dynamic mechanical analyzer, the modulus and Tg were measured. The modulus in the first cycle was smaller than that in the second cycle for all materials. After the first cycle, the modulus curves followed the second cycle curve. Next, the warpage behavior of the flip chip assemblies was observed using the Twyman-Green interferometry method to investigate how material property changes affect warpage behavior during thermal cycling (T/C) and it was found that the warpage of the flip chip assembly decreased after the first cycle. However, after the first cycle, the amount of warpage was constant for the following five cycles. As a result, it was verified that the material properties of NCPs and the underfill material change after the first thermal cycle, and the material property changes are closely related to the warpage hysteresis behavior during T/C. Finally, warpage hysteresis was understood as shear strain. [ABSTRACT FROM AUTHOR]

In this paper, we present the development of a low cost chip/wafer bumping technique for flip chip assembly and microelectromechanical systems integration using a bump transfer approach. In this method, high melting temperature bumps such as copper, nickel, and gold bumps are fabricated on a low cost, flexible carrier and then transferred onto the target chip/wafer/board for flip chip assembly. The aluminum pads on test chips were remetallized with electroless nickel and gold layers to facilitate the bonding of bumps to the chips using thermocompression bonding. Parallel bonding and transfer of bumps has been achieved. Thermal cycling and bump shear test showed that reliable bonding was obtained between the bumps and the pads. Surface study using laser ionization mass analysis found no traces of of the polymer carrier on the surface of the bumps on the test chip after the completion of the bump transfer process. [ABSTRACT FROM AUTHOR]

The near-eutectic Sn-Pb-Cu and Sn-Pb-Ni ternary solder alloys were developed based on the consideration of strength and fatigue reliability enhancement of solder joints in part via the altering of formation of interfacial intermetallic compounds. In this work, we examine electromigration reliability and morphologies of 62Sn-36Pb-2Ni and 62Sn-36Pb-2Cu flip-chip solder joints subjected to two test conditions that combine different average current densities and ambient temperatures: 5 kA/cm² at 150 °C and 20 kA/cm² at 3 °C. Under the test condition of 5 kA/cm² at 150 °C, 62Sn-36Pb-2Cu is overwhelmingly better than 62Sn-36Pb-2Ni in terms of electromigration reliability. However, under the test condition of 20 kA/cm² at 30 °C, the electromigration fatigue life of 62Sn-36Pb-2Ni shows a profuse enhancement and exceeds that of 62Sn-36Pb-2Cu. Electromigration-induced morphologies are also examined on the cross sections of solder joints using scanning electron microscopy. [ABSTRACT FROM AUTHOR]

We investigated electroless Ni uniformity on Al metal pads connected to different size pads or a pn junction for under bump metallurgy in flip-chip assemblies. In an electrically isolated pad, Ni thickness decreased as the pad size decreased. Because of nonlinear diffusion of Pb2+ stabilizer in the plating solution, fewer electrons were supplied to the smaller pad than to the larger pad by an anodic oxidation reaction on the pad surface. In pads smaller than 50 μm square, the Ni thickness increased when connected to a 100 μm square pad. This increase might be caused by electrons flowing from the 100 μm square pad to the smaller pad to produce an equipotential for the connected pads. In addition, the Ni thickness was increased by electrical connection to an n-type Si in the presence of fluorescent light illumination for a pn junction area larger than 100 μm². For a pad connected to a p-type Si, however, Ni thickness decreased in comparison to that of an electrically-isolated pad, regardless of the light illumination or pn junction area. The change of Ni height on pads connected to the pn junction is attributable to photoelectrons injected into the n-type Si, or to electron-hole recombination in the p-type Si. These results indicate that the pads should be of the same size within a chip for better Ni uniformity. Moreover, blocking light during Ni electroless plating can eliminate Ni thickness differences due to an n-type Si connection. [ABSTRACT FROM AUTHOR]

An analytical model is developed to predict the out-of- plane deformation and thermal stresses in multilayered thin stacks subjected to temperature. Coefficient of thermal expansion mismatches among the components (chip, substrate, underfill, flip-chip interconnect or C4s) are the driving force for both first and second levels interconnect reliability concerns. Die cracking and underfill delamination are the concerns for the first level interconnects while the ball grid array solder failure is the primary concern for the second level interconnects. Inadvertently, many researchers use the so-called rule of mixture in its effective moduli for the flip chip solder (C4)/underfill layer. In this study, a proper formula for effective moduli of solder (C4)/underfill layer, is presented. The classical lamination theory is used to predict the out-of-plane displacement of the chip substrate structure under temperature variation (AT). The warpage and stresses resulting from the analytical formulation are compared with the 3-D finite element analysis. The study helps to design more reliable components or assemblies with the design parameters being optimized in the early stage of the development using closed form analytical solutions. [ABSTRACT FROM AUTHOR]

This paper presents the results of a packaging process based on the stencil printing of isotropic conductive adhesives (ICA5) that form the interconnections of flip-chip bonded electronic packages. Ultra-fine pitch (sub-100-μm), low temperature (100 °C), and low cost flip-chip assembly is demonstrated. The article details recent advances in electroformed stencil manufacturing that use microengineering techniques to enable stencil fabrication at apertures sizes down to 20 μm and pitches as small as 30 μm. The current state of the art for stencil printing of ICAs and solder paste is limited between 150-μm and 200-μm pitch. The ICAs-based interconnects considered in this article have been stencil printed successfully down to 50-μm pitch with consistent printing demonstrated at 90-pm pitch size. The structural integrity or the stencil after framing and printing is also investigated through experimentation and computational modeling. The assembly of a flip-chip package based on copper column bumped die and ICA deposits stencil printed at sub-100-μm pitch is described. Computational fluid dynamics modeling of the print performance provides an indicator on the optimum print parameters. Finally, an organic light emitting diode display chip is packaged using this assembly process. [ABSTRACT FROM AUTHOR]

During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint shape prediction methods have been incorporated as a design tool to enhance the reliability of the WLCSP. However, the reliability of solder joints for a large chip size such as 10 mm × 10 mm without underfill remains questionable. In this research, a hybrid method combining an analytical algorithm with the energy-based approach is applied to predict standoff heights and geometry profiles of the solder joints. In addition, a hybrid-pad-shape system is proposed to design the solder ball layout, and to enhance the reliability of the solder joints. Next, a nonlinear and parametric finite element analysis is conducted to investigate the reliability issues that result from several design parameters. In addition, an experimental validation is completed to verify the correctness and feasibility of the solder joint shape prediction methods and finite element analysis procedures. The design parameters considered in this study include solder joint layout, solder volume, pad diameter, as well as the ratio and orientation of the elliptical pad. With regards to solder joint layout design, the solder joints located in the corner areas can be considered as structural dummy balls with no electrical signals passing through them. The results reveal that when the WLCSP has large round pads, or properly oriented elliptical solder joint pads at the corner areas underneath the chip, then the maximum equivalent plastic strain of the solder joints will be effectively reduced. As a result, the solder joint fatigue life under thermal loading will be greatly enhanced. Furthermore, the findings of this research can be used as a design guideline for electronic packaging with area array interconnections such as CSP, flip chip packaging, Super CSP, and fine pitch BGA. [ABSTRACT FROM AUTHOR]

New product designs within the electronics packaging industry continue to demand interconnects at shrinking geometry, both at the integrated circuit and supporting circuit board substrate level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by the need for reduced manufacturing costs and higher volume robust production capability. One of today's low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology and combines an under bump metallization (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of said bumps at different geometries. The effect of precise control of tolerances in squeegees, stencils and wafer fixtures was examined to enable the optimization of the materials, processes, and tooling for reduction of bumping defects. [ABSTRACT FROM AUTHOR]

An accurate characterization for the deformation behavior of conductive particles is important: 1) to understand the anisotropic conductive adhesive (ACA) interconnection and 2) to optimize the ACA bonding parameter. This paper introduces an experimental technique, which has been developed to allow continuous monitoring of deformation characteristics of a single conductive particle. The load-deformation curve of a single conductive particle is measured, which provides the quantitative estimation of the mechanical and electrical characteristics of metal-coated polymer spheres used in ACAs. Based on the load-deformation result of a single conductive particle and the number of trapped particles on a bump, equivalent spring models are used to predict the deformation degree of conductive particles after flip chip assembly. For two kinds of conductive particles with different polymer cores, the mechanical and electrical characteristics of ACA interconnection were studied. Such results are used to further achieve a more sophisticated approach of the ACA bonding process and contact reliability. [ABSTRACT FROM AUTHOR]

This paper addresses fatigue and bridging issues by numerical analysis for an ultra-fine-pitch flip-chip interconnect that consists of multiple copper columns (MCC) and a solder joint. First, the processing flow is briefly presented, which enables prototyping of high-aspect-ratio (∼6) copper columns, and hence, enhanced thermomechanical reliability of the interconnects. A public software, Surface Evolver (SE), has been used through this work to predict the solder joint geometry evolution. By integrating SE solder joint shape modeling, stress/strain analysis within ANSYS, and design of experiment (DoE) techniques as well, detailed numerical analysis has been conducted on the solder joint fatigue response to various factors such as the Cu-Solder wetting angle, loading direction, and solder geometry parameters. Finally, by applying the DoE techniques and the most updated features of SE, bridging risks of this interconnect with a fine pitch of 40 μm is investigated, in which critical solder volume is calculated as a function of the interconnect geometry parameters. Based on these results, a solid basis for the design and processing of this advanced flip-chip interconnect has been established. [ABSTRACT FROM AUTHOR]

Anisotropic conductive adhesive films (ACFs) have been used for electronic assemblies such as the connection between a liquid crystal display panel and a flexible printed circuit board. ACF interconnection is expected to be a key technology for flip chip packaging, system-in-packaging, and chip size packaging. This paper presents a methodology for quantitative evaluation of the delamination in a flip chip interconnected by an ACF under moisture/reflow sensitivity tests. Moisture concentration after moisture absorption was obtained by the finite element method. Then, the vapor pressure in the flip chip during solder reflow process was estimated. Finally the delamination was predicted by comparing the stress intensity factor of an interface crack due to vapor pressure with the delamination toughness. It is found that the delamination is well predicted by the present methodology. [ABSTRACT FROM AUTHOR]

Due to decreasing dimensions, electromigration becomes a major concern for flip chip joint reliability. A novel test structure for in-situ monitoring of electromigration in a flip chip connection is proposed. With this structure, small resistance changes at the cathodic and anodic sides can be mounted separately. This allows studying the asymmetric behavior of solder joints under electromigration conditions. The design of the new test structure is described and compared to the traditional measurement method. As a first test case, a Cu-Sn-Cu flip chip joint, stressed with a current of 6000 Amp/cm² at 150 °C, is studied. First tests clearly indicate diverging resistance values when comparing the cathodic and anodic side of the flip chip bumps. Microstructural analysis shows extensive Cu-migration from cathode to anode. [ABSTRACT FROM AUTHOR]

The standard model for electrical resistance of an anisotropic conducting film (ACF) bond has been analyzed for the case that includes both constriction resistance and a film resistance between the conducting particle and the bond pad. The electrical circuit for the bond resistance is divided into its different geometric regions for analysis. Evidence is give against the prevailing practice of equating the apparent physical area of contact between the conducting particle and the bond pad to the real area of electrical contact. A calculation evaluates the resistance of an ACF bond versus electrical current. This analysis shows that the constriction resistance for the ACF bond can be determined from the slope of the resistance versus current squared plot. Previous calculations for separable contact that extract the constriction resistance from the resistance versus current relationship have been carried out only for conductors that obey the Wiedemann-Franz law. Calculations in this work have extended the results to materials used in ACF bonds. Finally, it is argued that higher than expected contact resistance in anisotropic conducting adhesive bonds is likely due to a high resistivity temperature independent film resistance. [ABSTRACT FROM AUTHOR]

Precise solder bump shape prediction is crucial for the application of the solder jet bumping process to microelectronic component packaging. In the present study, numerical simulation of both the dynamics and phase change responses during a metal droplet impingement is conducted by introducing a nonconstant interfacial heat transfer coefficient, which varies with time and position. Comparison between the numerical and experimental results for a large metal droplet demonstrates the validity of the numerical method. The results of many simulation cases are presented corresponding to typical solder jet bumping conditions. Variations in the impact velocity, initial droplet size, and droplet temperature and substrate temperature are investigated to understand their impact on the formation of solder bumps. [ABSTRACT FROM AUTHOR]

In this study, the reliability of flip-chip ball-grid array package (FCBGA) is explored by a cyclic four-point bend test executed at different controlled temperature. The test vehicle is put in a heated chamber and the resulting daisy chain resistance and strains variations are monitored to check its failure. The strain gauges are mounted near the component corners to get the strains of the test boards when under bending. A data logger records the daisy chain resistance simultaneously during the test. The component failure is detected with a self-written program by judging when the failure resistance of the daisy chain is larger than 20 % of its initial resistance. The test results at various temperatures showed that the component life cycle is reduced with the increase of the temperature during the cyclic bend test when under a fixed maximum deflection setting. If tested at room temperature by varying the maximum deflections, the component life cycle is also reduced with the increase of the maximum deflection in the cyclic bend test. Through the fitted curve of all these test data, it is then possible to get relating equations among the variables of temperature, deflection, and life cycle. An extra test is conducted to verify these deduced equations with an error of only 6% approximately. Furthermore, the optic microscope is utilized to observe the failure mode of the FCBGA component after the test. It is found that all the failures are the delamination at the interface of solder balls and substrate. Also, from the results of tested curves, it can be used to predict the component life cycle at elevated temperatures based on the results tested at room temperature. [ABSTRACT FROM AUTHOR]

The nanosilica filled composite is a promising material for the no-flow underfill in flip-chip application. However, as the filler size decreases into the nano length scale, the rheological, mechanical, and thermal mechanical properties of the composite change significantly. The filler-filler and filler-polymer interactions have a profound impact on the material properties. The purpose of this paper is to achieve an in-depth understanding of the effect of the filler size and surface treatment on material properties and therefore to design a nanocomposite formulation with desirable material properties for no-flow underfill applications. Mono-dispersed nanosilica filler of 100 nm in size were used in this study. An epoxy/anhydride mixture was used as the base resin formulation. The nanosilica fillers were incorporated into the resin mixture to different filler loadings from 5 wt% to 40 wt% with or without silane coupling agents as the surface treatment. UV-Visible spectroscopy showed that the underfills with nano-size filler were transparent in the visible region even at high filler loading. The curing behavior and the Tg of the nanocomposite were studied using a modulated differential scanning calorimerter. It was found that the presence of the nanosilica could hinder the curing reaction, especially at the late stage of cure. The Tgs of the nanocomposites with untreated silica were found to decrease with the increasing filler loading. The measurement of the dynamic moduli from dynamic mechanical analyzer indicated that there was a secondary relaxation related to the filler-polymer interface. The coefficient of thermal expansion of the nanocomposite was measured using a thermal mechanical analyzer. The rheology of the nanocomposite was studied using a stress rheometer. It was found that the filler treatment could significantly reduce the viscosity of the nanocomposite and improve the processing capability of the underfill. Density measurements and moisture absorption experiments both indicated that the addition of nanosilica could increase the free volume of materials. The dispersion of the nanosilica in the cured composite materials was observed using scanning electron microscopy. Control samples with micron-size silica fillers were formulated and characterized for comparison. [ABSTRACT FROM AUTHOR]

The effects of under bump metallurgy (UBM) microstructures on the intermetallic compound (IMC) growth of electroplated and stencil printed eutectic Sn-Pb solder bumps were investigated. The process parameters and their effects on UBM surface morphology and UBM shear strength were studied. For the electroplating process, the plating current density was the dominant factor to control the Cu UBM microstructure. For the stencil printing process, the zincation process has the most significant effect on the Ni UBM surface roughness and Ni grain sizes. In both processes, the good adhesion of UBM to aluminum can be obtained under suitable UBM processing conditions. Samples with different UBM microstructures were prepared using the two processes. The resulting samples were thermal aged at 85 °C, 120 °C, and 150 °C. It was observed that the Cu UBM surface roughness had larger effect on the IMC growth and solder ball shear strength than the Ni UBM surface roughness. The thickness of Cu3Sn and Cu6Sn5 IMC depended strongly on the UBM microstructure. However, for Ni/Au UBM, no significant dependence was observed. More likely, the thickness of Au-Ni-Sn IMC near the IMC/solder interface was controlled by the amount of gold and the gold diffusion rate in the solder. Shear tests were performed after thermal aging tests and thermal/humidity tests. Different failure modes of different sample groups were analyzed. Electroless Ni UBM has been developed because it is a mask-less, low-cost process compared to electroplated Cu UBM. This study demonstrated that the process control was much easier for Ni UBM due to its lower reactivity with Sn material. These properties made Ni UBM a promising candidate for the lead-free solder applications. [ABSTRACT FROM AUTHOR]

Market demands and legislation are driving the electronics-manufacturing sector to move rapidly toward a lead-free future, with Pb-containing electronics products to be banned in Europe after 2006. Although the related scientific research has been undertaken for a decade, a number of technical complications still exist, which are further exacerbated due to the concurrent developments in miniaturization and multifunctionality of microelectronic products. As the packaging joint geometry shrinks toward a microscopic scale, the joint fabrication and reliability become extremely sensitive to the composition and resulting microstructure generated from the chosen joining process and materials. The current level of understanding of such issues is still in its infancy and therefore requires further fundamental study. Thermodynamic modeling is employed in this work as a computational tool to study the sensitivity of processing ranges (e.g., reflow temperature) and the resultant reliability of the micro joints by changing the alloying elements and their content in Sn-based lead-free systems. The work is implemented using the MTDATA program developed by the National Physical Laboratory. With a newly developed database containing critically assessed thermodynamic data appropriate for lead-free solder systems, MTDATA allows the prediction of the liquid-solid transformation and phase formation, for example, as a function of chemical composition and temperature. The paper emphasizes the formation and mass fraction of intermetallic precipitates of different phases in the bulk solder joints and the modeling is also validated through experimental work and recent literature. The results are expected to assist the optimization of processing parameters and cost-effective production using lead-free solders. [ABSTRACT FROM AUTHOR]

The reaction kinetics of a commercial fast cure nonconductive adhesive has been systematically investigated using differential scanning calorimetry. Samples were isothermally cured at temperatures from 120 to 160 °C and dynamically cured at ramp rates between 5 and 20 °C/min. A good agreement between the autocatalytic kinetic model prediction and experimental results was demonstrated. Deviation occurred at high degrees of cure for curing below 140 °C due to the occurrence of vitrification. Additionally, by comparing the dynamic cure prediction with the isothermal experiment, good agreements and equivalence were demonstrated. As such, it is possible to predict the isothermal reaction behavior of fast cure materials at high temperature provided that the variation between the actual temperature of the heating system and the setting temperature is not large. Furthermore, the effect of curing process on the adhesion strength has been demonstrated by testing the shear strength of lap joint specimens. It was found that the evolution of adhesion strength was largely dependent on the buildup of mechanical properties during the curing process. At low and medium degrees of cure, cohesive and adhesive failures were respectively observed, while at high degrees of cure, adhesion strength surpassing the shear strength of the solder mask was observed. The sharp increase in adhesion strength was observed to coincide with the gelation point marked by the crossover between the storage and loss modulii, thus suggesting that the contributors to adhesion strength include mechanical interlocking as well as chemical bonding, as evidenced by buildup of storage modulus and mechanical strength of the adhesive. [ABSTRACT FROM AUTHOR]

The detection of cracks in solder joints has been a challenge for the current nondestructive inspection techniques. This paper investigates the capability of a laser ultrasound and vibrometer inspection system to detect thermal cycle induced cracks in flip chip solder joints. Correlation coefficient analysis of ultrasound vibration signals is presented and compared with the previous error ratio method. The correlation coefficient method improves the system's signal-to-noise ratio. Optimum detection locations on the chip surface are investigated and an auto-comparison method is introduced to inspect a chip with fewer detection points and without the dependence on a reference chip. The results show that the system is able to identify thermally cracked solder joints from well-connected joints. When fully developed, the system can be put in-line and serve as a low-cost go/no-go inspection tool to screen out defects in solder joints at an early stage in the manufacturing process. It can also be used to evaluate the quality of many other types of electronic packages and other devices. [ABSTRACT FROM AUTHOR]

Anisotropic conductive adhesives (ACAs) are as promising interconnect materials for flip chip assembly in low cost, high-density, high-speed interconnection packages. We evaluated and compared several flip chip interconnects that use ACAs at the radio frequency (RF) and high-frequency range. The performance of high-speed circuits is limited by the package interconnect discontinuity which is due to large inductance and resistance in the high-frequency range. This discontinuity is determined by the interconnection geometry and materials used. For bumps on the integrated circuit (IC), we used Au studs, Au electroplated and electroless Ni/Au bumps, for the interconnection adhesives, we used two kinds of anisotropic conductive film (ACF) with a different dielectric constant. To evaluate the high frequency model parameters, which we based on an ACF flip chip model and network analysis, we took the high-frequency measurements of test flip chip vehicles that used different bonding materials. Furthermore, to demonstrate real applications for an ACF inter-connection at the RF and high-frequency range, we applied ACF flip chip technologies to assemble a passive device that uses an RF integrated passive device. We also applied these technologies to an active device that uses a highly integrated monolithic microwave (IC) device on an RF module. Moreover, we compared the high- frequency characteristics of these devices with those of flip chip assemblies fabricated with conventional methods such as solder ball interconnection. [ABSTRACT FROM AUTHOR]

Adhesive flip chip interconnect has been recognized as a promising substitute for solder interconnection due to its fine- pitch, lead-free, and low-temperature processing capabilities. As adhesives are made of polymers, moisture absorption by the polymeric resin remains as one of the principal contributors to adhesive joint failure mechanisms. In this research, the reliability performance of the adhesive flip chip in the pressure cooker test and moisture sensitivity test conditions was investigated. The failure modes were found to be interfacial delamination and bump/pad opening which may eventually lead to total loss of electrical con. tact. Different sizes of bump/pad opening in the interconnections were discussed in the context of the significance of mismatch in coefficient of moisture expansion (CME) between adhesive and other components in the package, which induces a hygroscopic swelling stress. The effect of moisture diffusion in the package and the CME mismatch were also evaluated from the standpoint of finite element modeling. In this study, it is concluded that hygroscopic swelling assisted by loss of adhesion strength upon moisture absorption is responsible for the moisture-induced failures in these adhesive flip chip interconnects. [ABSTRACT FROM AUTHOR]

The manufacturing and reliability of a novel type of first-level interconnections is described. Anisotropic conductive and nonconductive adhesives are used to electrically bond flip chip ICs with a pitch of 60 and 40 μm to flexible substrates. Analyses cover the initial state of the samples as well as their performance in the JEDEC moisture sensitivity level assessment and subsequent life testing. From the different behavior of the two types of adhesives a failure mechanism issues for the reflow-soldering test. [ABSTRACT FROM AUTHOR]

Minimizing device side die stresses is especially important when multiple copper/low-k interconnect redistribution layers are present. Mechanical stress distributions in packaged silicon die resulting during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, measurements of thermally induced stresses in flip chip on laminate assemblies are presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from -40 to +150°C. Using these measurements and ongoing numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages. [ABSTRACT FROM AUTHOR]

The fine-scale of interconnect structures in the back-end of modern microelectronic devices makes them Susceptible to unusual, scale-sensitive deformation phenomena during processing or service because of internal stresses induced by thermal expansion mismatch between adjoining materials. During thermo-mechanical cycling associated with processing or service, dimensional changes may occur in Cu interconnect lines embedded in a low-K dielectric (LKD) due to plasticity/creep, strain incompatibilities may arise between Cu and LKD due to diffusionally accommodated interfacial sliding, and Cu lines may crawl or migrate via plastic deformation and interfacial sliding under far-field shear stresses imposed by the package. Although small, these effects can have a pronounced effect on component reliability. This paper presents shear-lag based modeling approaches to simulate out-of-plane (OOP) strain incompatibilities which arise within a single-layer Cu-LKD back-end structure (BES) during back-end processing, and in-plane (19) deformation and migration of Cu interconnects within the BES after the chip is attached to a flip-chip package. Both models incorporate a previously developed constitutive interfacial sliding law, and help rationalize experimentally observed interfacial strain incompatibilities within Cu-LKD BES. [ABSTRACT FROM AUTHOR]

Flip-chip plastic ball grid array (FC-PBGA) pack. ages are widely used in high performance components. However, its die back is normally under tensile stress at low temperatures. This paper presents a probabilistic mechanics approach to predict the die failure probability in the FC-PBGA qualification process. The methodology consists of three parts: i) die strength test using four- point bending (4PB) method, ii) the radius of curvature (ROC) measurement of the assembled FC-PBGA at room temperature, and iii) finite element method (FEM) stress analysis. In the first part, a specially modified three-parameter Welbull function is used to fit the 4PB die strength data. The three parameters of the Weibull distribution are used as the sole description of the cracking characteristics for a specific die process in the late analysis. In the second part, the measured ROC of FC-PBGA at room temperature is used as a calibration input to determine the effective stress-free temperature of the FC-PBGA. It is used to overcome the difficulty caused by process-induced residual stress and unknown material properties. This effective stress-free temperature can be used in the stress analysis in the third part of the mentioned methodology. In the third part, the FEM is used to calculate the die stress distribution under most critical stage of certain qualification process. The calculated stress distribution is combined with the Weibull distribution parameters of die strength test to predict the die failure percentage. [ABSTRACT FROM AUTHOR]

The article presents study which correlates the material properties to reliability performance of anisotropic conductive adhesive (ACA) flip chip packages. A long with demands for cheaper, smaller and higher performance devices, microelectronics packaging technology is also moving toward lower cost, finer pitch, higher electrical performance and better reliability. Flip chip technology is the main candidate that meets all these demands. Lead based solder materials have been used for interconnections in flip chip technology for many decades. Among the electrically conductive adhesives, the ACA is a promising candidate that shows potential for further pitch reduction.

The article focuses on the development of single-phase liquid cooling techniques for flip chip ball grid array packages with high flux heat dissipations. The increasing demand for high performance and multiple functionality in electronic systems and devices has presented great challenges in the thermal management. Conventional air cooling techniques are reaching their limits for applications in areas such as cost-performance and high-performance electronics. On the other hand, single-phase liquid cooling techniques with microchannel heat sinks provide a methodology for removing heat fluxes in the order of 100 W/ square cms. MicroChannel heat sinks afford unique heat transfer enhancement feature compared with heat sinks with normal-sized channels.

The article focuses on design and analysis of wafer level chip scale packaging (WLCSP) with a double pad structure. The current trend of electronic devices is toward more integral functionality, higher speed, and better electrical performance; thus, an electronic package that has lower signal degradation, higher reliability and lower cost is of great demand. WLCSP technologies provide a very promising alternative in fitting the high performance requirements for today's electronic packaging applications. As compared to the flip chip packaging, almost all of the package process is conducted at the wafer level, and it does not need an underfill material to protect solder joints from thermal deformation.

The article discusses the influence of temperature and humidity on the adhesion performance of underfill material (epoxy cured with acid anhydride), which was evaluated by die shear test after exposure to various conditions. Flip chip is a packaging approach in which the integrated circuit is connected to the substrate through solder joints with the active side facing down. Flip chip technology is a packaging approach to meet high input/output count due to its area array of interconnection onto substrate. In addition, it has fast signal propagation because of its short interconnection path. It is a key method to improve packaging density, reliability, and cost of electronic products.

This paper reports the experimental results on the contact resistance of curable polymer gel thermal interface materials (TIMs) that have different mechanical properties due to difference in the rheology of the polymers. A semi-analytical model for the prediction of the thermal contact resistance of cured gel TIMs is also introduced in this paper. A novel method of finding the transition from grease type behavior to gel type behavior, which is very important for post reliability stress performance, based on G' (storage shear modulus) and G" (loss shear modulus) measurements is reported. Further, post thermal cycling thermal resistance degradation rate of gel TIMs are related to the ratio of C and G". Finally, design guidelines for gel TIMs for use in flip-chip packages comprising heat spreaders are proposed. [ABSTRACT FROM AUTHOR]

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package. [ABSTRACT FROM AUTHOR]

No-flow underfill has greatly improved the production efficiency of flip-chip process. Due to its unique characteristics, including reaction latency, curing under solder reflow conditions and the desire for no post-cure, there is a need for a fundamental understanding of the curing process of no-flow underfill. Starting with a promising no-flow underfill formulation, this paper seeks to develop a systematic methodology to study and model the curing behavior of this underfill. A differential scanning calorimeter (DSC) is used to characterize the heat flow during curing under isothermal and temperature ramp conditions. A modified autocatalytic model is developed with temperature-dependent parameters. The degree of cure (DOC) is calculated; compared with DSC experiments, the model gives a good prediction of DOC under different curing conditions. The temperature of the printed wiring board during solder reflow is measured using thermocouples and the evolution of DOC of the no-flow underfill during the reflow process is calculated. A stress rheometer is used to study the gelation of the underfill at different heating rates. Results show that at high curing temperature, the underfill gels at a lower DOC. Based on the kinetic model and the gelation study, the solder wetting behavior during the eutectic SnPb and lead-free SnAgCu reflow processes is predicted and confirmed by the solder wetting tests. [ABSTRACT FROM AUTHOR]

The physical contact characteristics of a nonconductive adhesive type of flip-chip-on-glass assemblies during manufacturing process and temperature variation is explored by using three-dimensional (3-D), nonlinear finite element analysis together with the so-called "death-birth" simulation technique. The contact mechanics of two typical types of micro-bump bonding technologies, i.e., the metal (i.e., Au alloy) and composite bumps, are extensively addressed, and substantially compared. The validity of the modeled contact characteristics is further verified by an electrical contact resistance measurement that adopts a four-point probe method and an equivalent circuit approach. Finally, through the parametric study, the dependence of the contact stress at the bumps and the peeling stress at the UV resin on a number of geometry and material design parameters is effectively identified. Both the modeling and experimental results show that the bump height uniformity is a key factor in the overall contact performance of the assembly, and should not be neglected from the analysis. In addition, it is identified that the composite-bump bonding technology outperforms the metal-bump assembly as a whole in terms of the contact consistency and stability due to its better bump uniformity and compliance. Furthermore, it is surprising to find that there is a full disagreement in the parametric results of the bump height and Al thickness between the shorter bump and the taller among those nonuniform bumps, and more importantly, an increase of the bump height or a reduction of the Al overcoat thickness would enhance the overall contact performance of the assembly. [ABSTRACT FROM AUTHOR]

This paper presents a systematic study on moisture absorption in uncured underfill based on epoxy cured with acid anhydride [methylhexahydrophthalic anhydride (MHHPA)] and epoxy cured with non-acid anhydride curing agent. The influence of absorbed moisture on curing properties, thermomechanical property, and adhesion property of underfill after curing has been investigated. For epoxy cured with non-acid anhydride, the moisture absorption is low, and the absorbed moisture has no significant effect on the properties of cured underfill materials. For epoxy cured with acid anhydride, the moisture absorption before curing can be more than 2.0%, and the absorbed moisture can affect the properties significantly. The absorbed moisture can catalyze the curing reaction between acid anhydride and epoxy. The glass transition temperature of the cured samples is reduced after the underfill absorbs the moisture before curing. The adhesion strength decreases dramatically after the underfill absorbs the moisture before curing. [ABSTRACT FROM AUTHOR]

The effects of exothermic heat generated during underfill curing on the integrity of the solder bumped package, which is an important issue for the package reliability, have been overlooked. In this study, theoretical exotherm of underfill materials during underfill curing has been calculated using a differential scanning calorimeter (USC) at cure temperature range from 100 °C to 200 ° C. The calculated exotherm was compared with the exotherm profile measured at the typical cure temperature. The effects of cure temperature, amount of underfill, and initial underfill curing temperature on the exotherm profile of underfill materials have been investigated. [ABSTRACT FROM AUTHOR]

In this work we study how the endurance performance of electrically conductive adhesive interconnections of flip chip integrated circuits with a pitch of 200 and 150 pm on flexible substrates is affected by varying environmental conditions. This is accomplished by comparison of offline and online control measurements that are carried out to monitor the electrical resistance in temperature-humidity and temperature cycling stress tests. From the gradual degradation of the resistance with time and the failure analysis, it is conjectured that periodic absorption and desorption of moisture forms one of the more important failure mechanisms in this type of assembly. [ABSTRACT FROM AUTHOR]

In recent year, the combination of III-V semiconductor devices with Si manufacture techniques to develop optoelectronic integrated circuits (OEICs) has been widely studied. Flip-chip bonding has been used widely because superior electrical performance, proper reliability, efficient heat conduction and self-alignment are the advantages of this technology. Because optoelectronic devices are quite sensitive to temperature and stress-induced degradation, the bonding medium should be chosen to have high thermal conductivity and stress-relief. The indium (In) based alloy solders are generally recognized to provide lower melting point, longer fatigue life, and higher thermal conductivity. In this study, we have successfully developed a fluxless bonding process to manufacture In-Au micro joint between laser diode and silicon substrate. During the soldering, the solder reacts with the bonding pad metal to form the intermatallic compound at the interface. Such an intermetallic compound is crucial to the quality of solder joint. We utilized SEM, EDX, and XRD to observe and identify the intermetallic compounds. These results indicate that AuIn[sub2] is the main intermetallic phase and plays an important role on the quality of joints. Moreover the reliability of solder joint is strongly depended on the initial microstructure. The optimum bonding temperature is found to be about 200°C by the microstructure of the solder joint by SEM and optoelectronic characteristics (I-V and L-I) of the laser diodes. Shear force test has also been performed according to MIL-STD-883C. The results reveal the fact that all well-boned devices meet the shear force requirement. To verify the thermal stability, the bonded samples were tested by thermal shock test. The bonded specimens endure 500 cycles... [ABSTRACT FROM AUTHOR]

Oxide-confined top-emitting 850 nm and bottom-emitting 980 nm vertical-cavity surface-emitting laser (VCSEL) 8 x 8 arrays were designed and fabricated for applications of optical interconnects. The arrays were flip-chip bonded onto sapphire substrates that contain complimentary metal-oxide-semiconductor (CMOS) driver and fan-out circuitries. The off-sited bonding contacts and minimized bonding force produced very high yield of hybridization process without causing damage to the VCSEL mesas. The hybridized devices were further mounted either on printed circuit board (PCB) or in 68-pin pin-grid-array (PGA) packages. The transparent sapphire substrate allowed optical outputs from the top-emitting VCSEL arrays to transmit directly through without additional substrate removal procedure. Lasing thresholds below 250 µA for 850 nm VCSELs and 800 µA for 980 nm VCSEL were found at room temperature. The oxide confinement apertures of VCSELs were measured to be around 6 µm in diameter. High-speed data transmission demonstrated a bandwidth of up to 1 Gbits/s per channel for these hybridized VCSEL transmitters. [ABSTRACT FROM AUTHOR]

Anisotropic conductive film (ACF) consists of an adhesive polymer matrix with dispersed conductive particles. In flip-chip technology, ACF has been used in place of solder and underfill for chip attachment to glass or organic substrates. The filler particles establish the electrical contacts between the interconnecting areas. ACF tip-chip bonding provides finer pitch, higher package density, reduced package size and improved lead-free compatibility. Nevertheless, the interconnection is different from traditional solder joints, the integrity and durability of the ACF interconnects have major concerns. Failures in anisotropic conductive film (ACF) parts have been reported after temperature cycling, moisture preconditioning and autoclave. The failures have not been well understood and have been attributed to a wide variety of causes. This paper investigates the failure mechanism of ACF using finite element simulation. From a failure-initiation point of view, the response of ACF packages to environmental (temperature and humidity) exposure is very different from standard underfilled packages. These differences cause the ACF package to fail in different ways from an underfilled package. Simulation results have shown that moisture-induced ACF swelling and delamination is the major cause of ACF failure. With moisture absorption, the loading condition at the interface is tensile-dominant, which corresponds to lower interface toughness (or fracture resistance). This condition is more prone to interface delamination. Therefore, the reliability of ACF packages is highly dependent on the ACF materials. The paper suggests a new approach toward material selection for reliable ACF packages. This approach has very good correlation with experimental results and... [ABSTRACT FROM AUTHOR]

When a bare die is flipped directly onto the printed circuit board (PCB) during chip-on-board assembly, it becomes exposed to a number of factors, which could influence its electrical performance. Although the mechanical integrity of flip-chip devices has been thoroughly studied, there is very little evidence of detailed investigations of the electrical performance of these devices. The present paper aims to bridge this gap by studying the electrical parameters of flip chip devices and analysing the changes occurring following assembly. A dedicated test chip comprised of passive and active semiconductor devices was designed for the study. Two different types of tacky flux and underfill materials were used in the flip chip assembly process. The flip chip structures were then subjected to various environmental stress techniques for accelerating ageing. Electrical parameters of the devices such as threshold voltage, I-V characteristics, off-state leakage current, current gain, and resistance were measured at various stages of the programme. A slight change in device parameters was observed immediately after assembly. Further change in some device parameters was observed after environmental stressing. The paper investigates the mechanisms that could be responsible for the changes, such as mechanical stresses introduced during the flip chip process or ionic contamination inherent to the assembly process. [ABSTRACT FROM AUTHOR]