Search

For power delivery applications, a method for reducing impedance is through the addition of decoupling capacitors (decaps). In this article, we propose a knowledge-based optimization method to determine decap design in power delivery networks (PDNs). The proposed method provides the optimized PDN with the minimum number of decaps by iteratively assigning the decaps that maximize the frequency range where the target impedance is satisfied. In addition, by integrating the time-domain analysis into the proposed method, a voltage response arising from any arbitrary load current sources is guaranteed within the threshold level while preventing the over-design problem. Unlike the recent random search-based methods (genetic algorithm and machine learning (ML) etc.) requiring a large number of PDN simulations for learning and selection, the proposed method determines effective decaps through multiple steps based only on domain knowledge, significantly reducing the number of PDN simulations and computational cost to obtain the optimized decap solution. We apply the proposed method to three different PDN models. The results show that only 1.3% of the computing time is required to achieve the optimized decap design compared with the ML-based method while having the same number of decaps as the optimal number obtained by the full-search simulation. [ABSTRACT FROM AUTHOR]

Heterogeneous integration allows multiple silicon dies of various technologies and complexity to communicate efficiently using second-level interconnects, interposers, in a single package. The interposer also provides a low-impedance power delivery path between multiple independent power domains. Although the channels are very short and the signal integrity is not a challenge, the huge increase in the transient current of multiple dies and the unique clocking architecture makes the supply noise and timing jitter the limiting factors in designing high-performance multidie systems. In this article, accurate analysis and characterization techniques of noise and jitter in multidie interfaces are presented. Power supply noise and empirically derived jitter models are correlated with measurements and detailed transistor-level circuit simulations, respectively. [ABSTRACT FROM AUTHOR]

The reliability of microcontrollers (MCUs) became crucial considering their massive use in numerous applications, especially in severe environments. Thus, the robustness against electromagnetic disturbances, particularly for the power supply network, is a major issue that we have to solve in order to acquire a comparative advantage on the market, or simply to assure the goods and people safety. Therefore, the fast transient burst test of integrated circuits is studied in relation with the IEC 61000-4-4 standard. The stress propagation mechanisms are highlighted, as well as the common-mode -to-differential-mode conversion. A novel measurement method was developed to validate this conversion. Finally, this paper opens new perspectives of improvement of the MCU robustness, such as package modification, for this kind of aggression, and thus their reliability. [ABSTRACT FROM AUTHOR]

The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented. [ABSTRACT FROM AUTHOR]

We propose a new simple and low-cost alignment method utilizing electric contact for die stacking on an interposer or a printed circuit board. Without any expensive aligning/bonding equipment assisted by microscopy, we successfully stacked and bonded two silicon dies on a printed circuit board achieving alignment accuracy of $20~\mu \text{m}$ by utilizing only cheap equipment: manual micropositioners, a stage, a stand, a heat gun, a hot plate, and a power supply. In the proposed method, conductive alignment marks are fabricated on the bonding surfaces, and the electric contact between them are used to characterize misalignment. Therefore, the proposed method does not require any expensive complex microscopy equipment for alignment. In addition, alignment can be quickly and simply examined in situ by detecting electrical conduction during bonding. In experiment, alignment accuracy better than $20~\mu \text{m}$ and 100% bonding yield was measured in testing of 1800 bonds connecting two silicon interposer dies which were stacked on a printed circuit board by the proposed method. [ABSTRACT FROM AUTHOR]

Central processing unit (CPU) for any computer generally operates at constant power supply voltage. Normally in product specification, this power supply voltage has tolerance margin close to ±5%. It is shown in the previous works that for every millivolt drop in power supply voltage, the operation frequency of a chip reduces by about 2 MHz. This voltage drop occurs when CPU starts drawing current from the power supply. It is desirable to maintain the supply voltage within the specification of allowed voltage fluctuations so that the CPU can run at the target operating frequency, for a given package inductance and die decoupling capacitance. In this paper, power supply noise reduction method for multicore CPU in a given silicon chip has been considered. The concept of variable frequency has been applied on every core to minimize the noise by changing the current ramp of a multicore system. This reduces the dI/dt, and therefore for fixed package inductance and die decoupling capacitance, the power supply noise reduces. In this paper, four-core CPU has been taken and also shown the reduction of noise by changing the current ramp using variable clock frequency on each core and also by staggering the time when each core will start clocking. [ABSTRACT FROM PUBLISHER]

In this paper, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation. These voltage fluctuations occur when a given chip comes out from the sleep mode to the active mode. This causes the chip to draw a hasty current, which in turn produces LdI/dt noise. That causes the voltage to drop and also to oscillate at the power delivery network’s resonance frequency. This power supply noise causes clock jitter. The voltage-controlled oscillator of the proposed PLL is designed at 45-nm technology such that when there is supply voltage variation, it is automatically corrected by a feedback methodology having only 11-ps response time delay, compared to 588-ps clock period. Simulation result shows that, for the proposed new PLL design, the number of places where the clock periods are altered due to this power supply voltage fluctuation is reduced. The performance of the proposed PLL design in terms of reduction of clock jitter, caused by the variation of power supply voltage and the flatness of the frequency versus power supply voltages, is tested by feeding the clock to a circuit (c17 of ISCAS’85) for the conventional methodology and also for our new methodology. It has been shown that, using the proposed method, the clock jitter caused by the power supply noise can be reduced by about 50% compared to the conventional design methodology. [ABSTRACT FROM AUTHOR]

An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented. Semianalytical expressions for jitter are derived based on separating the large signal response and the small signal noise response and subsequently combining the results. Proposed simplified relations enable the designers to estimate the PSIJ based on a single bit simulation. Proposed methods are validated on several examples of voltage-mode driver circuits, designed in different technologies and in the presence of different types of noise sources. [ABSTRACT FROM PUBLISHER]

Power supply rejection peaking in low-dropout (LDO) voltage regulators can lead to reduced bandwidth and efficiency. This paper presents a new design method by combining power transmission lines (PTLs) with LDOs for enhancing its bandwidth and efficiency. This approach is applicable for LDOs regulating high-speed I/O drivers. The PTL combined with decoupling capacitors on the package or board is used to mitigate the power supply noise (PSN). This methodology is demonstrated using printed circuit board test vehicles with off-the-shelf components. Compared to conventional approaches, the PTL solution showed an ~80% lower PSN. [ABSTRACT FROM AUTHOR]

The performance of silicon chip depends on the operating voltage of the chip. The chip should be designed using proper power and ground bond pads to minimize the power supply noise. When the chip starts working from the sleep mode, then the sudden rise in current inside the chip causes LdI/dt noise. This noise reduces the power supply voltage, which in turn reduces the operating frequency of the chip. This makes the chip manufacturer to sell products of high-performance chips at a lower operating frequency. In order to ramp this current slowly, an innovative and fundamentally new method is implemented. In this proposed method, we have increased the operating frequency inside the chip slowly (from f_{\textrm {min}} to f_{\textrm {max}}$ ) to control the current ramp and at the same time performed clock gating (CG) to minimize noise by suppressing the current drawn by the device. We have applied this concept of variable frequency together with CG in a 3-b up counter to demonstrate that one can construct a design where the clock can be modulated during its functional operation without any functional failure. [ABSTRACT FROM PUBLISHER]

This paper presents a simple power delivery design for mitigating the coupling of power supply noise in mixed-signal electronics. Digital circuitry operating at high data rates generates supply noise that can interfere with sensitive RF components. Currently used methods, such as split planes and ferrite beads, have limited isolation bandwidth and can pose difficulties for signal integrity. Electromagnetic bandgap (EBG) structures have been shown to exhibit excellent noise isolation characteristics. In this paper, a set of parallel digital buffers and a low-noise amplifier are powered by a power transmission line (PTL) instead of a voltage plane. An embedded bandstop filter in the PTL significantly reduces the amount of coupled noise between the digital and RF supply voltage pins. In addition, a source terminating the PTL provides good noise isolation with even lower supply noise. The proposed methods are easy to design and implement and use much less space than an equivalent EBG structure. Test vehicles using these proposed methods, as well as using an EBG structure, were fabricated and tested with regard to power supply noise, jitter, and noise isolation. The proposed methods show up to 13-dB decrease in coupled power compared with the EBG. In addition, the measured supply noise is decreased by 75% and the total jitter in the transmitted eye diagram is improved by 23% using the proposed method. [ABSTRACT FROM PUBLISHER]

In this paper, we have shown an analytical technique to scale the power delivery solutions for a given integrated circuit (IC) chip that can draw currents to cause enough inductive noise for the IC to fail. This scaling method will also provide the optimum package solutions to minimize the cost of IC products. This method can be very useful to determine the package and die design methodology at the initial phase of the design cycle of the chip. [ABSTRACT FROM AUTHOR]

Advances in 3-D integrated circuit (3-DIC) technology have allowed for advantages in integration, system speed, and power consumption for digital systems. In systems operating at very high data rates with large data width, the effect of simultaneous switching noise (SSN) can, however, drastically affect system performance. Therefore, the effect of SSN in the power delivery network (PDN) design of a through silicon via (TSV)-based 3-D stack has been investigated in this paper, and eye diagrams have been simulated in each level of the stack to analyze power supply noise and transition jitter. Using a novel PDN design concept based on constant voltage power transmission lines, it is shown that this new PDN design can significantly improve signal quality in a 3-DIC application. The 3-D system considered here consists of a PCB, an interposer, and three IC dies. Each IC contains a TSV layer, PDN, and digital logic. [ABSTRACT FROM PUBLISHER]

3-D integration creates vast opportunities to improve performance and the level of integration in nanoelectronic systems. However, 3-D integration presents many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2-D systems. In this paper, an analytical physical model is derived to incorporate the impact of 3-D integration on power supply noise. The model has less than 4% error compared to SPICE simulations. Based on the model, design guidelines and opportunities for reducing power supply noise, such as inserting “decap” die and through-vias, are discussed in this paper. [ABSTRACT FROM PUBLISHER]

A return-path decomposition method that eliminates artificial return-path discontinuities is presented. The methodology is applied to over 2 Gb/s simultaneous switching output analysis of a low-cost wire-bonding-type ball grid array package with a 32-bit double-data rate interface. The analysis is based on true transistor-level signal–power simulation and a large-scale, full-wave full 3-D boundary element method field solver package model. The simulation results suggest that in a weak return-path system, such as a wire-bonding-type package, the I/O performance is mainly dominated by the signal channel design rather than the power supply design in over 2-Gb/s region. The power supply acts as a secondary signal return path rather than as a noise source. The power supply design should be more focused on the main driver/predriver power supply noise interference in those systems. [ABSTRACT FROM PUBLISHER]

A power electronic device's lifetime depends on its maximum operating temperature and the temperature swings it is subjected to. Heat sinks employing phase change materials (PCMs) can be employed to achieve a temperature reduction, but only for a limited duration. This makes such heat sinks appropriate for use in applications with high peak loads but with low duty cycles. The heat sink is modeled using the thermal resistors and capacitors (RCs) network approach, and an optimization procedure for designing a hybrid air-cooled heat sink containing PCM is developed, yielding a maximum possible temperature reduction for a given application. It is shown that air-cooled heat sinks employing pure PCMs are best suited for applications with pulses width lengths of several minutes with a period of several tens of minutes. In order to achieve a faster response of the PCM, the concept of PCM-metal foam is explored and modeled. Experimental data is presented which confirms the validity of the thermal RC network approach. [ABSTRACT FROM PUBLISHER]