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This brief presents the experimental validation of a low-power, large output swing, class-AB buffer amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input amplifiers and a dual-path push–pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35- ${\mu }{\text{m}}$ technology and supplied from a 3-V supply, the proposed buffer amplifier can drive a 1-nF column line load within a 1.11- ${\mu }\text{s}$ settling time under a full voltage swing, while drawing only 1.6 ${\mu }\text{A}$ quiescent current and occupying 5562 ${\mu }{\text{m}}^{{2}}$ of silicon area. As compared to the state of the art, the best figure of merit (pF/ ${\mu }\text{s}{\cdot } {\mu }\text{A}$ ) is found.

This brief presents a low-power, area-efficient three-stage CMOS operational transconductance amplifier (OTA) suitable for very large capacitive loads, ${C} _{L}$ . A single Miller capacitor and an inverting current buffer embedded in the input stage are exploited to implement the frequency compensation network. An additional feed-forward path and a slew rate enhancer are also utilized to improve the large-signal transient response. Detailed small-signal analysis reveals that the proposed OTA does not exhibit an upper limit of drivable ${C} _{L}$ . The OTA is fabricated in a standard 0.35- ${\mu }\text{m}$ technology and occupies 0.0027 mm2 of die area. Under 1.4-V supply and 6.36- ${\mu }\text{A}$ quiescent current consumption, it provides a dc gain greater than 110 dB and is stable for any ${C} _{L}$ larger than 5 nF. Comparison with the state of the art shows remarkable improvement of both small- and large-signal performance.

A power management integrated circuit for an energy autonomous device is presented. It is based on a configurable 2:1 switched capacitor converter that is capable of delivering a maximum current to always-on and duty-cycled loads equal to 5 $ \mu \text{A}$ and 2 mA, respectively, from a thin-film 4.2-V lithium battery. The circuit is designed and implemented using the 0.8- $ \mu \text{m}$ CMOS transistors of a BCD technology and exploits off-chip ceramic capacitors. Power conversion efficiency as high as 93% in the active mode and 80% in the sleep mode, despite the large variation range of the output current, is achieved.

A CMOS class AB variable gain Voltage Feedback Current Operational Amplifier (VFCOA) is presented. The implementation is based on class AB second generation current conveyors and exploits an electronically tunable transistorized feedback network. The circuit combines high linearity, low power consumption and variable gain range from 0 to 24 dB with nearly constant bandwidth, tunable from 1 to 3 MHz. A prototype has been fabricated in a 0.5-um technology and occupies a total area of 0.127 mm2. The VFCOA operates using a 3.3-V supply with static power consumption of 280.5 uW. Measurements for maximum gain configuration show a dynamic range (1% THD@300kHz) of 87.5 dB and a THD lower than -40dB for an output current 23 times the bias current. This work has been supported in part by the Spanish Direccion General de Investigacion under grant TEC2010-21563-C02-01/MIC.

The paper presents the derivation of Miller formulas for weakly nonlinear feedback networks. The expressions found are simple and compact and constitute a generalization of the well- known linear case. As an application example, the formulas are applied to a common-emitter amplifier to straightforwardly derive the closed-form expressions of second- and third-harmonic distortion factors. The results found, validated by Spectre simulations with a VBIC bipolar model, allow to understand in depth the contribution of each nonlinear element.

A supplementary linearization technique for CMOS differential pairs with resistive source degeneration is proposed. The approach exploits an auxiliary (degenerated) differential pair to drive the bulk terminals of the main pair. Transistor-level simulations on a design using a 0.25-mum process and powered with 2.5 V and 1 mA, show that total harmonic distortion (THD) in the voltage-to-current conversion is decreased by 10 dB (for an input differential signal with a peak amplitude of 0.5 V and for frequencies up to 100 MHz) compared to the traditional source-degenerated transconductor. This THD improvement is achieved with a negligible increase in power consumption.

Two CMOS current output stages are presented. Compared to the traditional solution, which exhibits unbalanced operation, the proposed ones exploit an auxiliary high-gain feedback loop which provides differential drive, thereby highly improving the common-mode rejection ratio (CMRR). Prototypes are designed and fabricated in a 0.35-mum technology and experimental results confirm that a CMRR increase greater than 20 dB can be achieved and, for one of the two solutions, without increasing the voltage requirements.

This brief introduces and develops a novel frequency compensation technique for three-stage operational transconductance amplifiers. The new compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the compensation scheme, an amplifier has been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances

A novel current operational amplifier, in which the traditionally adopted input current follower is replaced by an input stage that exhibits current gain and single-input-to-differential-output conversion, is presented. Due to this, increased values of both dc gain and common-mode rejection ratio (CMRR) are obtained in the overall amplifier. A CMOS implementation, along with postlayout simulations, which are in good agreement with expected data, is also included. The proposed design is supplied with 2.5 V, dissipates 0.7 mW, and provides a nominal dc gain, a gain-bandwidth product, and a CMRR (at dc) of 72 dB, 28 MHz, and greater than 100 dB, respectively

The performance of the Miller integrator cells based on current feedback OpAmps (CFOAs) is evaluated. Inverting and noninverting structures are analyzed and compared to traditional implementations using voltage OpAmps (VOAs). Fundamental relations, useful for design purposes, are also carried out. CFOA-based implementations were found to exhibit lower dc gain and higher relative error in the unity-gain frequency, thereby, limiting the high-frequency potential. The higher CFOA bandwidth can be traded for higher quality factors. Experimental data, in excellent agreement with expected results, are included.