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This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB $\boldsymbol {\Omega }$ transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a $0.11\, \boldsymbol {\mu }\text{m}$ CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving $50 \boldsymbol {\Omega } $ loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 $\boldsymbol {\mu }\text{m}\,\,\boldsymbol {\times } 110\,\,\boldsymbol {\mu }\text{m}$ in area.

This work presents a novel amplifier architecture which is the input stage of an analog front end targeting the acquisition of biological signals with low voltage supply (1.2 V), low noise, high Common Mode Rejection Ratio (CMRR) and high current efficiency. A prototype, designed and fabricated in a 130 nm CMOS technology, was characterized by simulations and measurements. Our preamplifier presents one of the lowest noise levels reported up-to-date (over the considered bandwidth) while presenting a very competitive performance in other important features. Results from measurements show a bandwidth from 20 Hz to 11 kHz, a CMRR higher than 70 dB, an equivalent input-referred noise as low as $1.3~ \mu {\text V}_{rms}$ . The Noise Efficiency Factor (NEF) at 2.5 and Power Efficiency Factor (PEF) at 7.5 are remarkable results.

This paper presents an integrated ultra-low-power (ULP) wireless sensor system-on-chip (SoC) that can be used for voltage sensing in both Internet of Things applications and bio-potential monitoring. In order to increase the energy efficiency of the analog front-end (AFE), we propose a noise and power efficient push-pull low noise instrumentation amplifier (LNIA) with a built-in ripple reduction loop based on capacitor reuse. A low-power ISM-band harmonic injection locked on-off-keying transmitter (OOK-TX) is also implemented for energy efficient wireless connectivity. Circuit implementations, design considerations, and detailed analysis are presented to improve the overall energy efficiencies of the SoC including the AFE, TX and, the power management unit. The proposed ULP-SoC is fabricated in 130 nm CMOS technology with a total area of 1.92 mm2. The total power consumption of the proposed system-on-chip is $197.1~\mu \text{W}$ which is one of the lowest among state-of-the-art wireless sensor SoC.

An analog front-end (AFE) circuit comprising an amplifier module, a peak detector, and a timing discriminator has been designed to facilitate the target identification for direct time-of-flight (dToF) LiDAR. The amplitude saturation error (ASE) is compensated in this article for the intensity determination, which is conducted based on the combination of the pulse width and peak detector. Together with the improved walk error compensation scheme, the proposed AFE circuit can attain the distance and intensity information simultaneously with lower cost and larger dynamic range. A specific frequency compensation method is proposed with a shunt feedback TIA, which improves the stability and mitigates the impact of the package parasitics. The measured -3-dB bandwidth, transimpedance gain, and the input-referred noise current are 281 MHz, 86 dB $\Omega $ , and 4.68 pA/ $\surd $ Hz respectively. The proposed AFE circuit, which is fabricated in $0.18~\mu \text{m}$ CMOS technology, achieves the distance accuracy of ±30 ps and the intensity accuracy of ±4% in the dynamic range of 1:5000 without gain control scheme.

This paper presents a novel CMOS peak detect and hold (PDH) circuit scheme for pulsed time of flight (ToF) Lidar application. The proposed PDH circuit, which is one part of analog front end (AFE) circuit of Lidar receiver, is used to widen the narrow input pulse width, aiming to easily digitize the pulse amplitude through a low-speed and low-cost ADC in pulsed ToF Lidar application. The reset voltage clamped to the common-mode level of the input pulse voltage is beneficial to reduce the pedestal error voltage. Meanwhile, the auto-adjust charging current scheme is employed to decrease the peak error through rejecting the overshoot voltage in the proposed PDH circuit. The circuit was implemented and fabricated in a 65-nm CMOS technology. The proposed PDH circuit can detect the pulse voltage with a pulse amplitude range from ~20 mV to ~500 mV and a minimum pulse width of 5 ns. The measured results show that the maximum absolute and relative errors are less than 16 mV and 4.5%, respectively. The layout area of the proposed PDH circuit is equal to $0.17\times 0.14$ mm2.

This paper presents an Analog Front-End for integrated Wake-Up Radios. The proposed Analog Front-End is composed of an envelope detector, a Schmitt trigger and a biasing block and has three distinctive features: i) clockless solution, which does not require an always-on oscillator; ii) an envelope detector with band-pass response which leads to smaller capacitance, thus easier integration, and low-frequency noise suppression; iii) temperature compensated biasing scheme. An active scheme for the detector is used based on MOSFETs operated in the subthreshold region with a self-biased topology. Advantages and drawbacks of the proposed architecture are analyzed. A prototype was fabricated in the STMicroelectronics 90-nm BCD technology. The overall power consumption, excluding the biasing block, is 36 nW at 1.2 V. A 10 -3 Bit Error Rate is measured with a 771-MHz, 2-kbit/s OOK modulated input signal with -46 dBm power at room temperature and at -20 °C, and with almost -43 dBm power at 60 °C.

Biofuel cell as a natural energy source is a promising biocompatible technology which harvests the blood glucose into usable energy and replaces the toxic lithium-based battery solutions. However, the promise of this perennial non-toxic power is tempered by its unstable operation and low-voltage outputs leading to very limited operational lifetimes. This paper demonstrates a glucose-powered analog front-end with superior noise performance, which is enabled by standalone enzymatic biofuel cells operating for more than 30 min on active power without replenishment. Two biofuel cells are stacked to realize 0.5V output using commercially available glucose oxidase and the enzyme stability is improved via multipoint crosslinks by glutaraldehyde. To mitigate the effects of noisy and temperature-sensitive pseudo-resistors, a switched-resistor biasing scheme is applied to the input amplifier with the measured input-referred noise of $0.31~\mu V_{\mathrm{ RMS}}$ only. The proposed hybrid power scheme uses $1.6~\mu \text{W}$ from the battery with $1.9~\mu \text{W}$ provided by the biofuel cells. The entire analog front-end including a cascaded dual-supply amplifier with switched-capacitor SAR ADC and single-opamp relaxation oscillator occupies 1.12 mm2. Measured results show on-chip gain and noise variations across temperature of only 1.1 dB and 19.2 nV/ $\sqrt {\mathrm {Hz}}$ , respectively, with noise (power) efficient factor of 1.46 (1.63).

This paper presents an analog front end for measuring the triboelectric current flow between the triboelectric current sensor attached to the magnetic recording head and the media in a hard-disk-drive (HDD) system. The magnitude of the triboelectric current serves as a measure of the proximity between the head and the media and can be optimized for better performance in the next generation HDDs. The analog front end employs a novel current-divert circuit to create two separate signal paths with high and low gain that together provide a linear measure of the triboelectric current over a large dynamic range. A 42.6- $\text{M}\Omega $ dc-coupled, low leakage transimpedance amplifier is designed for the high gain path. It employs an area-efficient, floating, gate-voltage controlled MOS resistor with a novel open-loop temperature compensation scheme. A gain variation of

An analog front end suitable for powerline communication HomePlug AV2 is firstly presented. Targeting different input power level, an attenuation-programmable gain amplifier (AT-PGA) and a low- noise amplifier are adopted as the input stage of receiver, respectively, followed by a fourth-order low-pass filter and a PGA with a build-in feedback control to improve linearity and stay constant bandwidth. A line driver with programmability in transmitter is designed to synthesize output impedance for maximizing the power density transmission ratio in power lines characterized by an impedance of $50~\Omega $ . The analog front end is realized in 0.18- $\mu \text{m}$ 3.3-V CMOS technology with power consumption of 160 mW (receiver) and 350 mW (transmitter) that occupies a 5.75-mm $^{2}$ die area (dual channel). The receiver exhibits a bandwidth of 100 MHz and a gain range from −26.2 to 21 dB, with a minimum noise figure of 20.2 dB at maximum gain 21 dB and maximum IIP3 of 36.1 dBm at minimum gain −26.2 dB. The transmitter achieves 47-dB low-band multi-tone power ratios (MTPR) and 9.6-dB high-band MTPR.

This paper demonstrates an input impedance boosting method that was developed for long-term monitoring of electroencephalography signals. An instrumentation amplifier was designed with a negative capacitance generation feedback (NCGFB) technique to cancel the adverse effects of input capacitances from electrode cables and printed circuit boards. The NCGFB boosts the measured impedance from below 40 M $\Omega $ to above 500 M $\Omega $ at 50 Hz when the equivalent capacitance at the inputs is up to 150 pF. The prototype chip includes an automatic calibration system to adaptively enhance the input impedance through on-chip test signal generation, measurement, and the automatic digital control of the NCGFB. Consisting of an instrumentation amplifier, a low-pass notch filter, and a variable gain amplifier in 130-nm CMOS technology, the signal path has a combined gain range of 66–93 dB with a total power consumption of 42 $\mu$ W. The front-end bandwidth covers 0.5–48 Hz, and its integrated input-referred noise over the bandwidth is 3.75 $\mu$ Vrms. The measured third-order harmonic distortion component is at least 57 dB below the fundamental signal level. A common-mode rejection ratio of 77.6 dB and a power supply rejection ratio of 74 dB were measured at 10 Hz. When activated, the auxiliary test signal generation and calibration circuits consume a power of 542 $\mu$ W.

With the Internet of Things (IoT) paradigm promising to deploy trillions of sensors, the search is on for effective means to efficiently derive useful information from the flood of sensor data through efficient hardware preprocessing. Of particular interest are computational paradigms that get their inspiration from biological sensory systems that seamlessly extract relevant information through highly efficient analog signal processing. Functions, such as feature extraction, learning, or recognition, could especially benefit from bio-inspired architectures. As an example in the case, this paper presents a bio-inspired analog gas sensing frontend for an artificial olfactory system. The analog front end implements a novel trainable feature extraction algorithm for metal-oxide gas sensor arrays. The algorithm extracts one composite feature of all analytes by performing the gradient decent algorithm during training and transforms the sensor responses into concentration-invariant spike patterns. An integrated circuit realization of the algorithm, implemented in a 65-nm CMOS technology, supports six-input channels, uses subthreshold analog circuits, and consumes 519-nW/channel in the training mode, and 463-nW/channel in the recognition mode.

A high sensitivity analog front-end is presented for semi-passive HF RFID tag for implantable devices. The design is compatible with the ISO/IEC 14443 Type-A. A rectifier with high power conversion efficiency is presented to provide stable rectified voltage. Novel tag system architecture with wake-up circuit is proposed to improve the sensitivity. Other Key circuits are studied and designed to make the system work effectively. Simulation results show that the AFE has realized much longer recognition distance than passive tags. Its sensitivity is $-$ 5.7 dBm and can work properly when the magnetic field is 0.3A/m. The AFE was fabricated with HHNEC 0.13 $\mu{\rm m}$ 1P4M CMOS technology with an area of $416\ \mu{\rm m}\times 472\ \mu{\rm m}$ . The AFE is also measured with FPGA based digital baseband. Measurement results show that the proposed AFE can support the 100% ASK demodulation and a modulation depth of 16.4%. The AFE can also accommodate a data rates from 106 Kbps to 848 Kbps are supported. Its power consumption is as low as 129.6 $\mu{\rm W}$ . This chip meets the demands of a semi-passive HF RFID tag and has great potential for implantable devices.

Low energy consumption and wide operating temperature range of capacitors made them common in sensor designs, e.g., MEMS accelerometers, and hence increased the popularity of capacitive readout circuits. Their main challenges, in either discrete or integrated implementations, are sensitivity, noise, energy consumption, and parasitic components at the analog front end. Compared to conventional “frequency-shift monitoring” which is one of the most accurate and common methods for capacitance measurements, weakly-coupled resonators (well-known in mechanical systems) can offer up to three orders of magnitude increase in sensitivity. Therefore, this concept has been recently applied to the design of micromechanical sensors, e.g., for sensitive mass sensing. This paper applies, for the first time in the electrical domain, the concept of monitoring the eigenstates variations in weakly-coupled resonators as a generic readout circuit technique for measuring very small capacitance changes. The outstanding sensitivity of this method is verified analytically and demonstrated using both extensive circuit simulations and experimental measurements.

A fully integrated 2-MHz Gaussian frequency-shift keying (GFSK) analog front end for low-IF receivers is presented. The analog GFSK demodulation uses a Bessel-based quadrature discriminator and a differentiator-based data decision circuit, eliminating the need for analog-digital converters while enabling high sensitivity and large frequency offset tolerance. The analog front end consists of a fifth-order Butterworth low-pass prefilter, a seven-stage limiter, a quadrature discriminator with a fourth-order Bessel phase-shift network, a fourth-order Butterworth low-pass postfilter, and a differentiator-based data decision circuit. The prefilter, Bessel phase shifter, postfilter, and differentiator are built using identical Gm-C cells and tuned across process variations with a single master-slave phase-locked loop. The GFSK analog front end is implemented in a 1.8-V 0.18-mum CMOS process, recovering 1-Mb/s input data from a 2-MHz GFSK signal with maximum frequency deviation of plusmn160-kHz, frequency offset tolerance from - 38% to +47%, and input sensitivity of -53 dBm and consuming 7 mA of current.

A new digital programmable CMOS analog front-end (AFE) IC for measuring electroencephalograph or electrocardiogram signals in a portable instrumentation design approach is presented. This includes a new high-performance rail-to-rail instrumentation amplifier (IA) dedicated to the low-power AFE IC. The measurement results have shown that the proposed biomedical AFE IC, with a die size of 4.81 mm/sup 2/, achieves a maximum stable ac gain of 10 000 V/V, input-referred noise of 0.86 /spl mu/ V/sub rms/ (0.3 Hz-150 Hz), common-mode rejection ratio of at least 115 dB (0-1 kHz), input-referred dc offset of less than 60 /spl mu/V, input common mode range from -1.5 V to 1.3 V, and current drain of 485 /spl mu/A (excluding the power dissipation of external clock oscillator) at a /spl plusmn/1.5-V supply using a standard 0.5-/spl mu/m CMOS process technology.