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This paper presents a digitally programmable bi-directional 7-bit passive phase shifter in a 65 nm CMOS technology. The core of this passive vector-synthesized phase shifter is a hybrid quadrature generator (HQG), an interstage matching network, and a passive vector modulator (PVM). This work proposes a high coupling-factor-based quadrature generator design methodology and demonstrates it with a compact vertical transformer. The interstage matching network between HQG and PVM is proposed to release the bandwidth bottleneck and achieve a 34% fractional frequency bandwidth. Two 6-bit X-type attenuators in the I and Q path form a high-resolution 12-bit controlling word. In 32–40 GHz, this 7-bit 360° phase shifter achieves a measured 2.8° step with 0.45-1.6° RMS phase error and 0.2-0.36 dB RMS magnitude error. With the broadband technique, its 3-dB bandwidth reaches 30.2-42.7 GHz with a 2.8° RMS phase error. Its in-band 1-dB compression point is 10.2 dBm. With the proposed compact HQG and PVM, this mm-wave passive phase shifter only occupies $220\times 630\,\,\mu \text{m}^{2}$ and has no power consumption. [ABSTRACT FROM AUTHOR]

This paper presents a monolithically integrated E-band amplifier multiplier chain (AMC) developed in 130 nm SiGe BiCMOS process. This E-band AMC is composed of a 25 GHz 1:1 power divider, two 25 GHz driver amplifiers (DA1,2), a 75 GHz passive frequency tripler, and a 75 GHz power amplifier (PA). By applying a bypass tuning capacitor based power enhancing technique in the single-ended DA and PA, the output power and power-added-efficiency (PAE) of the AMC have been effectively improved. Benefiting from the proposed passive tripler core with second harmonic suppression function, and the impedance matching network with frequency selection characteristics, the AMC presents better harmonic suppression performance compared with the conventional topology. The bias circuits with temperature compensation are applied to the DA and PA to ensure the performance of the AMC when the temperature changes. The AMC has a measured output power exceeding 0 dBm in the entire E-band frequency range with a peak output power of 10.9 dBm at 77 GHz, and exhibits a record PAE of 8.25 %. Within the 3 dB operating frequency range from 69 to 87 GHz, the rejection of fundamental and second harmonics are better than 33.5 dB. The AMC can work properly between −40°C and 125 °C with the proposed temperature compensation bias circuits. [ABSTRACT FROM AUTHOR]

We propose a framework to analyze mm-wave baluns directly from physical parameters by adding a dimension of Machine Learning (ML) to existing electromagnetic (EM) methods. From a generalized physical model of mm-wave baluns, we train physical-electrical Machine Learning models that both accurately and quickly compute the electrical parameters of mm-wave baluns from physical parameters, reducing the need for full-wave simulations and advancing several aspects of mm-wave designs. One of the advancements is a fully automated design process that accurately generates full EM designs of mm-wave baluns when given an electrical specification and a metal option. The automated technique only takes several seconds to complete, compared to hours-weeks of the current trial-and-error methods, and notably the approach can optimize mm-wave baluns directly for the lowest metal loss. Another advancement is the theoretical interpretation of several high-level and abstract questions concerning mm-wave designs, in which we quantify the optimum transistor sizes for the last stage of a class-AB differential power amplifier on an on-chip process and derive the rule of thumb describing the inverse relationship between the optimum device sizes and mm-wave frequencies. [ABSTRACT FROM AUTHOR]

MOS N-path mixer-first receivers are capable of providing instantly-reconfigurable RF impedance and bandwidth while achieving moderate noise figure (NF) and high linearity, but their frequency tuning range is limited by both LO (local oscillator) generation and the RF port input capacitance. State-of-the-art mm-wave MOS N-path receivers often compromise performance to cover the mm-wave range, but this paper presents the theory and design considerations for a new topology of N-path mixer which makes use of high fT HBTs and breaks this trade-off between performance and tuning range. Here, we borrow from a previously derived LTI model for MOS-based N-path mixers to derive an analogous model for the HBT-based counterpart which provides a meaningful comparison between the performance of the two topologies. We show that the HBT-based implementation is capable of operation beyond the frequency limits of MOS-based implementations while maintaining comparable NF and linearity without consuming exorbitant power. Measurements done on a proof-of-concept chip in GlobalFoundries BiCMOS8HP are consistent with our models and simulations. By organizing process parameters and user-selected design variables into dimensionless ratios, we provide expressions for key performance metrics which enable the designer to make informed decisions about trade-offs and optimizations for both LO generation and the mixer core. [ABSTRACT FROM AUTHOR]

This paper presents a 60 GHz highly efficient singlestage differential stacked Class-AB power amplifier (PA) with second harmonic control (HC) for short range applications using mm-wave radar. The circuit is realized in a 45nm partially depleted sillicon-on-insulator (PD-SOI) CMOS technology. Measurement results show that the power amplifier achieves a saturated output power (Psat) of 16.4dBm with a competitive maximum power-added efficiency (PAEmax) of 32% at 60 GHz. The output-referred 1-dB compression point (OP1dB) is 9.5 dBm. Furthermore, the circuit draws 40mA from a single 1.8V supply and the chip core size is 0.36mm $\times\,\,0.35$ mm. [ABSTRACT FROM AUTHOR]

In this paper, we present a mixer-first receiver front-end suitable for millimeter wave (mm-wave) applications. The proposed architecture includes a modified single-balanced mixer core with an on-chip balun in order to provide a differential output from an injected single-ended local oscillator signal. The mm-wave active balun incorporates a cascode cross-coupled structure to achieve a high voltage gain with low amplitude and phase imbalance. The inter-stage inductors are utilized to increase the mixer conversion gain (CG). Moreover, by manipulating the transistor body effect in the transconductance stage, the CG and noise figure of the mixer are further improved. The mixer also achieves a high input return loss which makes it suitable for the mixer-first receivers. As a proof-of-concept, a 53–67 GHz mixer with a center intermediate-frequency of 20 GHz is designed and implemented in a 65-nm CMOS process. The mixer achieves a measured peak conversion gain of 12.1 dB and a 1-dB compression point of −5 dBm. Furthermore, the fabricated mixer achieves a minimum double-sideband (DSB) noise figure of 6.5 dB over its bandwidth. The whole chip consumes 11.5 mW from a 1-V supply and excluding the pads occupies 0.27 mm2 of silicon area. [ABSTRACT FROM AUTHOR]

Millimeter-wave (mm-Wave) communication, operating from 30- to 300-GHz bands with wider available spectrum, has now emerged as a promising solution for future wireless systems. To reduce the hardware complexity of mm-Wave transceivers, beam-selection techniques combined with beamspace multiple-input multiple-output (MIMO) communications have been proposed in the literature. In such a system, beam selection is performed to exploit the near-sparse nature in the mm-Wave channel and, hence, is crucial to the system performance. This paper presents the world’s first digital signal processing (DSP) architecture design for beam selection operation in an mm-Wave multi-user MIMO system. A computationally efficient beam-selection algorithm is first presented. Based on the proposed algorithm, a hardware-scalable beam selection processor is implemented using coordinate rotation digital computers arithmetic. To establish the validity of the concept, the proposed processor is implemented in a 40-nm CMOS technology, integrating 360k logic gates in an area of 0.5625 mm2, while dissipating 44 mW at 266 MHz in an MU-MIMO system with 16 beams and 8 users. [ABSTRACT FROM AUTHOR]

This paper analyzes and compares two popular methods to widen the modulation bandwidth of a phase-locked loop, i.e., the pre-emphasis and the two-point injection technique. The analysis reveals that both architectures have the same sensitivity to gain errors and nonlinearity in the loop, though, compared with the pre-emphasis, the two-point injection scheme features less sources of error and does not require a phase detector with wide range and tight linearity requirements. The verification of the analysis as well as the comparison of the two modulation techniques is carried out on an accurate time-domain model of a 60-GHz digital phase-locked loop, taken as a case study and used to generate wideband chirp signals for a radar system. [ABSTRACT FROM AUTHOR]

Impedance transformation is one of the central concepts in high-frequency circuits and systems and is used ubiquitously for optimal power matching, noise matching, and high-efficiency power delivery to the antenna by power amplifiers. The matching network can be generally expressed as a path on the Smith chart and given the load and source impedances, there are theoretically infinite ways to achieve the transformation. When losses are included, each path will encounter a different loss, and currently, no comprehensive theory exist for finding the most optimal matching network. Furthermore, the networks will also provide different bandwidths of operation. Due to the matching network losses, it is often not optimal to force conjugate matching for maximizing end-to-end power transfer efficiency. In this paper, we provide a method toward finding 1) the globally most efficient path between two arbitrary impedances with lossy passives; 2) given the source and the load impedances, the optimal (typically non-conjugate) impedance to match and the highest efficiency path to reach the impedance; and 3) upper bounds on achievable efficiencies under the various scenarios. This paper also proposes ways to combine this method with nonlinear load-pull simulations for optimal combiner and matching network for integrated power amplifiers. This analysis creates interesting ways to maximize efficiency and bandwidths simultaneously and the paper also discusses this joint optimization. To the best of our knowledge, this is the first comprehensive analysis of globally optimal impedance transformation networks between arbitrary impedances with lossy passives. [ABSTRACT FROM PUBLISHER]

Several transformer-based techniques are proposed to enhance the frequency tuning range of mm-wave voltage-controlled oscillators (VCOs) and the frequency locking range of injection-locked frequency dividers (ILFDs). Firstly, a switched-transformer VCO (ST-VCO) based on dual-band topology is proposed to increase the frequency tuning range. Secondly, transformer-distribution ILFDs (TD-ILFDs) are demonstrated to achieve much improved frequency locking range with compact chip area and low power consumption. Thirdly, the injection-saturation problem of ILFDs is identified, analyzed, and solved in this work. A VCO and three different TD-ILFDs are designed and fabricated in a 65 nm CMOS process. The proposed ST-VCO measures wide tuning range of 22.3% from 62.1 GHz to 78.3 GHz with phase noise of −112 dBc/Hz at 10 MHz offset while consuming 7.7 mW, corresponding to FoM and FoMT of −180.4 dBc/Hz and −187.4 dBc/Hz, respectively. The proposed 60-GHz TD-ILFDs measure locking range of 19.6 GHz (29.6%), 19.8 GHz (29.2%), and 3.8 GHz (6.1%) while consuming 1.44 mW, 1.44 mW, and 0.44 mW. [ABSTRACT FROM AUTHOR]

The performance characteristics of transmission lines, silicon integrated waveguides, tunable LC resonators and passive combiners/splitters and baluns are described in this paper. It is shown that Q-factor for an on-chip LC tank peaks between 20 and 40 GHz in a 65 nm RF-CMOS technology; well below the bands proposed for many mm-wave applications. Simulations also predict that the Q-factor of differential CPW transmission lines on-chip can exceed 20 at 60 GHz in RF-CMOS when a floating shield is applied, outperforming unshielded variants employing more advanced metal stacks. A PA circuit demonstrator for advanced on-chip passive power combiners, splitters and baluns realizes peak-PAE of 18% and Psat better than 20 dBm into a 50∼\Omega load at 62 GHz. An outlook to the enablement of digitally intensive mm-wave ICs and low-loss passive interconnections (0.15 dB/mm measured loss at 100 GHz) concludes the paper. [ABSTRACT FROM AUTHOR]