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Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an FPGA establishing obstacle avoidance task. We demonstrate the proposed methodology on a spiking neural network implemented on Xilinx Artix-7 FPGA. The system is able to maintain stable firing (tolerance ±10%) with a loss of up to 75% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with a tuning circuit (repair unit) which consumes only three slices/neuron for implementing a threshold voltage-based homeostatic fault-tolerant unit. The overall architecture has a minimal impact on power consumption and, therefore, supports scalable implementations. This paper opens a novel way of implementing the behavior of natural fault tolerant system in hardware establishing homeostatic self-repair behavior. [ABSTRACT FROM PUBLISHER]

This paper proposes a fractional-N digital phase locked loop (DPLL) architecture with calibration-free multi-phase injection-locked time-to-digital converter (TDC) and gradient-based adaptive single-tone spur cancellation scheme. By using the injection-locked ring oscillator, the TDC quantization step is automatically tracked with the period of the digitally controlled oscillator (DCO) over PVT, and hence is free of calibration. The multi-phase TDC further achieves a fine resolution of 7 to 12 ps, depending on the DPLL's operating frequency. The proposed single-tone spur cancellation scheme achieves more than 40 dB spur suppression. The proof-of-concept DPLL prototype is implemented in 65 nm CMOS technology and synthesizes frequencies from 2.7 to 4.8 GHz with a 1V supply, consuming 21.2 mW. The measured in-band phase noise is −92 dBc/Hz at 40 kHz offset, the far out phase noise is −130 dBc/Hz at 3 MHz offset, with a reference spur of −86.5 dBc. [ABSTRACT FROM PUBLISHER]

A delta-sigma (\Delta\Sigma) phase locked loop (PLL) transmitter with an efficient modulation bandwidth calibration technique is proposed in this paper. With the proposed technique, the digital-analog mismatch between digital pre-emphasis filter and PLL is calibrated. The loop filter RC variation is tracked in the first place, and then the variation of the loop gain is calibrated by sensing the magnitude differences of the modulator between DC and ten times of the loop bandwidth. The proposed transmitter has been implemented in 0.18-\mum CMOS technology for GSM/GPRS application. Measurement results show that the maximum RMS phase error of the proposed transmitter is 0.8^\circ. In addition, the measured calibration accuracies for RC and loop gain variations are 0.5% and 0.8%, respectively. By reusing the PLL locking time, 18-\mus calibration time is achieved. Moreover, most parts of the calibration circuitries can be shared with the receiver chain, reducing the circuit complexity overhead. [ABSTRACT FROM AUTHOR]

This paper presents a loop gain optimization technique for integer-N digital phase-locked loops with a time-to-digital converter. Due to noise filtering properties, a phase-locked loop has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the loop gain optimization technique, the digital phase-locked loops can automatically attain this loop gain in background to minimize the jitter. Theoretical analysis is presented. The stability issue and the impact of loop latency are also discussed. Finally, the analysis is compared to behavioral simulations with good agreement. [ABSTRACT FROM AUTHOR]

An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-\mum CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 mm^2 consumes 12 mA and its measured jitter is 4 psrms at 2.4 GHz. [ABSTRACT FROM PUBLISHER]

This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented. [ABSTRACT FROM AUTHOR]

All-digital phase-locked loops (ADPLL) are inherently multirate systems with time-varying behavior. In support of this statement linear time-variant (LTV) models of ADPLL are presented that capture spectral aliasing effects that are not captured by linear time-invariant (LTI) models. It is analytically shown that the latter are subset of the former. The high-speed ΣΔ modulator that improves the frequency resolution of the digitally-controlled oscillator (DCO) is included, too. It realizes fractional resampling and interpolation of the tuning data of the DCO. The noise transfer from all three operating clock domains of the ADPLL (reference, ΣΔ, and DCO) to its output phase is accurately predicted and design metrics are derived with regard to its folded close-in and far-out phase noise performance. The analytical results are validated via simulations using measured event-driven modeling techniques for a CMOS RF ADPLL. [ABSTRACT FROM PUBLISHER]

This paper presents an all-digital phase-locked loop (ADPLL) that features separate use of integer and fractional parts for the phase digitization in the feedback path. This separation simplifies the circuit implementation allowing reduced power consumption and silicon area. The proposed arrangement frees the ADPLL from potential metastability hazard during fine-tuning operation. Furthermore, it eliminates spurious tones associated with frequency reference retiming. In addition, the ADPLL employs an original frequency calibration technique that allows an extremely fine calibration resolution with minimized calibration time. Theoretical analysis is provided for both the architectural modification and frequency calibration technique. The ADPLL has been implemented in a 65-nm CMOS. Its simulation and measurement results are presented. [ABSTRACT FROM PUBLISHER]

In this work, a frequency-based model is presented to examine limit cycle and spurious behavior in a bang-bang all-digital phase locked loop (BB-ADPLL). The proposed model considers different type of nonlinearities such as quantization effects of the digital controlled oscillator (DCO), quantization effects of the bang-bang phase detector (BB-PD) in noiseless BB-ADPLLs by a proposed novel discrete-time model. In essence, the traditional phase-locked model is transformed into a frequency-locked topology equivalent to a sigma delta modulator (SDM) with a dc-input which represents frequency deviation in phase locked state. The frequency deviation must be introduced and placed correctly within the proposed model to enable the accurate prediction of limit cycles. Thanks to the SDM-like topology, traditional techniques used in the SDM nonlinear analysis such as the discrete describing function (DDF) and number theory can be applied to predict limit cycles in first and second-order BB-ADPLLs. The inherent DCO and reference phase noise can also be easily integrated into the proposed model to accurately predict their effect on the stability of the limit cycle. The results obtained from the proposed model show good agreement with time-domain simulations. [ABSTRACT FROM PUBLISHER]

This paper analyses the stability of the synchronized state in Cartesian networks of identical all-digital phase-locked loops (ADPLLs) for clock distribution applications. Such networks consist in Cartesian grids of digitally-controlled oscillator nodes, where each node communicates only with its nearest neighbors. Under certain conditions, we show that the whole network may synchronize both in phase and frequency. A key aspect of this study lies in the fact that, in the absence of an absolute reference clock, the loop-filter in each ADPLL is operated on the irregular rising edges of the local oscillator and consequently, does not use the same operands depending on whether the local clock is leading or lagging. Under simple assumptions, these networks of so-called "self-sampled" all-digital phase-locked-loops (SS-ADPLLs) can be described as piecewise-linear systems, the stability of which is notoriously difficult to establish. The main contribution of this paper is a simple design rule that must be met by the coefficients of each loop-filter in order to achieve synchronization in a Cartesian network of arbitrary size. Transient simulations indicate that this necessary synchronization condition may also be sufficient for a specific (but important) class of SS-ADPLLs. A synthesis of the different approaches that have been conducted in the study of the synchronization of SS-ADPLLs is also done. [ABSTRACT FROM PUBLISHER]