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This paper presents a compact and low-power time-domain CMOS temperature sensor intended for Internet of Things. To eliminate the off-chip reference clock that is commonly needed for time-domain CMOS temperature sensors, a precise on-chip reference clock is designed to measure the temperature-dependent delay generated by an inverter chain with even stages. In the reference clock circuit, a relaxation oscillator showing discharging phases with negative temperature coefficient (TC) is designed, which are compensated by 2 identical inverter-chains with positive-TC delay, resulting in a reference clock with nearly temperature-independent pulse width and period. In addition, a $2^{{\text {nd}}}$ -order hybrid time-voltage delta-sigma ($\Delta \Sigma $) modulator with feedforward path is proposed to quantize the temperature-dependent delay of the main inverter chain, achieving 100-mK resolution only in about 25-ms conversion time. Fabricated in 0.18- $\mu \text{m}$ CMOS, measurement results show that the best (worst)-case temperature accuracy of the clock’s reference time is ±0.015% (±0.055%) and the temperature sensor achieves a maximum inaccuracy of +0.66/−0.73 °C from −20 °C to −80 °C. The prototype occupies 0.45-mm2 chip area and consumes 1.99- $\mu \text{W}$ from a 1.8-V supply at room temperature. [ABSTRACT FROM AUTHOR]

This article presents an $8\times $ -oversampling successive approximation register (SAR) analog-to-digital converter (ADC) with configurable center frequency of noise shaping (NS), which permits the signal passband being configured to any one of the 8 equally divided sub-bands in the first Nyquist band. The configurable noise shaping is realized by an error-feedback (EF) structure with an adjustable 2-tap switched-capacitor (SC) FIR filter. Taking advantage of the sub-bands’ symmetry, the selection of the 8 sub-bands are determined by only a 2-bit controlled variable capacitor in the FIR filter in addition to one bit indicating which half-band the target sub-band is in. As a result, the configuration circuit is area efficient and introduces very little parasitic into the critical EF path. A 2-stage clock-controlled amplifier (CAMP) is proposed for the EF path, which can ensure gain and speed simultaneously through allocating reasonable currents into the gain stage and the driving stage separately. Implemented in 65-nm CMOS process, measurement results under a sampling rate of 10 MSPS show that the prototype achieves signal-to-noise-and-distortion (SNDR) of 71.9~74.6 dB in the 8 sub-bands with 625-KHz bandwidth, corresponding to a Scherier FoM of 171.4 -174 dB. The ADC prototype occupies 0.03-mm2 core area and consumes 70- $\mu \text{W}$ average power at 1-V supply voltage. [ABSTRACT FROM AUTHOR]

This paper presents a self-biased subthreshold CMOS voltage reference for low-power and low-voltage applications. To achieve near-zero line sensitivity and high PSRR, a compensation structure utilizing the drain-induced-barrier-lowering (DIBL) effect is proposed to sink a supply dependent current from the output branch of a self-biased CMOS reference, which cancels the bias current’s dependence on the supply voltage due to the DIBL effect. Fabricated in a 0.18- $\mu \text{m}$ CMOS technology, the measurement results demonstrate that the proposed circuit could operate under a minimum supply voltage of 0.34 V and generate a reference voltage of 147 mV, while consuming only 48 pW power. The PSRRs measured at 1 Hz and 10 kHz are −70.6 dB and −50.2 dB, respectively. For 39 measured samples, the mean line sensitivity is 0.019%/V in a supply voltage range from 0.34 to 1.8 V, and the average temperature coefficients before and after trimming are 64.81 and 10.06 ppm/°C in 0 ~ 100 °C temperature range, respectively. The total area of the voltage reference circuit is 0.0332mm2. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18- ${\mu }\text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{\mu }\text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm2. [ABSTRACT FROM AUTHOR]

Hybrid solid state drive based on ReRAM and NAND flash technologies has shown promising performance and energy efficiency. In this application, ReRAM is mainly used as a non-volatile buffer to hold recently accessed data pages or address mapping information. The previous studies on the ReRAM-based buffer mainly focus on performance and efficiency improvement, while reliability issues are not taken into consideration. Nevertheless, according to our quantitative evaluation, the limited endurance and random bit errors pose challenges to ReRAM-based buffer design. For example, without wear leveling, the raw lifetime of ReRAM-based SSD buffer may be as low as 0.02 year for some specific I/O traces. Therefore, we propose two efficient architecture techniques, i.e., multi-bloom-filter-based wear leveling and hybrid error protection, to improve the lifetime and reduce the error protection cost of ReRAM-based buffer, respectively. Simulation results demonstrate that the proposed wear leveling technique can extend the lifetime of ReRAM-based buffer by $34.7\times $ on average. The proposed hybrid error protection scheme can improve the response time by at least 4.2% compared with other error protection schemes. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant bits and skips unnecessary switching without using any auxiliary circuit. It is further verified in this paper that the HSRS switching scheme shows lower nonlinearity compared with the conventional CDAC structure with the same unit capacitor size and matching condition. This additional advantage permits using DAC topologies with lower total capacitance under given linearity requirement. A hybrid CAP-MOS DAC is adopted to reduce the total capacitance of the DAC, which consumes lower static current and chip area than the conventional hybrid capacitive-resistive DAC under the same settling requirement. The prototype 10-bit SAR ADC is implemented in a 0.18- $\mu \text{m}$ CMOS technology, showing an SNDR/SFDR of 56.43 dB/71 dB at 90-kHz input, under a 0.6-V power supply, while consuming $1.01~\mu \text{W}$ at 200 kS/s for a figure of merit of 9.32 fJ/conv.-step. The ADC occupies only a small active area of 0.0675 mm2. [ABSTRACT FROM AUTHOR]