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This paper presents a K/Ka-band voltage biased differential LC-VCO in 22nm FD-SOI achieving a 1/f3 corner below 18 kHz and a figure-of-merit (FOM) at 1 MHz offset frequency of 188~190 dBc/Hz over the tuning range. Thanks to the flicker noise filtering technique, flicker noise upconversion can be suppressed significantly without degrading the phase noise (PN) in the 1/f2 region. The difference in connection of the switched-capacitor bank (SCB) over the VCO tuning range is taken into account in our analysis of flicker noise filtering. The VCO uses differential source degeneration with a self-coupled inductor that is used for layout compactness and common-mode (CM) resonance manipulation. To obtain a low 1/f3 corner over the tuning range, a common centroid layout technique is used for the SCB. The post-layout simulation shows that the 1/f3 corner is well below 50 kHz over the tuning range in different process corners. The PN@1 MHz and PN@100 kHz are −110.2 dBc/Hz and −89.9 dBc/Hz, respectively, at the center of the tuning range with a power consumption of 8.8 mW. [ABSTRACT FROM AUTHOR]

This paper presents design considerations and methodology for D-band transformer-based Class-AB gain-boosting power amplifiers (PAs) in three advanced silicon technologies: 28 nm bulk CMOS (complementary metal oxide semiconductor), 22 nm FD-SOI (fully-depleted silicon on insulator), and 130 nm SiGe BiCMOS (Silicon-germanium bipolar-CMOS). Firstly, the choice of processes and models together with de-embedding approaches are discussed and described. Then, a general design flow for a transformer-based matching network (TMN) is introduced to accelerate the design of multistage PAs. Further, two gain-boosting topologies are analyzed. The influence of capacitive gain-boosting on PA performance (maximum available power gain Gmax, saturation power Psat, drain efficiency DE and power-added efficiency PAE) is studied for different silicon technologies after properly sizing the PA transistors to reach an optimum load resistance Ropt. The inductive gain-boosting PA is explored and compared with the capacitive gain-boosting one in SiGe BiCMOS to achieve an even higher Psat while maintaining a high Gmax. Finally, A D-band 4-stage capacitive gain-boosting PA is fabricated in a 28 nm bulk CMOS process as a reference to verify the design methodology and simulation results, and its detailed design considerations are described. This prototyped D-band PA achieved the state-of-the-art results: a 22.5 dB Gp, 6.6 % PAE, 8 dBm Psat and 81.1 FoM with only 0.0265 mm2 core area. [ABSTRACT FROM AUTHOR]

This paper presents an analog baseband beamforming topology, which combines phase shifting, signal combination, and biquadratic lowpass filtering in one block. This reduces the number of stages cascaded in a receiver chain, leading to a shorter signal path, thus improving the dynamic range. Flexibility of the proposed solution is illustrated with different possible implementations depending on the top-level chip floorplan. It is shown that the proposed structure does not introduce extra power consumption compared to the conventional approach, while obtaining a higher SNR. A four-antenna-path version of the proposed topology is implemented in 40 nm low-power CMOS as a prototype together with a variable gain block forming a complete analog baseband section for a phased-array receiver. The functionality includes beamforming with a resolution better than 6.8 degrees, fourth-order lowpass filtering with a 1 GHz cutoff frequency, variable gain between 10.6 and 30 dB and automatic DC offset compensation. Output IP3 above 10 dBm and output noise below 4.2 mVrms over the whole gain range yield an SFDR larger than 31.2 dB, which is sufficient for 16-QAM modulation according to IEEE 802.11ad. The circuit consumes between 30 and 42 mW. [ABSTRACT FROM AUTHOR]

Substrate noise is a major obstacle for single-chip integration of mixed-signal systems. To reduce this problem and to assess its evolution with CMOS technology scaling, the different mechanisms that generate substrate noise and their dependencies on different parameters need to be well understood. In this paper, we show that with downscaling of the technology, substrate noise due to supply coupling becomes the dominant coupling mechanism when the chip substrate is directly biased with the digital ground. With Kelvin ground substrate biasing on the other hand, source/drain capacitive coupling becomes the dominant coupling mechanism. Further, we show that with downscaling, the peak value of the supply coupling noise component becomes more dependent on the relative ratio of the switching capacitance to the nonswitching capacitance, which is formed by the circuit decoupling and the nonswitching circuit elements, rather than the Ldi/dt noise. These insights illustrated in a quantitative framework are believed to be very useful for the systematic use of digital low-noise design techniques in future CMOS technologies. [ABSTRACT FROM AUTHOR]

The successful realization of a wireless body area network (WBAN) requires innovative solutions to meet the energy consumption budget of the autonomous sensor nodes. The radio interface is a major challenge, since its power consumption must be reduced below 100 μW (energy scavenging limit). The emerging ultra-wide-band (UWB) technology shows strong advantages in reaching this target. First, most of the complexity of an UWB system is in the receiver, which is a perfect scenario in the WBAN context. Second, the very little hardware complexity of a UWB transmitter offers the potential for low-cost and highly integrated solutions. Finally, in a pulse-based UWB scheme, the transmitter can be duty-cycled at the pulse rate, thereby reducing the baseline power consumption. We present a low-power UWB transmitter that can be fully integrated in standard CMOS technology. Measured performances of a fully integrated pulse generator are provided, showing the potential of UWB for low power and low cost implementations. Finally, using a WBAN channel model, we present a comparison between our UWB solution and state-of-the-art low-power narrow-band implementations. This paper shows that UWB performs better in the short range due to a reduced baseline power consumption. [ABSTRACT FROM AUTHOR]