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In this paper, for the first time, the phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to the three stages of conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved phase noise with increasing stages. The primary distinction between these two designs (SDRO and three-stage CROs) is the inherent skew offset between the PMOS/NMOS gates caused by the unique connection. This skew offset is the fundamental cause of delay cell noise suppression; the SDROs have loosely coupled oscillators that run concurrently, forming multiple 3-stages of separately driven Ring Oscillators. As a result, a shaping function is derived in terms of skew offset, and simulating these with varying skew offset results in suppressing behavior. Additionally, we derived phase noise for a skew-based design and validated it in PDKs of 180nm and 65 nm. We plotted the thermal (flicker) noise contribution and found that increasing the number of stages leads to an approximately 1-2 dB reduction in phase noise while maintaining the same NMOS/PMOS size ratio. Finally, a 2-3 dB reduction in phase noise is achieved in MSSROs by incorporating the shaping function into phase noise equations. [ABSTRACT FROM AUTHOR]

In this work, a stable and accurate model order reduction method for large-scale partial element equivalent circuit (PEEC) models with many delays is proposed. The method reduces the dimension of the original model by interpolating the original transfer function. The interpolation points are iteratively selected using a greedy algorithm. An efficient error estimator for the reduced transfer function makes the greedy algorithm very successful in both, properly selecting the interpolation points and tightly measuring the error of the reduced transfer function. The resulting reduced-order model is accurate both in the frequency and in the time domain. Numerical tests have shown that the reduced-order model successfully filters the instability behavior of the original model and exhibits stability over a large time interval. [ABSTRACT FROM AUTHOR]

This paper analyzes the ability to suppress in-band noise power of a regenerative amplifier (RA) operating in the nonlinear regime in response to a continuous wave (CW) input tone. As opposed to the linear regime where a CW tone and the noise floor experience the same transfer function, it is shown that the non-linear saturation behavior of an RA yields different transfer characteristics between a CW tone and noise, ultimately leading to an improvement in the output carrier-to-noise ratio (CNR). This is all thanks to the high gain, narrow bandwidth, and the compressive third-order nonlinearity of the RA. This non-linear noise suppression is first analyzed mathematically using single tones in the frequency domain to represent the signal and the noise. Then, simulation of an RA circuit model is shown to be in excellent agreement with the analytical results. Lastly, a discrete RA has been implemented to experimentally verify the noise-suppression phenomenon. The measurement results clearly demonstrate noise suppression and show an output CNR improvement of up to 3 dB. Potential applications of the RA with noise suppression are also discussed. [ABSTRACT FROM AUTHOR]

This paper presents a compact single-ended inverter-based transceiver with swing improvement for short-reach links. The low output impedance of the transmitter enlarges the output swing and the eye size to overcome large single-ended noise while relaxed impedance matching provides good signal integrity. For good area efficiency, the proposed transmitter utilizes an inverter driver which is much smaller than the conventional source-series termination driver and thus occupies only $42.5 ~\mu \text{m}^{2}$. By taking the advantage of a large signal swing, the receiver consists of only four slicers and latches to minimize area overhead and to simplify the design. The transceiver was fabricated in 28-nm CMOS technology and tested at supply voltage of 1.13 V. The transmitter achieved a large output swing of 850 mV, which is 50.4 % larger than the conventional source-series termination transmitter. At the far-end of a channel consisting of a 1 m SMA cable and a 17 mm printed circuit board trace, the transmitter achieved eye openings of 440 mV and 234 mV at 16 Gb/s (−2.7 dB) and 20 Gb/s (−8 dB), respectively. Even with a large switching noise of 100 mV, the in-situ eye at the receiver was measured 114 mV with 7.4 dB loss. [ABSTRACT FROM AUTHOR]

The continuous-time pipeline (CTP) analog-to-digital converter is an emerging technique that combines the benefits of pipelining with continuous-time operation. Prior-art multistage CTP ADCs have employed stages with identical transfer functions. This work proposes the use of non-identical (and appropriately chosen) transfer functions for different stages of the pipeline. We investigate the benefits of this approach when compared with conventional techniques. We also demonstrate that the sharp filtering offered by a multi-stage CTP can be exploited to implicitly decimate the output sequence of the converter. This is accomplished by clocking the back-end ADC at a lower rate, and by appropriately modifying the digital reconstruction filters. The implicit-decimation theory is supported with measurement results from a three-stage CTP designed in a 65nm CMOS process. The converter achieves 70.4dB SNDR in a 100MHz bandwidth with its front-end operating at $f_{s}\,{=}\,800$ MHz, while the back-end samples at $f_{s}/2$. [ABSTRACT FROM AUTHOR]

This paper presents a rigorous transfer function analysis of the power supply rejection ratio (PSRR) of low-dropout (LDO) regulators and the LDO with the feed-forward ripple cancellation (FFRC) scheme. Four main noise sources of conventional LDOs are first clarified. An efficient and accurate model is proposed to facilitate the analysis, and the transfer function, along with the poles and zeros, is derived based on the simplified model. Software simulation results and numerical plots are both demonstrated and compared to verify the analytical results, with respect to two specific design examples. The widely-used FFRC scheme for PSRR enhancement is also reinvestigated based on the proposed model. With the inclusion of the FFRC circuit, the new transfer function with new poles and zeros is presented. The working principles of the FFRC scheme are illustrated and the optimal FFRC case is clarified. The proposed model and the derived transfer function match well with the simulation results and the measurement results in prior works. The proposed model and the analytical results serve as the theoretical foundation of the design of high-PSRR LDOs. The recommended simulation methodology could be helpful during the circuit design phase. [ABSTRACT FROM AUTHOR]

The objective here is to develop a uniform and comprehensive procedure for symbolic analysis of linear circuits using the Sum of the Tree Products (STP) of the circuit. We achieve this goal in two stages. In the first stage a circuit with active devices, such as VCCSs and I/O ports, is changed to a nullor circuit, i.e., to a circuit with only passive components and nullors. The nullor circuit is also partitioned into two parts, a passive circuit and an all-nullor circuit. It is shown that the magnitude of the STP, i.e., the determinant of the NAM, of the circuit is equal to the STP of the passive portion of the circuit, and the sign (0, 1, or −1) of the STP comes from its all-nullor part. Another significant development in this presentation is the replacement of the regular STP methodology with a rather new Admittance Method (AM). It is shown that by doing this the entire two-graph theory for active circuits as well as the use of 2-tree procedures for I/O ports analysis are eliminated. It is these new developments that substantially simplifies the circuit analysis and makes it quite efficient for symbolic representation of transfer functions. [ABSTRACT FROM AUTHOR]

The analysis of injection-locked clock multipliers (ILCMs) using bang-bang phase detectors (BBPDs) is challenging due to the nonlinear BBPD and the multi-rate injected oscillator. This paper presents an explicit analysis of digital ILCMs using BBPDs and proposed an intuitive approach to optimizing parameters with given noise sources. A time-domain analysis in the single-clock domain is presented to solve the closed-form expression of jitter in the ILCM. The proposed approach exhibits good consistency with simulations, for various design parameters and noise cases. With the predicted input-referred jitter, the equivalent BBPD gain is resolved to derive the frequency-domain noise transfer functions in concise forms. To achieve the desired performance with given specifications, recommended design procedures are summarized based on the proposed analysis and verified by simulations. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical design procedure for a class of 2D filters with a directional characteristic in the frequency plane. The method starts from two types of low-pass prototypes, namely a Gaussian filter and a wide-band filter. The two prototypes and the resulted 2D filters are zero-phase, a very useful property in image processing tasks. The prototypes are parametric and can be scaled along the frequency axis, thus resulting narrower or wider. A 1D to 2D frequency mapping, based on accurate approximations, is derived and applied to each prototype, obtaining the desired directional 2D frequency response with specified selectivity and orientation. The designed filters are adjustable, with a frequency response in factored matrix form depending on specifications. The Gaussian prototype yields very selective directional filters, used in detecting oriented straight lines in images, as show simulation results on several test images. Using oriented wide-band filters, other useful 2D filters result, namely square and parallelogram filters. The designed filters have accurate frequency responses, good directional selectivity and high linearity at relatively low order. An advantage of this analytical approach is that the filter transfer function results in parametric form and allows for easy tunability. [ABSTRACT FROM AUTHOR]

Instability and oscillation issues originating in high-voltage direct current (HVDC) systems comprising modular multilevel converters (MMCs) are gaining increasing interest in the research community. To detect such phenomena in advance, considerable effort has been devoted recently to developing MMC models for small-signal analysis. The derivation of such models is a challenging task due to the topology and complex control structure of MMCs, which results in them having a multi-frequency response. To address this issue, scholars developed methods based on dynamic phasors and harmonic state-space modelling, which, however, require extensive pen-and-paper computations. In this paper, the periodic small-signal analysis (PAC) is adopted to determine numerically several MMCs transfer functions. Such functions can be computed between any electrical circuit node or input/output port, without the need to recast the three-phase average MMC model to derive a linear equivalent one, possibly in the DQ-frame. We show how vector fitting allows converting these functions to equivalent algebraic representations, which can be profitably used to design MMCs and study their stability following some parameter changes. To showcase this feature, we exploit one of these transfer functions to detect DC-side instability in a point-to-point HVDC system. [ABSTRACT FROM AUTHOR]

This paper presents a time-interleaved analog-to-digital converter mismatch calibration, which can be adapted to any interleaving factor and calibrate offset, gain, time skew and bandwidth mismatches. Moreover, the proposed scheme utilizes a non-return-to-zero pilot signal, avoiding the high-resolution requirements of sinusoidal generators. In addition, there are no multiplications in the detection path in contrast with the state-of-the-art approaches. Consequently, the proposed calibration presents the smallest complexity in terms of hardware requirements compared to previous work (to the author’s knowledge). Therefore, the proposed calibration can be made with the smallest area and power consumption. Numerical simulations show an SNDR improvement of 49.52 dB for a 12-bit 4-channel TI-ADC and an SNDR improvement of 29.64 dB for an 8-bit 32-channel TI-ADC when random mismatches are applied. The measurement results show an SNDR improvement of 24.68 dB for a 3.6 GS/s 2-channel TI-ADC experimental board. [ABSTRACT FROM AUTHOR]

The dual-rank configuration is one of the parallelization methods to increase the memory capacity for mobile applications. However, the stub mainly composed of the redistribution layer causes resonance reflections and its reflection interval reaches the bit period, which distorts signal and limits the signal bandwidth. A single-ended duobinary transmitter that utilizes the reflection is presented for dual-rank mobile memory interfaces where reflections dominate. The reflection is included in the transfer function for duobinary modulation, which allows the transmitter to have a wide eye opening and high energy efficiency. Two-tap reverse feed-forward equalization and slew-rate control are used to support the duobinary modulation in combination with the reflection. A prototype chip fabricated in a 65 nm CMOS process has an area of 0.0378 mm2 and consumes 1.24 pJ/bit. It is verified at data rates of 8, 9 and 10 Gb/s/pin where the flight time of the 9 mm stub is 55.6 ps. [ABSTRACT FROM AUTHOR]

The continuous-time pipelined (CTP) ADC is a promising emerging high-speed analog-to-digital conversion technique that achieves anti-alias filtering and analog-to-digital conversion in one step. Driving such a converter is easy, thanks to its resistive input impedance. RC time-constant shifts, which will occur in practice due to a change in ambient temperature, degrade the performance of such converters. The aim of this work is to understand this phenomenon, quantify the resulting SNDR degradation, and thereby derive design tradeoffs. The theory is compared with measurements from a three-stage CTP that targets 70dB SNDR in a 100MHz bandwidth while sampling at 800MS/s. [ABSTRACT FROM AUTHOR]

Recently, an in-memory analog circuit based on crosspoint memristor arrays was reported, which enables solving linear regression problems in one step and can be used to train many other machine learning algorithms. To explore its potential for computing accelerator applications, it is of fundamental importance to improve the computing speed of the circuit, i.e., the circuit response towards correct outputs. In this work, we comprehensively studied the transfer function of this circuit, resulting in a quadratic eigenvalue problem that describes the distribution of poles. The minimal real part of non-zero eigenvalues defines the dominant pole, which in turn dominates the response time. Simulations for multiple linear regression solutions with different datasets evidence that, the computing time does not necessarily increase with problem size. The dominant pole is related to parameters in the circuit, including feedback conductance, and gain bandwidth products of operational amplifiers. By optimizing these parameters synergistically, the dominant pole shifts to higher frequencies and the computing speed is consequently optimized. Our results provide a guideline for design and optimization of in-memory machine learning accelerators with analog memristor arrays. Also, issues including power consumption, impact of noise and variation of sources and memristors are investigated to offer a comprehensive evaluation of the circuit performance. [ABSTRACT FROM AUTHOR]

In this paper a low-power and high-performance 2nd-order complex band-pass filter in trans-impedance amplifier (TIA) configuration is presented. Thanks to the adopted topology for the passive network and active-components exceeds current solutions exhibiting a gain as high as 121.5 dB $_\Omega $ and 1.57 MHz of bandwidth centered around 1.33 MHz. The output noise is only 630 nV/ ${\sqrt {Hz}}$. Furthermore, a new fully-differential class-AB operational trans-conductance amplifier (OTA) provides the required current to drive heavy ADC loads with very fast signals while an improved common-mode feedback circuit enables ultra low current without introducing stability and avoids start-up problems. The filter has been integrated in a 90-nm complementary metal oxide semiconductor (CMOS) technology. Despite the high performance and accuracy of the transfer function the power consumption is only $400~\mu \text{A}$ from a 1.2-V power supply. [ABSTRACT FROM AUTHOR]

The TICER (TIme-Constant Equilibration Reduction) algorithm is a well-known resistor-capacitor (RC) network reduction algorithm. It finds wide applications in integrated circuit post-layout simulation tools. However, the original algorithm is one-dimensional in that each step eliminates one circuit node to obtain an approximately equivalent circuit by connecting additional elements to the neighboring nodes after each elimination. This work extends the TICER algorithm to its high-dimensional version in the sense that each step eliminates a subcircuit as a whole to obtain an approximately equivalent circuit, again by connecting extra elements to the neighboring nodes after each elimination. In practice the high-dimensional TICER (HD-TICER) algorithm finds many advantages over the classical one-dimensional TICER (1D-TICER) algorithm, which is a special case of the HD-TICER algorithm. An elegant mathematical derivation of the HD-TICER algorithm is provided by applying the notion of driving point impedance (DPI). The advantages of the HD-TICER algorithm are demonstrated by application to reductions of some purely resistive networks and RC networks. An approximate time constant estimation method is also provided for selection of a subblock circuit to eliminate. [ABSTRACT FROM AUTHOR]

The presence of nonlinearities in a fractional-N frequency synthesizer leads to the generation of an additional component of noise that appears in the output phase noise spectrum. This nonlinearity-induced noise component manifests itself as spurious tones and an elevated noise floor, also known as folded noise. This paper presents a mathematical analysis of the folded noise generated in fractional-N phase locked loops (PLL) by the interaction between the quantization noise introduced by the divider controller and a nonlinearity. The analysis is performed for different digital $\Delta \Sigma $ modulators (DDSM) and nonlinearities, providing expressions that allow one to predict the folded noise. These are compared with state-of-the-art predictions and simulation results. [ABSTRACT FROM AUTHOR]

When the accumulated zero-mean output of a digital modulator encounters a nonlinear function, nonlinearity-induced spurs can arise in the spectrum of the resulting signal. These spurs occur with both periodic and aperiodic modulator outputs, and can appear in applications such as frequency synthesis at frequencies where filtering approaches are ineffective. The mechanism at the root of these spurs is the nonlinear transformation of the cyclostationary modulator-induced phase noise. An algorithm is presented which determines modulator parameters that guarantee a spur-free spectrum after the application of a memoryless nonlinearity to the accumulated modulator noise. The algorithm takes as its input a sampled representation of the in-loop nonlinearity function, and determines a matrix of probabilities to be applied by the modulator. The algorithm can handle arbitrary nonlinear functions and relies on straightforward, synthesizable operations. Simulations demonstrate the ability of the algorithm to program a modulator such that spur-free operation is obtained for an illustrative selection of nonlinearities. [ABSTRACT FROM AUTHOR]

Active noise control (ANC) requires a controller with a small delay. However, in most ANC applications, this delay is significant due to the typically low sample rate, the anti-aliasing (AA), and reconstruction filters (RC) of the analog to digital (AD) and digital to analog (DA) converters. This delay can be reduced by increasing the sampling frequency at the expense of a significant increase in computational complexity. Sigma-delta AD and DA converters work at high sampling frequencies, but their use in ANC is limited due to the delay of AA and RC filters. This work proposes removing the AA and RC filters of the sigma-delta converters and using the oversampled signals directly in an ANC system. This proposal allows the ANC system to be implemented at a large sample frequency but using signals with fewer bits per sample (word-length). This is the first short-word length implementation of the least mean squares (LMS) algorithm to the authors’ knowledge. Gains of up to 6 times may be achieved in the computational complexity when compared with a long-word length implementation. Theoretical and simulation results validate the current solution. [ABSTRACT FROM AUTHOR]

This paper presents a novel Look-up Table (LUT) calibration technique for static non-linearity compensation in analog-to-digital converters (ADCs) with digital redundancy, such as Successive Approximation Register (SAR), Algorithmic, Sub-ranging or Pipeline ADCs. The method compensates the performance limitations of the conventional LUT approach in presence of comparison noise and/or non-monotonicity. In these circumstances, the input-output transfer function of a redundant ADC becomes significantly multivalued - that is, different output codes can be achieved for the same input level at different time instants. This behavior is motivated because from sample to sample, in a design with redundancy, the processing signal path is not unique, causing that the error under calibration becomes time-dependent, something which is not contemplated in the conventional calibration model. To deal with this effect, this work proposes a digital low-cost post-processing of the standardized Integral-Non-linearity (INL), which resolves multivalued situations using a direct access to the internal redundant codes. The method improvements are validated by realistic SAR and Pipeline ADC case studies at behavioral level, and by experimental data from an 11-bit 60Msps Pipeline ADC implemented in a 130nm CMOS process. These experimental results show that the proposed calibration achieves an improvement of approximately 1.6 effective bits at full-scale input amplitude. [ABSTRACT FROM AUTHOR]

Incremental delta-sigma data converters are useful in applications where one ADC is needed to digitize multiple channels. They can be realized using single- or multi-bit feedback. In both cases, the use of FIR feedback is beneficial in terms of improving the modulator’s linearity, reducing the quantizer’s complexity, and mitigating the effects of clock jitter (in a continuous-time realization). In the incremental mode, however, the maximum stable amplitude of the ADC is severely impacted by FIR feedback. The reasons behind this are examined, and techniques that mitigate this problem are given. Circuit simulations of an example fourth-order single-bit incremental modulator with an eight-tap FIR DAC are given to illustrate the efficacy of the theory. [ABSTRACT FROM AUTHOR]

This work presents a novel amplifier architecture which is the input stage of an analog front end targeting the acquisition of biological signals with low voltage supply (1.2 V), low noise, high Common Mode Rejection Ratio (CMRR) and high current efficiency. A prototype, designed and fabricated in a 130 nm CMOS technology, was characterized by simulations and measurements. Our preamplifier presents one of the lowest noise levels reported up-to-date (over the considered bandwidth) while presenting a very competitive performance in other important features. Results from measurements show a bandwidth from 20 Hz to 11 kHz, a CMRR higher than 70 dB, an equivalent input-referred noise as low as 1.3 μVrms. The Noise Efficiency Factor (NEF) at 2.5 and Power Efficiency Factor (PEF) at 7.5 are remarkable results. [ABSTRACT FROM AUTHOR]

This paper proposes a novel artificial neural network (ANN) based control method for a dc/dc buck converter. The ANN is trained to implement optimal control based on approximate dynamic programming (ADP). Special characteristics of the proposed ANN control include: 1) The inputs to the ANN contain error signals and integrals of the error signals, enabling the ANN to have PI control ability; 2) The ANN receives voltage feedback signals from the dc/dc converter, making the combined system equivalent to a recurrent neural network; 3) The ANN is trained to minimize a cost function over a long time horizon, making the ANN have a stronger predictive control ability than a conventional predictive controller; 4) The ANN is trained offline, preventing the instability of the network caused by weight adjustments of an on-line training algorithm. The ANN performance is evaluated through simulation and hardware experiments and compared with conventional control methods, which shows that the ANN controller has a strong ability to track rapidly changing reference commands, maintain stable output voltage for a variable load, and manage maximum duty-ratio and current constraints properly. [ABSTRACT FROM AUTHOR]

The time-interleaved analog-to-digital converter has shown to be a key component of the latest ultra-wide band systems. Unfortunately, the sub-analog-to-digital converters are prone to parameter deviations caused by process-voltage-temperature, which can affect the output linearity. This article presents a foreground time-interleaved analog-to-digital converter mismatch calibration, which is one of the few available in the literature that can be adapted to any interleaving factor and calibrate overall frequency-dependent mismatches. Moreover, the proposed scheme is highly suited to state-of-the-art transceivers without the need for extra analog expensive circuitry or input signal purity. The foreground signal and correction structure complexity are greatly alleviated due to the developed mismatch detection and genetic algorithm logic. Numerical simulations and measurement results are presented. A commercial 3.6-GS/s time-interleaved analog-to-digital converter was utilized to verify the algorithm performance and experimental issues regarding mixed mismatches are addressed. [ABSTRACT FROM AUTHOR]

This paper analyses the noise performances of coupled phase-locked loops, providing closed-form expressions for the transfer functions of the various noise sources, and presents a novel coupling topology, whose goal is the reduction of both in-band and out-of-band phase-noise. The proposed circuit consists of two, or more, standard loops coupled via an additional phase detector. It will be demonstrated that in this architecture the impact of the main PLL noise sources, the oscillator and the reference buffer, is efficiently traded with the power dissipation without resorting to lossy and area-consuming passive coupling networks. The work then shows how to derive the set of design parameters that grant the desired performance for a given case study. The entire procedure is verified by simulations. [ABSTRACT FROM AUTHOR]

N-path commutated capacitive networks provide a practical solution to implement highly sought on-chip high-Q filtering applications in which the use of lumped inductors is undesirable due to their significant footprints and low Q-factors. Recently, it has been also revealed that N-path networks can also exhibit other interesting functionalities, such as nonreciprocal phase-shifting and ultra-wideband true time delay, providing a path to miniaturization of various reciprocal and nonreciprocal devices. The analytical treatment of these networks, however, remains challenging, because their operation involves frequency mixing produced by the time modulation. In this article, we present a highly accurate frequency-domain approach for the analysis of N-path networks based on perturbation theory. Our method compares favorably to the state-of-the-art polyphase analysis by being much simpler mathematically, yet providing results essentially indistinguishable from numerical simulations, while offering physical insights into the N-path filter operation. We particularize the solution for the high-Q operation regime and obtain simple closed-form analytical expressions for harmonic transfer functions, scattering parameters and baseband impedance. [ABSTRACT FROM AUTHOR]

Analog integer order notch filters (IONF) are practically realised by using two or more capacitors. If the dissipation factor of capacitors (used in the IONF) increases then the overall order of the circuit reduces. Reduction in the order causes attenuation-loss at the notch frequency. Once the order reduces, the loss can only be compensated by reducing the quality factor of the IONF circuit, which is not desirable. This problem can be overcome by using a fractional order notch filter (FONF). The FONF circuit uses fractional order capacitors ($Z=\frac {1}{Cs^\beta }$), which provides an extra degree of design freedom to control the order of the circuit, thereby helping in compensating the attenuation-loss. In this work, a new fractional order notch filter (FONF) has been proposed in which the attenuation-loss, due to change in the order of the system, can be compensated by tuning resistor/s of the proposed circuit. [ABSTRACT FROM AUTHOR]

This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to quantize the most significant bits (MSBs), which are encoded with a proposed residue transformation method to control the residue generation of the first stages in two fine channels. The residue voltages generate on the capacitive digital-to-analog converters (C-DACs) of split fine channels directly without successive approximation processes. Therefore, the conversion rate is increased and the power is reduced. A shuffle mechanism is introduced into split-ADC based digital background calibration to avoid the divergence of the conventional algorithm in the proposed architecture. A high-energy-efficiency dynamic amplifier is also introduced as the residue amplifier. A 14-bit 60-MS/s ADC is prototyped in a 28-nm CMOS process. The digital calibration engine operates under 0.9-V supply, other parts of the ADC core operate under 1.05-V supply. The ADC core consumes 4.26 mW. Measurement results show that the calibration improved the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) dramatically, the calibrated ADC achieves SNDR and SFDR of 66.9 dB and of 91.0 dB respectively, translating to a Schreier FoM of 165.4 dB and a Walden FoM of 39.3 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

In this paper, we study networks of coupled oscillators applied to the distributed synthesis of clock signals for large systems-on-chip. The oscillators are implemented as interconnected all-digital phase-locked loops (ADPLLs), which are asynchronous control systems. We address the issue of modelling, synchronization and stability of both a single ADPLL and interconnected ADPLLs. We prove that the stability domain is universal for large Cartesian networks, and it related to the domain for a single ADPLL. We show that within the stability domain the network synchronises to the reference signal both in frequency and phase. A hardware verification of Cartesian networks is presented, and it is consistent with our theoretical findings. The proposed design may be useful for multiples engineering and physics applications, including clock generation, distributed computations, beamforming, and other applications, where the control over time synchronicity is crucially important for the system performance. [ABSTRACT FROM AUTHOR]

The Modulated Wideband Converter (MWC) is one of the promising sub-Nyquist sampling architectures for sparse wideband signal sensing applications. Its frequency support detection and the reconstruction ability is well-defined through compressed sensing theory. However, the reconstruction performance of the MWC is strictly limited by the non-ideal components in practical implementations. Previous calibration methods exploit sequential single-tone signals to estimate the actual transfer function of the MWC, which is fairly time-consuming. We propose a new calibration method that estimates the actual sensing matrix coefficients of the MWC only with a single measurement based on a pilot multi-tone signal. The feasibility of the proposed calibration method is demonstrated in terms of normalized mean square error (NMSE) and image rejection ratio (IRR) of the reconstructed original signal. [ABSTRACT FROM AUTHOR]

This paper introduces a new class of ring oscillator (RO)-based filters that address linearity and process variance limitation of existing RO-based filters. A highly-linear process-tolerant RO filter topology is achieved by imitating the widely known active-RC topology in the phase domain. We propose utilizing a set of frequency detectors (FDs) and phase detectors (PDs) to extract both the frequency and phase information of an inverter-based RO to synthesize active filters in a way similar to integrator-based active-RC filters, which are synthesized using a set of capacitors and resistors, respectively. A zero compensation technique is proposed to extend the achievable bandwidth of the proposed topology. Also, a delay-locked loop (DLL)-based tuning scheme is introduced to achieve resilience over PVT variations. A prototype 5th-order, 2–22 MHz continuous-time Butterworth filter is presented in 130 nm CMOS technology to demonstrate the proposed topology. The filter consumes 6.2–8.9 mA from a 1 V supply and achieves 26.2 dB in-band IIP3. The filter achieves bandwidth variation less than ±3.5% over a temperature range of −40 °C to 85 °C and supply voltage range of 0.9–1.2 V. [ABSTRACT FROM AUTHOR]

Two methods are presented for implementing a multi-channel ADC using a continuous-time delta-sigma modulator (CTDSM) without resetting its states. The first is adapted from a method used with a discrete-time delta-sigma modulator. It uses a sample-and-hold (S/H) at the Nyquist rate before the modulator and an adaptive equalizer at the Nyquist rate after the modulator for flattening the equivalent frequency response and eliminate memory. The newly proposed $\pi $ -shifted filter, instead of flattening the equivalent discrete-time frequency response, merely ensures that the equivalent frequency response is symmetric about $\omega =\pi /2$. In the time domain, this means that the equivalent impulse response at the Nyquist rate has zero-valued odd samples ensuring no cross-talk between two multiplexed inputs. Compared to the adaptive equalizer used for flattening the frequency response, this filter consumes three times lower power while occupying half the area. A two-channel ADC is demonstrated using both the adaptive equalizer & the $\pi $ -shifted filter. The ADC uses a CTDSM running at 6.144 MHz with an oversampling ratio (OSR) of 64, yielding a per-channel bandwidth of 24 kHz. The prototype in 180nm achieves a peak SNR/SNDR/DR of 91.7 dB/84.9 dB/98 dB and consumes 1.33mW per channel with adaptive equalizer. The SNR/SNDR/DR is 90.5 dB/83.7 dB/97 dB with a power consumption of 0.86mW per channel with the $\pi $ -shifted filter. [ABSTRACT FROM AUTHOR]

Continuous-time $\Delta \Sigma $ modulators used in wireless transceivers need to digitize small desired signals that are accompanied by large out-of-band interferers. In such applications, it is desirable that the CT $\Delta \!\Sigma \text{M}$ have a low-pass signal transfer function whose bandwidth can be specified. Many architectures present themselves as potential candidates to realize such filtering-CT $\Delta \!\Sigma $ Ms. This work investigates these threads and concludes that a CT $\Delta \!\Sigma \text{M}$ with an embedded Rauch filter is a compelling design choice. The theory is supported by measurement results from a filtering-CT $\Delta \!\Sigma \text{M}$ test chip that achieves a peak SNDR of 76.7dB in a 1MHz signal bandwidth. Measurements demonstrate improved power efficiency and out-of-band linearity when compared to prior art. [ABSTRACT FROM AUTHOR]

This paper presents a wide bandwidth inverter-based continuous time sigma delta (CTSD) analog-to-digital converter (ADC) with a latency-free calibration to suppress the nonlinearity originating from the feedback digital-to-analog converter (DAC). The modulator in the ADC uses a fourth-order architecture with 4-bit quantization. To compensate the excess loop delay (ELD), the proportional-integrating element (PI-element) is employed in the loop filter where the problem of no real solution in conventional PI-element compensation method is solved. In addition, the two-stage inverter-based amplifiers are used in the loop filter to improve power efficiency. To suppress nonlinearity of the 4-bit DAC, a background calibration method based on modified quantizer is proposed which would not introduce additional latency thus ensuring stability of the modulator. The CTSD ADC achieves 64.6 dB SNDR and 71.2 dB SFDR over a 75 MHz signal bandwidth before calibration, and the SNDR and the SFDR can be improved to 67.3 dB and 82.3 dB respectively after calibration. The ADC consumes 38 mW from supply voltages of 1.1/1.8 V with an active area of 0.675 mm2 in 40 nm CMOS. [ABSTRACT FROM AUTHOR]

High-resolution, single-loop incremental Delta-Sigma (I- $\Delta \Sigma $) ADCs require large oversampling ratios to sufficiently suppress quantization noise. This limits the bandwidth of most designs to the low-kHz range. To overcome this problem, the presented proof-of-concept design makes use of time interleaving two third-order I- $\Delta \Sigma $ modulators with embedded hardware sharing that helps to enhance the efficiency of the presented modulator. The modulator is fully reconfigurable in a way that both channels can either be operated time interleaved or independent from each other. This is a means of enhancing the flexibility and efficiency of the modulator depending on the application scenario. The presented design was fabricated in a 180nm technology node. [ABSTRACT FROM AUTHOR]

Critical conduction mode (CrCM) active clamp flyback (ACF) converter is regarded as a good candidate for low power adaptor applications. However, the most adopted control strategy of variable-frequency peak current mode (VF-PCM) and discrete zero voltage switch (ZVS) control makes it difficult to get the accurate small signal model. Therefore, by using sampled-data modeling method, this paper proposes an exact small signal model of CrCM ACF converter for the first time. In the modeling process, the influence of discrete-ZVS control is firstly considered. The conduction time of power switch is regarded as the control signal, which is different from constant-frequency converter. The total current close-loop transfer function is simplified by the linear combination of single VF-PCM and discrete-ZVS control model. After considering the sampling effect and the modulator gain from the derived sampled-data model respectively, the control-to-output transfer function of CrCM ACF converter is developed. The analytical results are analyzed by comparing with single VF-PCM and the widely used average model. Finally, to validate the accuracy of the proposed model, a 65W 20V output CrCM ACF converter is simulated and measured. The verification shown that the proposed sampled-data model is basically agreement with the simulation and experimental results. [ABSTRACT FROM AUTHOR]

In this work we propose a single channel band-pass (BP) SAR ADC with dynamic noise transfer function (NTF) re-configuration. The proposed ADC employs a low-power two-stage architecture. After the SAR finishes quantization, the residue is extracted by firing the comparator multiple times. An estimate of the residue is obtained by employing a maximum likelihood based estimator (MLE). The output of the ADC is obtained by subtracting a delayed version of the estimated residue from the SAR output thus generating a complex NTF with multiple notches in the spectrum. A 65nm ADC prototype achieves 74.1/78dB SNDR/DR over a 101.2kHz bandwidth while consuming 17 μW from a 1V supply at 2.43MS/s. The ADC core occupies an area of 0.12mm2. The ADC achieves 8fJ/c-step bandpass FoM which is 85 × better than state-of-the-art BP ADCs with similar bandwidth and 8.7 × better than all reported state-of-the-art BP ADCs. [ABSTRACT FROM AUTHOR]

Analysis of ac electrical systems can be performed via frame transformations in the time-domain or via harmonic transfer functions (HTFs) in the frequency-domain. The two approaches each have unique advantages but are hard to reconcile because the coupling effect in the frequency-domain leads to infinite dimensional HTF matrices that need to be truncated. This paper explores the relation between the two representations and shows that applying a frame transformation on the input-output signals creates a direct equivalence to a similarity transformation to the HTF matrix of the system. Under certain conditions, such similarity transformations have a diagonalizing effect which, essentially, reduces the HTF matrix order from infinity to two or one, making the matrix tractable mathematically without truncation or approximation. This theory is applied to a droop-controlled voltage source inverter as an illustrative example. A stability criterion is derived in the frequency-domain which agrees with the conventional state-space model but offers greater insights into the mechanism of instability in terms of the negative damping (non-passivity) under droop control. Therefore, the paper not only establishes a unified view in theory but also offers an effective practical tool for stability assessment. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable delta-sigma modulation (DSM) architecture for concurrent multi-band transmission. The reconfigurability in terms of carrier spacing and the number of simultaneous carrier transmission is useful for applications such as carrier aggregation in 5G. This paper uses $4^{th}$ order reconfigurable multi-band DSM (RMB-DSM) such that the zeros of the noise transfer function can be reconfigured to fall at multiple frequencies, where the carriers are being aggregated. The quantization noise between the transmission bands is a critical issue in the case of multi-band transmission. Therefore, a multi-band additional noise shaping (ANS) function is also introduced, which generates notches around each carrier and reduces the noise level between the multiple pass-bands. The proposed scheme has been validated in simulation, as well as in experiment for aggregating up to four 15 MHz long term evolution (LTE) signals with an overall aggregated bandwidth of 60 MHz. Measurement results show a 10-25% improvement in coding efficiency and 15-35 dB improvement in noise level near the operating frequency band using the proposed multi-band augmented noise shaping technique, as compared to the standard DSM. The corresponding improvement of 8% in the overall efficiency is observed by using the proposed multi-band augmented noise shaping technique. [ABSTRACT FROM AUTHOR]

For the first time, we present a generic, formal design and optimization method for a fully-passive loop filter based CTDSM. The presented method aims at the automatic design of compact, low energy and simple, fully passive CTDSM for multi-channel biomedical applications. The challenges involving high RC variations, low energy consumption and compactness for multi-channel applications necessitates automated design and optimization of the CTDSM. The proposed method uses a simple linear model to arrive at the loop filter transfer function and minimize the SNR degradation across RC corners while minimizing the area and power per channel. The method was implemented in Matlab and verified using Spectre simulations. For target ENOB of 9 bits and consumed energy of less than 60 fJ/conv a CTDSM was automatically designed using the proposed method and fabricated in standard 180 nm CMOS mixed mode technology. The CTDSM uses a fully passive second order modulator with the CIFF architecture eliminating active summer circuits. The measurement results show that the modulator achieves peak SNDR of 55.42 dB at 1V supply while consuming 61.2 fJ/conv and occupies an extremely small area of 0.068 mm2 making it the most compact reported CTDSM modulator among the low energy moderate resolution CTDSM. [ABSTRACT FROM AUTHOR]

This paper presents a generic foreground calibration algorithm that estimates and corrects memoryless nonlinear impairments in both single channel and time-interleaved analog-to-digital converters (TIADCs), and which is capable of correcting for amplifier nonlinearity, comparator offsets, and capacitance mismatch for each channel. It operates by generating, and then using, a look-up table which maps raw ADC output decision vectors to linearized output. For TIADCs, the algorithm also uses information gained during the calibration phase to estimate timing and gain mismatches among the sub-ADCs. The problem of selecting an appropriate timing reference so as to relax the requirements on the time-skew correction circuitry is statistically analyzed, as is the corresponding impact on manufacturing yield. Accordingly, a new method is proposed having superior performance; for example, in the case of an eight sub-ADC TIADC system, the proposed scheme reduces the time skew correction requirement by 44% compared with conventional methods. The architecture is instrumented with some additional circuitry to facilitate built-in self-test, allowing manufacturing test time and cost reductions. Implementation aspects are discussed, and several complexity reduction techniques are presented along with synthesis results from a Verilog implementation of the calibration engine. [ABSTRACT FROM AUTHOR]

The performance of analog integrated circuits is often limited by the noise generated in its components. Several circuit techniques exist for mitigating the effects of the low-frequency noise. In this paper, a novel approach is described, which can also reduce even-order distortion, another major limitation of analog circuits. It may also allow the use of single-ended circuits in applications where usually differential structures are needed. In most cases, the resulting single-ended circuit will be much simpler than the fully or pseudo-differential one. It does not require common-mode feedback circuitry, nor single-ended-to-differential and differential-to-single-ended conversions at the input and output ports. The amplifiers may be single-ended, using, e.g., inverter-based circuits, and the use of baluns can be avoided. The number of pins and pads of the chip can be reduced. In addition, the single-ended opamps of the circuit may require less power than differential ones. These factors and the omission of the common-mode feedback circuits as well as the single-ended/differential converters will usually allow significant power savings. [ABSTRACT FROM AUTHOR]

In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interference. Moreover, by filtering the feedback signal in the discrete-time domain, the jitter robustness of the modulator is greatly improved and most importantly the slewing requirements on the OpAmps in the modulator’s loop filter are greatly relaxed up to a level that the OpAmps can be scaled down toward their ultimate noise limited power level. Furthermore, this LPSC-DAC does not suffer from the SCR-DAC’s disadvantageous trade-off between the modulator’s jitter, slewing, and anti-aliasing performance. We also show how to compensate for the extra pole of the LPSC-DAC, such that the CTSDM’s loop filter, noise- and signal-transfer function remains unchanged. As a result, this technique is completely transparent to the system level designer and established system-level design techniques for sigma delta modulators remain applicable. [ABSTRACT FROM AUTHOR]

This paper presents a programmable single-chip sustaining amplifier for MEMS-referenced oscillators. The chip integrates a low-noise amplifier, variable-gain amplifiers (VGAs), band-pass filters (BPFs), all-pass filters (APFs), automatic level control, and output buffers. It also contains a second signal path for background cancellation, i.e., eliminating the effect of electrical feedthrough capacitance of the MEMS resonator. Important parameters of each circuit block (e.g., VGA gain, BPF center frequency and quality factor ($Q$), APF phase shift, and so on.) can be set using bias currents, thus enabling fine-grained control over the overall transfer function. The amplifier was designed and fabricated in $0.5~\mu \text{m}$ CMOS. The chip was integrated with board-level current DACs (programmable via an I2C bus) and tested inside a vacuum chamber with various polysilicon (poly-Si) and single crystal (SC-Si) silicon comb-drive MEMS devices with resonant frequencies in the 10–90 kHz range. Oscillators referenced to a high- $Q$ (~13 000) SC-Si device had 20 dBc/Hz lower close-in phase noise (at 10 Hz) than those referenced to the low- $Q$ (~320) poly-Si device. Experimental results highlight advantages of the design, including automatic mode selection, background cancellation, control of feedback phase to optimize phase noise, and frequency locking to an external reference. [ABSTRACT FROM AUTHOR]

Delta-sigma modulators spectrally shape quantization noise in discrete systems and are used extensively in communications and signal-processing systems. They are implemented using a loop-filter that processes the input and feed-back signals such that the closed loop behavior has a separate signal transfer function (STF) and noise transfer function (NTF). Loop-filter design often relies on special cases for the NTF or simplified loop-filter structures. This paper presents a method for generalized loop-filter synthesis that can implement a chosen NTF and STF independent of internal loop-filter structure or filter order. The transfer functions are formulated as polynomials of integration, $(z-1)^{-n}$ , instead of delay, $z^{-n}$ , to enable practical numerical loop-filter synthesis even for high-order and highly oversampled loop-filters. An example design shows how to use this synthesis method to design a high-order modulator that directly filters and re-modulates a direct stream digital audio signal. [ABSTRACT FROM AUTHOR]

In this paper, we formulate and prove new results in the context of storage functions for lossless systems: we use these results to propose new algorithms to compute the storage function. The computation of the storage function for the lossless case is not possible using conventional algebraic Riccati equation-based algorithms, though the storage function itself is well-defined. This is because a certain “regularity condition” on the feedthrough term in the i/s/o representation of the lossless system does not hold. We formulate new results about the storage function matrix for the lossless case and use them to propose non-iterative and stable algorithms to compute the storage function directly from different representations of the given system, namely, a kernel representation, transfer function, and the i/s/o representation of the system. Across the methods, for randomly generated transfer functions, we compare: 1) the computational effort (in flops); 2) the computation time using numerical experiments; and 3) the computational error. [ABSTRACT FROM AUTHOR]

An oversampling stochastic analog-to-digital converter is presented. This stochastic converter spatially averages quantization errors in multiple voltage-controlled oscillator (VCO)-based quantizers. Unlike other stochastic converters, this proposed architecture does not require an inverse Gaussian cumulative density function estimator. The digital adder becomes an ideal estimator due to uncorrelated quantization errors, which can be modeled as a uniformly distributed random variable. Because of the simple open-loop structure, this stochastic converter can easily be synthesized and reconfigured. The proof-of-concept prototype is implemented in a 0.18 $\mu \text{m}$ CMOS process. The prototype employs eight VCO-based quantizers and validates the extra 9 dB signal to quantization noise ratio improvement from quantization error spatial averaging. The measurements further demonstrate 54.2 dB and 45.4 dB SNDR for 50 MHz and 100 MHz bandwidths, while dissipating 116 mW of power. [ABSTRACT FROM AUTHOR]

This paper presents new techniques to obtain sample-by-sample analog-to-digital conversion using a delta–sigma modulator (DSM) without resetting the modulator or the decimation filter. It is shown that memoryless A/D conversion without reset can be realized using a discrete-time DSM with a signal transfer function (STF) of unity and a Nyquist $M$ -band decimation filter running at the oversampled rate. It is also shown that a delta–sigma ADC preceded by a sample-and-hold at the Nyquist rate is a linear, time-invariant system at the Nyquist rate. This relaxes the constraint on the STF and allows using a multi-rate decimation filter and an equalizer at the Nyquist rate to significantly lower the power in the digital filters. Crosstalk suppression, which is limited by analog imperfections when a fixed-coefficient equalizer is used, is shown to be substantially improved using an adaptive equalizer at the Nyquist rate. A 180-nm prototype operating at 32 MHz and an OSR of 32 demonstrates two-channel operation with crosstalk below 89 dB. It consumes 18.2 mA from a 1.8-V supply, occupies 3.86 mm2 and has DR/SNR/SNDR of 84.2/82.5/80.1 dB. [ABSTRACT FROM AUTHOR]

This paper presents a systematic method to analyze $N$ -path mixers and filters consisting of periodically switched $RC$ -networks of arbitrary order. It is assumed that each capacitor periodically exchanges charge with the rest of the network during the on-phase of the switching clock, then samples its charge, and holds it perfectly until the next on-phase. This assumption allows for using the adjoint network for simplified analysis of the harmonic transfer functions that describe the signal transfer and folding. Moreover, harmonic transfer cancellations due to the $N$ -path implementation with $N$ equal capacitors switched by $N$ non-overlapping clocks are systematically analyzed. The method is applied to a recently published $N$ -path filter-mixer combination and verified by simulations. [ABSTRACT FROM AUTHOR]

In this paper, a design method for high-order delay-lock loops (DLLs) is presented and verified through simulations and physical experiments. The general approach is based on selecting the closed-loop transfer function of the DLL, together with identifying the coefficients of the phase-detector and voltage-controlled delay line, and subsequently, solving for parameters of the loop filter of the DLL. Past DLL design approaches relied more on establishing a desired phase margin requirement than attempting to establish a desired input–output behavior. This limited the realization of DLLs to second order; largely a result of the complicated mathematics that arise. As the method proposed in this paper is based on selecting a desired closed-loop transfer function, the issues of stability or phase margin never come to the forefront. This paper will show how a DLL can be designed to achieve a fast-settling-zero-overshoot step response with large jitter-rejection capabilities. The method is simple and easy to execute. No optimization or iteration is necessary. The method is similar to the methods used to design active-RC filter circuits. A fully programmable experimental prototype involving a custom IC implemented in a 130-nm IBM CMOS process was constructed. DLLs with orders ranging from second to eighth will be investigated. [ABSTRACT FROM PUBLISHER]