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This paper presents a 32-channel analog filterbank for front-end signal processing in sound classification systems. It employs a passive N-path switched capacitor topology to achieve high power efficiency and reconfigurability. The circuit’s unwanted harmonic mixing products are absorbed by the machine learning model during training. To enable a systematic pre-silicon study of this effect, we develop a computationally efficient circuit model that can process large machine learning datasets on practical time scales. Measured results using a 130 nm CMOS prototype IC indicate competitive classification accuracy on datasets for baby cry detection (93.7% AUC) and voice commands (92.4% average precision), while lowering the feature extraction energy compared to digital realizations by approximately $2\times $ and $10\times $ , respectively. The 1.44 mm2 chip consumes 800 nW, which corresponds to the lowest normalized power per simultaneously sampled channel in recent literature. [ABSTRACT FROM AUTHOR]

This paper presents a two-way time-interleaved (TI) 7-bit 2-GS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The design achieves wideband operation with an effective resolution bandwidth (ERBW) in the 3rd Nyquist zone. The converter’s front-end employs current integrating (CI) sampler that provide both buffering and anti-alias (AA) filtering at low power dissipation. Facilitated by the CI-samplers’ inherent inter-sample interactions, the timing mismatch among the TI channels can be detected in the amplitude domain, obviating the need for a dedicated reference channel for background calibration. After calibration, the ADC achieves 36.4 dB signal-to-noise-and-distortion ratio (SNDR) near Nyquist and >2.6 GHz ERBW at a sampling rate of 2 GS/s. The ADC’s power consumption is 7.62 mW (including the CI buffer) and its Walden figure of merit (FoMw) is 70.8 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

The integrator is an important building block in circuit design and its transfer characteristic is inherently frequency-dependent. When it is implemented as an $RC$ op-amp circuit, a nonlinear element (the amplifier) is placed within a frequency-dependent feedback loop. Conventional techniques allow us to obtain the nonlinear error easily at certain frequencies only. Furthermore, when the integrator is periodically reset, the circuit is not in steady-state and conventional techniques assuming a steady-state behavior do not apply. It is not obvious how the actual error relates to the circuit parameters when the integrator is driven with a wideband signal. In this paper we present an approach to quickly estimate the normalized mean squared error (NMSE) as a function of the circuit and signal parameters. We show that, to first-order, the NMSE is proportional to the ratio of the signal bandwidth and the dominant pole of the integrator. For an integrator with reset, the signal builds up from zero and results in an additional, integration-time dependent NMSE reduction. [ABSTRACT FROM AUTHOR]

This paper presents a feedback receiver for the digital predistortion (DPD) of radio frequency (RF) power amplifiers (PAs). In contrast to conventional architectures, the receiver samples in the frequency domain. By randomly selecting a frequency bin in each sampling interval, the PA model is identified with substantially lower acquisition bandwidth and sampling rate. The receiver prototype is implemented in a 28-nm FD-SOI technology and samples at 4MS/s instead of the full Nyquist rate of 168MS/s for a 20-MHz Long Term Evolution (LTE) signal with spectral regrowth. The prototype is shown to linearize a 4-W small base station power amplifier from an adjacent channel leakage ratio (ACLR) of −35 dBc to −47.7 dBc, after processing only about 250 samples. [ABSTRACT FROM AUTHOR]

Energy harvesting is an emerging technology for powering wireless sensor nodes, enabling battery-free operation of these devices. In an energy harvesting sensor, a power management circuit is required to regulate the variable harvested voltage to provide a constant supply rail for the sensor circuits. The power management circuit needs to be compact, efficient, and robust to the variations of the input voltage and load current. A closed-form power expression and custom control algorithm for regulation of a switched-capacitor DC-DC converter with optimal conversion efficiency are proposed in this paper. The proposed regulation algorithm automatically adjusts both the voltage gain and switching frequency of a switched-capacitor DC-DC converter based on its input voltage and load current, increasing the power efficiency across a wide input voltage range. The design and simulation of a fully integrated circuit based on the proposed power managing approach is presented. This power management circuit has been simulated in a 0.25 \mum standard CMOS process and simulation results confirm that with an input voltage ranging from 0.5 V to 2.5 V, the converter can generate a regulated 1.2 V output rail and deliver a maximum load current of 100 \muA. The power conversion efficiency is higher than 74% across a wide range of the input voltage with a maximum efficiency of 83%. [ABSTRACT FROM AUTHOR]

Even though small metal fringe capacitors are important for the realization of a variety of circuits, including low-energy analog-to-digital converters and digitally controlled oscillators, the present literature is lacking experimental data on their mismatch characteristics. This paper describes a test structure and measurement results pertaining to the characterization of single-layer, lateral-field, 0.45-fF and 1.2-fF unit metal capacitors in a 32-nm SOI CMOS process. The measurement-inferred average standard deviations for these capacitances are 1.2% and 0.8%, respectively, confirming area scaling according to Pelgrom's matching formula. [ABSTRACT FROM AUTHOR]

This paper presents the design and optimization of a nested-Miller compensated, three-stage operational transconductance amplifier (OTA) for use in switched-capacitor (SC) circuits. Existing design methods for three-stage OTAs often lead to sub-optimal solutions because they decouple inter-related metrics like noise and settling performance. In our approach, the problem of finding an optimal design with the best total integrated noise and settling time has been cohesively solved by formulating a nonlinear constrained optimization program. Equality, inequality, and semi-infinite constraints are formed using closed form symbolic expressions obtained by a closed loop analysis of the SC gain stage and the optimization program is solved by using the interior-point algorithm. For the optimization routine, there is no need to interface with a circuit simulator because all significant device parasitics are included in the model. The optimization and modeling steps are general in nature and can be applied to any amplifier or filter topology. Simulation results show that a 90-nm prototype amplifier achieves a \pm 0.1\\% dynamic error settling time of 2.5 ns with a total integrated noise of 240 \mu Vrms, while consuming 5.2 mW from a 1-V power supply. [ABSTRACT FROM PUBLISHER]

This paper presents an open-loop design method for fast-settling three-stage class-A amplifiers. Specifically, using the open-loop damping factor as a design parameter, the presented method delivers robust settling performance of a third-order system in the presence of process and component variation. As an illustration of the proposed approach, we show Spice simulation results of a nested-Miller-compensated three-stage-amplifier designed in 0.35-µm CMOS technology. The design achieves a 1% and 0.1% dynamic-error settling times of 6.4 ns and 13.7 ns, respectively, at a gain-bandwidth product of 55 MHz and a dynamic range of 80 dB, while consuming 5.4 mW from a 3-V supply. [ABSTRACT FROM AUTHOR]

Time-interleaved analog-to-digital converters (TIADCs) are sensitive to various mismatches that distort the sampled signal. Standard TL&DC analysis assumes a narrowband sinusoidal input, which may result in pessimistic matching constraints for system-specific ADCs used with wideband input signals. Closed-form expressions bounding the acceptable phase-skew for wideband systems are derived and are validated through simulations. In one of the examples presented, it is shown that standard analysis can overconstrain the bound on acceptable phase-skew variance by a factor of three. [ABSTRACT FROM AUTHOR]

A very important limitation of high-speed analog-to-digital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and today's designs. [ABSTRACT FROM AUTHOR]

Electronic noise is a significant and fundamental issue in the design of analog circuits. In the widely used class of switched-capacitor circuits, the noise metric of interest is the so-called total integrated noise. Closed-form expressions for this quantity are unavailable in literature for all but the simplest circuit configurations that involve first-and second-order noise transfer functions. The lack of these expressions has prevented design automation and performance optimization without relying on repetitive simulations. In this paper we provide a general formula for calculating the total integrated noise in arbitrary circuits. The results are applied to two popular operational transconductance amplifier (OTA) circuits; a two-stage Miller-compensated architecture and a two-stage cascode-compensated topology. Simulations show that the calculated noise for these circuits is in close agreement with SPICE simulations. [ABSTRACT FROM AUTHOR]

This paper describes a background calibration technique for analog-to-digital converters (ADCs) that exploits communication protocol redundancy to measure and correct for analog circuit imperfections. In particular, we consider the implementation of a 6-bit, 500-MS/s ADC in the receiver of an ultra wideband system using orthogonal frequency division multiplexing (OFDM). The calibration is intended for a time-interleaved array of successive approximation register ADCs and cancels converter nonlinearity due to inter-channel offset mismatches. The individual channel offsets are estimated through statistical correlation, based on known pseudorandom modulation sequences used in OFDM pilot tones. Our simulation results show that the proposed calibration is capable of improving the signal-to-noise and distortion ratio from 20 to 37 dB with a tracking time constant of 85 ms, assuming an additive white Gaussian noise channel with 20-dB signal-to-noise ratio. [ABSTRACT FROM AUTHOR]