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In this paper, for the first time, the phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to the three stages of conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved phase noise with increasing stages. The primary distinction between these two designs (SDRO and three-stage CROs) is the inherent skew offset between the PMOS/NMOS gates caused by the unique connection. This skew offset is the fundamental cause of delay cell noise suppression; the SDROs have loosely coupled oscillators that run concurrently, forming multiple 3-stages of separately driven Ring Oscillators. As a result, a shaping function is derived in terms of skew offset, and simulating these with varying skew offset results in suppressing behavior. Additionally, we derived phase noise for a skew-based design and validated it in PDKs of 180nm and 65 nm. We plotted the thermal (flicker) noise contribution and found that increasing the number of stages leads to an approximately 1-2 dB reduction in phase noise while maintaining the same NMOS/PMOS size ratio. Finally, a 2-3 dB reduction in phase noise is achieved in MSSROs by incorporating the shaping function into phase noise equations. [ABSTRACT FROM AUTHOR]

This paper introduces a new true random number generator (TRNG) based on a three-edge ring oscillator. Our design uses a new technique with a time-to-digital converter to effectively acquire jitter accumulated independently by each edge. As a part of the security evaluation, we present the stochastic model of the TRNG’s digital noise source and estimate a lower bound of the min-entropy per random bit. Starting from the obtained entropy bound, we propose a procedure for selecting and implementing an area-efficient and throughput-optimal post-processing function based on the best known linear codes that will increase the output min-entropy rate to more than 0.999. The proposed TRNG exquisitely balances low design effort and resource consumption with high throughput and a high min-entropy rate, making it more suitable for randomness-demanding and resource-constrained platforms than the state-of-the-art. The complete implementation of the TRNG digital noise source and the post-processing occupies 33 slices and achieves a throughput of 12.5 Mbps on Xilinx Zynq-7000 FPGAs. The min-entropy of the generated random bits is assessed by NIST SP 800-90B entropy estimators, and the tested sequences pass the AIS-31 test suit. [ABSTRACT FROM AUTHOR]

A digital-intensive four-level pulse amplitude (PAM-4) transceiver featuring a 2-tap time-based decision feedback equalization (TB-DFE) circuit was demonstrated in a 65 nm GP CMOS process. A novel inverter-based differential voltage-to-time converter (DVTC) increases the linearity and dynamic range compared to a prior time-based DFE approach enabling reliable PAM-4 operation. The four-level signal comparison and DFE operation were performed entirely in the time domain using programmable delays and a phase detector (PD). Using an on-chip bit error rate (BER) monitor, we verified a BER less than 10−12 while achieving an energy-efficiency of 0.97pJ/b at a 32Gb/s data rate. The transmitter (TX) and receiver (RX) circuits occupy an area of 0.009 mm2. [ABSTRACT FROM AUTHOR]

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively. [ABSTRACT FROM AUTHOR]

The continuous-time pipelined (CTP) ADC is a promising emerging high-speed analog-to-digital conversion technique that achieves anti-alias filtering and analog-to-digital conversion in one step. Driving such a converter is easy, thanks to its resistive input impedance. RC time-constant shifts, which will occur in practice due to a change in ambient temperature, degrade the performance of such converters. The aim of this work is to understand this phenomenon, quantify the resulting SNDR degradation, and thereby derive design tradeoffs. The theory is compared with measurements from a three-stage CTP that targets 70dB SNDR in a 100MHz bandwidth while sampling at 800MS/s. [ABSTRACT FROM AUTHOR]

This work demonstrates a Continuous-Time (CT) Ladder filter using transconductance amplifiers as an approximate delay stage implemented on a large-scale Field Programmable Analog Array (FPAA) and characterized on an SoC FPAA. We experimentally demonstrate a reprogrammable CT Analog linear-phase filter by utilizing the ladder filter delay element and Vector-Matrix Multiplication (VMM) both compiled on the SoC FPAA. Using the Ladder Filter as a programmable CT delay operation enables a traditionally difficult analog signal operation. This effort extensively models and characterizes the ladder filter delay stage in terms of its transfer function, delay tunability, power requirements, distortion, and SNR. The theoretical development is compared to experimental measurements on an SoC FPAA with programmable ladder filter delay of $2.9\mu \text{s}$ and $4.2\mu \text{s}$ for multiple input frequencies (e.g. 5kHz, 20kHz). In addition, we show that VMMs can compensate the non-idealities found in the ladder filter delay-line operation. [ABSTRACT FROM AUTHOR]

The Stochastic Phase-Interpolation Time-to-Digital Converter (SPI-TDC) leverages redundancy to tolerate Process-Voltage-Temperature (PVT) variations. This article presents a comprehensive analysis of the linearity of the SPI-TDC and its error mechanisms, and proposes a linearization technique to reduce the redundancy requirement. Using deterministic and stochastic models, this article analyzes the effects of the unit delay, length of the delay-line, clock frequency, jitter, and mismatch on the linearity of the SPI-TDC, and prescribes a compact set of design equations to guide the designer. Based on the results of the analysis, the article proposes a robust solution using a Delay-Locked Loop (DLL) to linearize the SPI-TDC with reduced hardware and power overhead. This article also analyzes, for the first time, the loop dynamics of a DLL accounting for the delay of the delay-line. Measurements of an 8-bit, 60-MHz SPI-TDC validate the theories and demonstrate the effectiveness of the proposed solution across supply and temperature variations while using only $4\times $ redundancy. [ABSTRACT FROM AUTHOR]

In this article, a digitally controlled voltage-mode buck converter with embedded transient improvement using delay line-based control techniques is presented. Two voltage-controlled delay lines (VCDL’s) are used to convert the difference between the feedback and reference voltages to a delay time difference. The delay difference is then fed to the multiple-outputs bang-bang phase detector (MOBBPD), which converts the input delay difference to multiple-bits digital codes in a simple nonlinear way. The MOBBPD scheme leads to high resolution for small output ripple and improved response when large load transient happens in a low-cost way. A digital loop filter (DLF) accumulates the MOBBPD output codes to control the duty cycle through a novel digital pulse width modulator (DPWM) to regulate the output voltage. By designing the coefficients of the DLF, a type-II compensator can be achieved through the integral and proportional paths to make the loop stable. The proposed DPWM, which consists of a divide-by-8 frequency divider, two delay lines and a few simple digital logics, achieves a wide tunable range of duty cycle under various process corners and supply voltages. A proof-of-concept design of the proposed buck converter was fabricated in a standard $0.18~\mu \text{m}$ CMOS technology. The measured results show that it achieves a very wide output voltage range from 0.1 V to 3.5 V for a input supply range from 2.4 V to 3.6 V. With a 400 mA step in the load current, the overshoot/undershoot is less than 87 mV and the 1% settling time is less than $16~\mu \text{s}$. The peak efficiency is 95.2% with 250 mA load current at 2.4 V output voltage with 3.3 V input voltage. [ABSTRACT FROM AUTHOR]

The increase of clock frequency in digital circuits exacerbates the electromagnetic interference (EMI) between devices. Spread-spectrum techniques reduce the electromagnetic noise lowering harmonic peaks of the clock signal by means of frequency modulation. In System-on-Chips (SoCs) another requirement in many applications is the coexistence of both modulated and un-modulated clock domains. In these cases, suitable synchronization systems are used to allow data to cross the boundary between spread and un-spread clock domains. In this paper we present a spread-spectrum clock generator (SSCG) able to provide both spreaded and un-spreaded clocks. The spreaded clock has a specially designed modulation profile, allowing at the same time a seamless synchronization-free interface between spreaded and un-spreaded clock domains and a large EMI reduction. The paper presents the derivation of the new highly discontinuous modulation profile (that allows to achieve an EMI reduction up to 15.8dB) and implementation details of an all-digital SSCG able to provide the developed modulation waveform. A test chip has been fabricated in UMC 65nm CMOS technology, using a novel dual-output digitally controlled delay line. The circuit can generate both spread and un-spread clocks (double output mode) or the spread clock alone (single output mode). Area occupation is 0.102mm2, whereas power consumption is 48.5mW in double output mode and 34mW in single output mode. [ABSTRACT FROM AUTHOR]

An M-ary Differential Chaos Shift Keying modulation using Chaotic Shape-forming Filter (CSF-M-DCSK) is proposed here to transmit two sub-streams with different system performances. The chaotic shape-forming filter is used to generate the chaotic carrier which is modulated according to the DCSK concept. The modulated chaotic signal is demodulated by a coherent matched filter receiver and the maximum likelihood decision rule is used to get the best noise performance. Compared to DCSK and its enhanced versions, the new modulation scheme offers not only better noise and multipath performances but also a higher data rate. The hardware implementation of the proposed method is as simple as that of a conventional communication system. Analytical expressions have been derived for the CSF-M-DCSK Bit Error Rate (BER) and its performance has been evaluated in AWGN and multipath channels by simulations. The new CSF-M-DCSK system has been implemented and successfully tested on a Wireless open-Access Research Platform (WARP). Results of simulations and measurements performed in real application scenarios have proven the feasibility and superiority of CSF-M-DCSK over its competitors. [ABSTRACT FROM AUTHOR]

This article describes a 10.7b 300MS/s two-step digital-slope analog-to-digital converter using an on-chip digital-offset correction. The proposed two-step digital-slope ADC is implemented using a passive track-and-hold followed by the input-polarity comparison and the two-step digital-slope conversion. The polarity of the input signal must be determined to control the level-shifting process and specify the operation polarity of the two-step digital-slope conversion. Besides, the two-step digital-slope conversion shares the unary DAC with different weights, which not only mitigates the resolution issues of the digital-slope quantizer but also converts the residue without requiring gain-error calibration. The two-step digital-slope ADC can be divided into three conversion steps and provide 1-bit, 5.7-bit, and 4-bit resolution for each conversion cycle. The digital-offset correction then encodes the three sets of outputs and subtracts the digital-offset caused by the feedback-process latency of the quantizers. The proposed two-step digital-slope ADC is manufactured using 1P9M 65-nm CMOS technology, and the active area of the prototype is 0.0946 square millimeter. At the Nyquist frequency, the SNDR and SFDR measured at 1.2 V, and 300 MS/s are 60.72 dB and 70.05 dB, respectively. With the power consumption of 6.2mW, the corresponding Walden FoM is 23.3 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where $R^{2}$ maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps. [ABSTRACT FROM AUTHOR]

This paper proposes a low power 10-bit 2b/cycle time and voltage based-successive approximation register (SAR) analog-to-digital converter (ADC). At low supply voltage, there will be a significant difference in comparator decision time for different input voltages. By taking advantage of the fact, this ADC converts the reference voltage to the corresponding comparator decision time, achieving 2b/cycle quantization to improve the conversion speed. In addition, by obtaining reference delays with duplicated circuits and using non-binary capacitor arrays, the ADC can tolerate process, voltage and temperature (PVT) variations and decision errors. To validate these concepts, a 10-bit 2MS/s SAR ADC is designed using 130nm CMOS process with 0.5V power supply voltage. Measured results show that the ADC can work normally from 0.5V to 1V supply voltage, with the sampling rate increasing from 2MS/s to 32MS/s. The ADC achieves an SNDR (signal-to-noise distortion ratio) of 56.7dB, corresponding to an ENOB (effective number of bits) of 9.13 bits and consumes $3.4\mu \text{W}$ , resulting in a figure of merit (FoM) of 3.03 fJ/c.-s at 0.5V supply voltage and 2MS/s sampling rate. [ABSTRACT FROM AUTHOR]

This work presents a low-power all-digital approach to multiphase delay locked loop (DLL) design by the use of a scalable phase-to-digital converter (PDC) based on asynchronous sampling. The PDC is used as a linear phase detector (PD) with the ability to measure any phase difference leading to a shorter delay line with less power consumption. Two different approaches for the delay cell implementation are investigated. The digitally controlled shunt-capacitor inverter (SCI) delay cell leads to an extremely small design with the delay line being the only analog component, while the voltage controlled current-starved inverter (CSI) delay cell has a lower power consumption and less jitter. The proposed design procedure of the SCI based DLL allows fast simulation using Verilog based models since no analog low pass filter is required. Using the proposed modeling technique for the PDC, the behavior of the DLL can be estimated based on input clock jitter specifications. The SCI and CSI based multiphase DLL designs are fabricated in a 65nm CMOS process operated from a 1.2V supply. The proposed SCI based DLL occupies only 0.0048mm2 of active area and consumes 2.25mW at 2.5GHz input frequency with a 622.6MHz sample clock. The RMS jitter of the circuit is 1.2 ps and 1.4 ps for the DLL loop and the phase shifter loop, respectively. The RMS jitter is significantly reduced with the CSI based DLL to 0.86 ps and the power consumption of 2.64mW at 4GHz input frequency with a 996.1MHz sample clock provides an improved power efficiency compared to the SCI based DLL. As a trade-off, the area is increased to 0.0085mm2 due to the use of a $\Delta \Sigma $ modulator and an analog low pass filter. [ABSTRACT FROM AUTHOR]

This paper proposes an ultra-compact 4 to 10-Gb/s 5-tap current-mode transmitter to realize the sub 1-UI fractional de-emphasis (DE) using a hybrid delay line, which is alternatively controlled by the voltage bias and clock. It exhibits the scalability between the clocked 0.5-UI and 1-UI DEs and data rate. The sub-1-UI DE provides wide tunability of the data amplitude and delay to compensate different channel losses between the $1^{st}$ and $2^{nd}$ Nyquist frequencies while effectively compensating the high-frequency portion of the pseudo-random binary sequence (PRBS) spectrum for data jitter improvement. Additional techniques are a two-step current-summing scheme, namely, two-step DE in the data path, and active inductors in both the data and clock paths to enhance the internal bandwidth without the need for passive inductors. In addition, we present an analytical model for predicting data-dependent jitter (DDJ) based on a generic system’s step response, derive the exact closed-form DDJ expression of DE, and verify its validity by mean of circuit simulation. Prototyped in 65-nm CMOS technology, it achieves a figure-of-merit of 4.6 mW/Gb/s and an output jitter of 10.8 pspp at 10 Gb/s under a PRBS $2^{31}-1$ pattern. The data eyes measure 0.62-UI-horizontal and 19.5%-vertical openings after −20-dB channel loss. The die area is 0.0071 mm2. [ABSTRACT FROM AUTHOR]

A new, all-digital on-chip peak-to-peak (p-p) jitter measurement circuit (OCJM) that features automatic resolution calibration for high PVT-variation resilience without a reference clock and off-line calibration is presented in this paper. The OCJM uses a front-end self-referenced circuit (SRC) to eliminate the jitter-free reference signal and a back-end p-p jitter detector (PPD) to perform p-p jitter measurements. The key design of the proposed OCJM is that the SRC and the PPD share a Vernier delay line (VDL) so that the run-time PVT information automatically extracted from the SRC operation can be carried onto the PPD to achieve automatic on-line resolution calibration. Besides this feature, the OCJM uses on-chip direct p-p jitter measurement with only 1-time readouts to eliminate the huge power consumption of the off-chip data communication while avoiding data loss of a possible large jitter caused by PVT variations during off-chip data communication. These techniques make the proposed OCJM suitable for any-time, any-site jitter measurements for SoC applications. The proposed OCJM is fabricated in a 28-nm CMOS. The measurement results show that the timing resolution and minimum measurable jitter range specifications are met under extreme PVT conditions while achieving 98% clock cycle and energy reduction compared to the conventional OCJM designs. [ABSTRACT FROM AUTHOR]

We consider a digital encoding/processing system in which both the analog-to-digital converter and the digital signal processor are implemented by repeating a single fundamental design unit: the digital delay. Timing becomes an integral part of the resulting signal representation and processing, thereby promising to improve with technology scaling. System properties are studied and design considerations for a potential integrated implementation are discussed. Simulation results confirm the theory. [ABSTRACT FROM AUTHOR]

This paper demonstrates a completely on-chip implementation of expansion and compression of continuous-time, wideband, analog pulses. The input pulse is fed to a continuous-time filter whose delay exceeds the pulse duration. Once the pulse is completely inside the filter, it is stored in the form of the filter’s state-variables, which can completely reconstruct the pulse. Instantaneously decreasing or increasing the filter’s bandwidth at this instant results in the output pulse being expanded or compressed, respectively, compared with when the bandwidth is unchanged. A 1.6 mm2, 370 mW, 0.13 $\mu \text{m}$ prototype has a delay filter whose bandwidth can be switched between 870 and 472 MHz. It achieves $1.8\times $ pulse expansion and $1.7\times $ pulse compression with an rms error which is 33 dB below the peak-peak pulse amplitude. [ABSTRACT FROM AUTHOR]

In this paper, a design method for high-order delay-lock loops (DLLs) is presented and verified through simulations and physical experiments. The general approach is based on selecting the closed-loop transfer function of the DLL, together with identifying the coefficients of the phase-detector and voltage-controlled delay line, and subsequently, solving for parameters of the loop filter of the DLL. Past DLL design approaches relied more on establishing a desired phase margin requirement than attempting to establish a desired input–output behavior. This limited the realization of DLLs to second order; largely a result of the complicated mathematics that arise. As the method proposed in this paper is based on selecting a desired closed-loop transfer function, the issues of stability or phase margin never come to the forefront. This paper will show how a DLL can be designed to achieve a fast-settling-zero-overshoot step response with large jitter-rejection capabilities. The method is simple and easy to execute. No optimization or iteration is necessary. The method is similar to the methods used to design active-RC filter circuits. A fully programmable experimental prototype involving a custom IC implemented in a 130-nm IBM CMOS process was constructed. DLLs with orders ranging from second to eighth will be investigated. [ABSTRACT FROM PUBLISHER]

A 1.5–3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency range and small intrinsic delay. The inverter-based fine delay line is controlled by an XOR-based up/down counter with dead-zone free phase detector to overcome the dead-zone problem of conventional phase detectors. The D-type flip-flops in the phase detector are modified to detect sub-ps level delay difference between the input and output clocks, so that a delay resolution of better than 1 ps is achieved in the proposed design. The combination of both coarse and fine locking processes gives outstanding performance in terms of residual phase difference and output jitter. The overall design occupies 0.0077 mm2 area. The experimental results show that the peak-to-peak and root mean square jitters are 12 and 1.629 ps at 3.3 GHz, respectively, while the input jitter is 2.6 ps peak-to-peak and 612 fs rms. [ABSTRACT FROM PUBLISHER]

Based on multi-carrier transmission and multi-level chaos shift keying modulation, a novel multi-carrier chaos shift keying (MC-CSK) modulation system is proposed and designed in this paper. The new system adopts multiple subcarriers, on which all chaotic basis signals along with multiple data-bearing signals are transmitted simultaneously. The data-bearing signals and their references, though sharing the same subcarriers, are separated by I/Q channels. As a consequence, the MC-CSK system can achieve higher bit rate and better spectral efficiency compared with the MC-DCSK system. It can also dispense with chaos synchronization and threshold shifting that are required in conventional CSK systems, and achieve a delay-line-free design in both transmitters and receivers. Also, the performance of the proposed system is further improved by normalizing all chaotic basis signals and making them strictly orthogonal using the Gram-Schmidt algorithm. Moreover, the bit error rates (BERs) of the MC-CSK system over additive white Gaussian noise and multipath Rayleigh fading channels are derived. Finally, simulations are performed under different channel conditions and the effects of system parameters on the BER performance are evaluated. Both analytical and simulation results confirm that the MC-CSK system outperforms differential CSK (DCSK) and MC-DCSK systems in BER performance, except a rare case when the number of subcarriers is very small. [ABSTRACT FROM PUBLISHER]

Thanks to the high flexibility in matching the channel frequency response and the compatibility with simple adaptation techniques, Finite Impulse Response (FIR) filters enhance the equalization performances of high-speed wireline receivers. This paper presents a 25-Gb/s FIR equalizer in 28-nm CMOS. The impact of filter noise and distortion, crucial aspects for an analog implementation, is discussed. A thorough system analysis, aimed at deriving the specifications for circuits design, suggests four taps, with a tap-to-tap delay in the range 0.5–1 UI, as optimal compromise among complexity (hence power dissipation) and equalization performances. To keep high SNR, a new all-pass stage is proposed to realize a delay line suitable for high-speed operation while being able to accommodate large input signal amplitude. Measurements are shown at 25 Gb/s for both Non Return to Zero (NRZ) and Pulse Amplitude Modulation (PAM)-4 signals. With a core power dissipation of 25 mW from 1-V supply, the proposed FIR filter recovers 20- and 9-dB channel loss for NRZ and PAM-4, respectively, with horizontal eye openings of 50% and 30%. Compared with the previously reported FIR filters for wireline links at comparable speed, the proposed realization achieves excellent equalization performance with the best power efficiency of 1 mW/Gb/s. [ABSTRACT FROM AUTHOR]

A digital class-D amplifier (CDA) converts an audio digital stream into sound directly and power-efficiently. It first encodes the pulse-code-modulated audio input into a digital pulse-width-modulated (PWM) signal. It needs a digital-to-pulse converter (DPC) to translate this digital PWM signal into a series of analog binary pulses accurately. We report a 5-3 segmented DPC that includes both a counter and a delay line for pulse width conversion. The timing skews along the delay line are detected using a zero-crossing detection scheme and corrected in the digital domain. This calibration can operate continuously in the background. A digital CDA prototype was fabricated using a 65-nm CMOS technology. It includes the aforementioned PWM modulator and DPC. It also integrated an open-loop switching driver to deliver the DPC’s output to a speaker. This digital CDA consumes 875~ \mu \text W under a 1-V supply when the input is zero and no output power is transferred to the external load. It can deliver 13.3 mW to a 32~ \Omega resistive load in the H-bridge topology with 89% power efficiency. For a 1-kHz sine-wave input, it achieves 95 dBA dynamic range, 93.6 dBA peak SNR, 86.4 dBA peak SNDR, and 0.006% THD at -2-dBFS input level. The core area of the chip is 0.87\times 0.5\,\,\text mm^2 . [ABSTRACT FROM AUTHOR]

This paper describes a power and area-efficient forwarded-clock (FC) receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a delay-locked loop (DLL) based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by half. The proposed FC receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.025 mm2. At a data rate of 12.5 Gb/s, the proposed FC receiver exhibits an energy efficiency of 0.36 pJ/bit, and tolerates 1.4-\textUI\mathrm{pp} sinusoidal jitter of 300 MHz. [ABSTRACT FROM AUTHOR]

A novel non-coherent multi-level differential chaos shift keying (DCSK) modulation scheme is proposed in this paper. This new scheme is based on both the transmitted-reference technique and M-ary orthogonal modulation, where each data-bearing signal is chosen from a set of orthogonal chaotic wavelets constructed by a reference signal. Thanks to this signaling design, the new scheme can achieve a higher attainable data rate, lower energy loss in reference transmission, increased bandwidth efficiency, better data security and better bit error rate (BER) performance as compared to the conventional DCSK. Unlike other DCSK-based systems that separate the reference and data-bearing signals using the TDMA scheme, this new system employs I/Q channels to send these two signals in a parallel and simultaneous manner, making the system easily extendable to multi-carriers. This transmission mechanism not only can further increase data rate but also can remove all radio frequency delay lines from detectors. Analytical BER expressions of the proposed system are derived for both additive white Gaussian noise (AWGN) and multipath Rayleigh fading channels. Relevant simulation results are given and compared to non-coherent binary/M-ary DCSK systems. In addition, the impacts of various system parameters on noise performance are discussed. Both theoretical analysis and simulation results confirm the promising benefits of the new design. [ABSTRACT FROM PUBLISHER]

A time-to-digital (TDC) converter based on cyclic interpolators has been designed. The TDC is designed to be used in a pulsed time-of-flight laser radar, where a long measurement range is required. The TDC's two interpolators provide a picosecond level resolution, which is combined with a main reference clock counter to give a measurement range of 327 \mus. The interpolators measure time intervals with a switched-frequency ring oscillator. The frequency switching is used as a mechanism to amplify the quantization error in the cyclic interpolator. A digital calibration scheme is used for radix extraction. The interpolators' worst case INL is \pm4.5 ps. Due to the interpolator's INL, the TDC's RMS precision is about 4.2 ps, while the worst and best case single-shot precisions are 5.5 ps and 1.7 ps, respectively. The overall accuracy of the TDC is better than 5 ps in a temperature range of -30 C to 70 C. The TDC is designed in 0.35 \mum CMOS technology and consumes 80 mW at 0.8 MHz measurement rate. [ABSTRACT FROM AUTHOR]

This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. A 256-bit shift register using pulsed latches was fabricated using a 0.18 \mum CMOS process with VDD=1.8V. The core area is 6600\ \mum^2. The power consumption is 1.2 mW at a 100 MHz clock frequency. The proposed shift register saves 37% area and 44% power compared to the conventional shift register with flip-flops. [ABSTRACT FROM AUTHOR]

Traditional all-digital delay-locked loops (ADDLLs) have a long control loop, and false skew compensation may occur due to late code adjustment. To avoid this problem, the ADDLLs either simply sacrifice the maximum operating frequency or adopt a lower code adjustment rate to achieve a higher maximum operating frequency. However, lowering the code adjustment rate not only increases the number of the locking cycles but also results in large output jitter because the clock skew induced by run-time variations cannot be compensated in time. This paper presents a 55 nm 1.0 V 0.1-to-2.5 GHz ADDLL, which is constructed on a previously proposed half-delay-line skew-compensation circuit with several new circuit design techniques developed to achieve low jitter, small area, low power, fast lock-in, and high PVT- variation tolerance across a large operating frequency range. The key design feature is a ping-pong phase maintenance scheme that allows the code adjustment to be performed in time in each clock cycle, even for gigahertz operations. The measurement results show that the ADDLL achieves a peak-to-peak (p-p) jitter of 3 ps with 1.96 mW power consumption and 8 lock-in cycles when operated at 2.5 GHz. [ABSTRACT FROM AUTHOR]

This paper presents several novel low-power low-distortion \Delta\Sigma modulator topologies with shifted loop delays. Both single-sampled and double-sampled modulators are discussed. The proposed architectures can relax the critical timing for quantization and for dynamic element matching. A delay-free integrator in the last stage is used to perform the active summation, hence eliminating the active adder. The reduced input swing of the last integrator relaxes the OTA's requirements. The proposed topology simplifies the feed-forward paths, and saves power consumption and capacitor area. Noise-coupled technique can also be utilized to enhance the noise shaping. To verify the effect of the proposed topology, single- and double-sampled third-order \Delta\Sigma modulators with and without noise coupling were analyzed and simulated. [ABSTRACT FROM AUTHOR]

This paper presents the analysis and design of a tunable CMOS delay gate with improved matching properties as compared with the commonly used “current starved inverter” (CSI). The main difference between these structures lies in the location of the current limiting transistor on the inverter's output rather than on the side of the power rail. This improves the dynamic performance of the proposed “output split inverter” (OSI) circuit reducing the influence of the MOS transistor mismatch on the generated delay time variability. A test chip including two arrays consisting of 512 16-stage delay lines employing the CSI and OSI gates has been designed and fabricated in a standard 90 nm CMOS technology. The experimental results show that the proposed OSI circuit is about 10–50% more accurate than the conventional current starved inverter with no penalty in terms of the increased area, power consumption or complexity. Applications of the proposed circuit are in the design of time-to-digital converters (TDCs), delay locked loops, readout circuits for particle detection and time-based asynchronous computation systems. [ABSTRACT FROM AUTHOR]

This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space architecture. The TDC is implemented using a 0.13-\mu\ m CMOS process. The measurement result shows a dynamic range with an 11-bit 6.98-ps resolution, an integrated nonlinearity of \pm1.5 LSB, a power consumption of 328.8 \mu\ W, and a die area of 0.28 \ mm^2. [ABSTRACT FROM AUTHOR]

The paper is concerned with the problem of input-to-state stability (ISS) for nonlinear delay systems with large delay periods (LDP). The concepts of the length rate of LDP and the frequency of LDP are introduced. First the considered system is converted into a switched delay system which may include an unstable subsystem. Then based on a piecewise Lyapunov functional, the ISS properties of the systems are developed under the constraints of the length rate and the frequency of LDP. ISS for a special kind of nonlinear delay systems is also considered and the conditions of nonlinear matrix inequalities (NLMIs) are proposed to guarantee the ISS properties of such a system. A numerical example and an example of a series DC motor are given to show the effectiveness of the proposed methods. [ABSTRACT FROM AUTHOR]

Wide-range level shifters play critical roles in ultra- low-voltage circuits and systems. Although state-of-the-art level shifters can convert a subthreshold voltage to the standard supply voltage, they may have limited operating ranges, which restrict the flexibility of dynamic voltage scaling. Therefore, this paper presents a novel level shifter, of which the operating range is from a deep subthreshold voltage to the standard supply voltage and includes upward and downward level conversion. The proposed level shifter is a hybrid structure comprising a modified Wilson current mirror and generic CMOS logic gates. The simulation and measurement results were verified using a 65-nm technology. The minimal operating voltage of the proposed level shifter was less than 200 mV based on the measurement results. In addition to the operating range, the delay, power consumption, and duty cycle of the proposed level shifter were designed for practical applications. [ABSTRACT FROM AUTHOR]

Strain engineering for performance enhancement is an integral part of a state-of-the-art CMOS process flow. However, use of stressors makes the performance of CMOS devices layout dependent. Performance variability arising due to the use of stressor materials is often referred to as Layout Dependent Effect (LDE) variability. The existing delay models do not take LDE into consideration and, therefore, results into unaccounted change in performance and degraded design robustness. In this paper we propose an analytical delay model for Inverter, 2-input NAND and NOR gates while considering LDE variability due to the use of strain engineered devices. We compare our derived model with TCAD calibrated HSPICE simulation results and observe that our model estimates delay well for varying transistor sizes, load capacitances and input signal transition times. [ABSTRACT FROM AUTHOR]

This paper analyzes the spurs due to delay line (DL) buffer mismatch errors and phase quantization errors in a digital-to-time conversion (DTC) direct frequency synthesizer. Applying the time/frequency axis scaling property of the Discrete Fourier Transform (DFT) to a close approximation of the general case of both buffer error and quantization error spurs, it is shown that the spur spectra for all possible output frequencies can be divided into a very small number of classes. All the spectra within a class are scaled and systematically re-arranged versions of each other. For a DTC with a phase accumulator with I integer and M fractional bits, this result simplifies the number of spectra from 2^(I+M) to M. The condition that allows separation of the buffer errors spur locations from the quantization error spur location is derived. Spurs predicted based on the analysis match closely with actual measurements performed on a 90 nm CMOS DTC synthesizer. The spur analysis also applies to the flying adder (FA) synthesizer. [ABSTRACT FROM PUBLISHER]

This paper presents a novel die-to-die clock synchronization method that is independent of the inter-die wire delay. Through a 2-Phase All-Digital Delay Locked Loop (2P-DLL) and a Dual Locking Mechanism (DLM), this method can be used to maintain a global clock signal between two dies in a 3-D IC, and thereby enabling the synchronous 3-D IC design methodology. Unlike previous designs, ours does not need to replicate the delay of the inter-die clock wire. This property can make our scheme more adaptive to various 3-D technologies and more robust to PVT variation. Such a method has several other benefits. For example, it can accommodate the ever-increasing process variation easily through its silicon tracking ability. Simulation results indicate that it can support clock signals running up to 2.8 GHz. Silicon measurements of a test chip in a 90 nm CMOS technology show that the phase error can be locked constantly to less than 9.6 ps at a clock frequency of 600 MHz, with a peak-to-peak jitter of 9.778 ps and a power consumption of only 1.8 mW. [ABSTRACT FROM PUBLISHER]

This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm^2 in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 psrms and the data eye opening is 0.613UI. [ABSTRACT FROM AUTHOR]

An all-digital 90^\circ phase shift delay lock loop (DLL) is presented, which is robust against the delay mismatch caused by process variation. Each of the four 90^\circ phase shift blocks accurately aligns its output to a 90^\circ shifted phase using its own ring oscillator and locking delay code. It is analytically proved that the phase shift accuracy of the proposed 90^\circ phase shift block is always higher than that of the conventional all-digital 90^\circ phase shift DLL. The harmonic locking problem is prevented by a ring oscillator and a counter. An area-efficient binary-to-thermometer converter is proposed to reduce the area overhead caused by the delay-line control logic. A fast operating frequency with a finer resolution is achieved through the fine delay range selector and the resistance controlled fine delay unit. The proposed 90^\circ phase shift DLL is implemented using a 45-nm CMOS process. The phase shift accuracy errors at the 90^\circ and 270^\circ phases are 0.43^\circ and 1.01^\circ, respectively, when the maximum locking delay code difference between the four 90^\circ phase shift delay lines corresponds to \pm 9.97^\circ at 800 MHz. It proves that the DLL corrects the significant phase error caused by process variation. The power consumption is 3.3 mW at 800 MHz. [ABSTRACT FROM AUTHOR]

Recently, an ultra-wideband (UWB) system with frequency-modulated differential chaos shift keying (FM-DCSK) modulation has attracted increasing interest for its many distinctive superiorities over its conventional counterparts, especially in low-rate and low-power wireless personal area network (WPAN) applications. However, some of its drawbacks, such as low energy efficiency, complex implementation and weak multiaccess capacity, have also been noticed, which restrict its further acceptance and applications. To overcome these problems, an architecture, named single-input and multiple-output (SIMO) FM-DCSK UWB system, is introduced in this paper. With chaotic transmitted signals based on a high-order Walsh function and multiple antennas diversity reception, this paper demonstrates the superiorities of the new system in bit error rate (BER) performance as well as in moderation complexity. Furthermore, by transmitting chaotic pulse cluster signals, an improved emission signal structure of the SIMO FM-DCSK UWB system is proposed so as to overcome the delay line implementation constraints and to further enhance the BER performance. Based on this new signal format, a method of combining time division and Walsh function division is introduced into the existing Walsh function division scheme, thereby resolving the inherent obstacle in user capability which was known to be limited by the order of the Walsh function. [ABSTRACT FROM PUBLISHER]

In this paper the asymptotic limits of negative group delay (NGD) phenomena in multi-stage RLC resonator-based circuits are discussed. A NGD-bandwidth-product limit is derived as a function of the number of stages and the out-of-band gain, which is independent of the circuit topology and can include active gain compensation. The limit is verified experimentally at microwave frequencies using a gain-compensated NGD circuit employing a parallel RLC resonator in the feedback path of a high-frequency op-amp. It is shown that, in the asymptotic limit, the NGD-bandwidth-product is proportional to the square root of the number of stages, and also to the square root of the logarithm of the out-of-band gain. The relation between the time-domain transient amplitude and the out-of-band gain is analyzed for finite-duration modulated signals, indicating an exponential increase in transient amplitudes with the square of NGD. Analysis shows that any attempt to increase the NGD of a finite-duration modulating waveform, by cascading more stages, is thwarted by the transients. [ABSTRACT FROM PUBLISHER]

This paper presents an automatic within-pair skew compensator for high-speed differential data transmission. A wide-bandwidth data delay line is proposed to provide adjustable delay for data signals. Also presented is an on-chip within-pair skew detection circuit to detect skew between the differential data signals for automatic close-loop skew compensation. A within-pair skew compensator prototype for 5 Gb/s data was fabricated in 0.13 \mu\m CMOS. Measurement results show that the within-pair skew compensator can automatically compensate for within-pair skew of \pm200 ps (\pm1 unit interval). It consumes 20.4 mW from 1.2 V supply and occupies 0.015 \mm^2 die area. [ABSTRACT FROM PUBLISHER]

This paper presents a time-to-digital converter (TDC) using a fractional difference conversion scheme. Two delay-locked loops (DLLs) provide negative feedbacks to stabilize the delays against process and ambient variations. In addition, by adopting the principles of cyclic Vernier delay line, the resolution is improved while dynamic range is significantly increased. The proposed TDC architecture is competitive in terms of resolution and power compared to the other DLL/PLL stabilized TDCs. The TDC designed and fabricated in 0.18 \mu \m CMOS process achieves a 14.6 ps resolution as well as a 50 ns dynamic range, while consuming 6.4 mW power. [ABSTRACT FROM PUBLISHER]

Soft errors are becoming an increasingly important issue for circuit reliability. Traditional techniques to protect against soft errors, like triple modular redundancy (TMR), have a large cost in terms of area and power. This has motivated the development of specific protection techniques for various types of circuits. In this paper, techniques to protect adaptive filters are presented, which provide reasonable reliability with reduced cost and power consumption. An adaptive equalizer case study is used to discuss and evaluate the proposed techniques in terms of both protection and cost. [ABSTRACT FROM PUBLISHER]

A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and, the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. The coarse block consists of two ladder-shaped coarse delay chains. The delay of the first one is an odd multiple of an inverter delay and that of the second one is an even multiple. An interpolation operation is performed at the second coarse delay chain, which reduces both the resolution of the coarse delay block and the delay range of the fine block to half. This increases the maximum output frequency of the DCO while it maintains the wide frequency range. The ADPLL with the proposed DCO was fabricated in a 0.18 μm CMOS process with the active area of 0.32 mm2. The measured output frequency of the ADPLL ranges from 33 to 1040 MHz at the supply of 1.8 V. The measured rms and peak-to-peak jitters are 13.8 Ps and 86.7 PS, respectively, at the output frequency of 950 MHz. The power consumption is 15.7 mW. [ABSTRACT FROM AUTHOR]

This paper deals with fault-tolerant master-slave synchronization for Lur'e systems using time-delay feedback control. Taking a general nature of fault in the master system into account, a new synchronization scheme, namely, fault-tolerant master-slave synchronization, is proposed, by which the master-slave synchronization can be achieved no matter if the fault occurs or not. By making use of an observer-based fault estimator and a modified time-delay feedback controller, the fault-tolerant master-slave synchronization is formulated so as to discuss the global asymptotic stability of the error system and the bound of energy gain from fault to state and fault estimation error vectors. Some new delay-dependent criteria are derived to analyze the synchronization error system, and based on the analysis results, a sufficient condition on the existence of such a master-slave synchronization scheme and a solution to the controller and fault-estimator gain matrices are obtained in terms of linear matrix inequalities. Finally, a Chua's circuit is used to illustrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

We propose an analytical closed-form gate-interconnect interdependent delay model that accounts for the dynamic behavior of signal slope across different regions of operation. In the presence of interconnects, the gate driver influences the input slope of the driven wire affecting the interconnect delay, and the driven wire acts as a parasitic load to the driver affecting the gate delay. Hence, it is essential to consider their interdependence for an accurate estimation of the circuit delay. The proposed model converts a signal slope into its effective fan-out for a simple yet accurate delay estimation. Simulations show that, for ISCAS benchmark circuits, our framework exhibits an error of < 5.3% at each stage and < 4.3% for the path delay with a speedup of three orders of magnitude over HSPICE at the 130-nm technology node. Two test chips have been fabricated in 90- and 65-nm CMOS technologies to verify the effectiveness of the proposed model. Measured results show that, for a wide range of interconnect lengths (2000 and 1400 μm) and geometries, the proposed model predicts the circuit delay with an error of 5.7% at a supply voltage of Vdd = 1.2 V and 4.8% at Vdd = 0.3 V. [ABSTRACT FROM AUTHOR]

In the past few years, hybrid stochastic retarded systems (also known as stochastic retarded systems with Markovian switching), including hybrid stochastic delay systems, have been intensively studied. Among the key results, Mao et al proposed the Razumikhin-type theorem on exponential stability of stochastic functional differential equations with Markovian switching and its application to hybrid stochastic delay interval systems. However, the importance of general asymptotic stability has not been considered. This paper is to study Razumikhin-type theorems on general p-th moment asymptotic stability of hybrid stochastic retarded systems. The proposed theorems apply to complex systems including some cases when the existing results cannot be used. [ABSTRACT FROM AUTHOR]

MOS-transistor-based current-mode logic (CML). type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional RC delay model which is based on ideal step input assumption fails to track the delay of MCML circuits with errors as high as 40% when a design is optimized for high-speed. In this paper, a comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high-speed and low-swing applications by including the input slope effect (ISE) into the conventional RC delay model. Furthermore, the proposed model is extended to multilevel complex logic gates without losing the general RC delay model format. Theoretical results are compared with Spice simulations in a 0.13-μm CMOS technology. Results show that the error in delay of the proposed model is less than 20% for all practical designs. The proposed model is still sufficiently tractable to be use in back-of-envelope calculations that achieve close-to-optimum solutions without running extensive parametric simulations. In addition to the achieved accuracy and preserved simplicity, the proposed model enhances the intuitive understanding of MCML gates that simple RC delay model fails to provide. [ABSTRACT FROM AUTHOR]

Our previous work, has shown that coefficient symmetry can be exploited for designing high-accuracy and low-complexity even-order variable fractional-delay (VFD) filters. The objectives of this paper are twofold; One is to derive a coefficient symmetry for odd-order VFD filters, and then formulate a closed-form weighted-least-squares (WLS) design. Exploiting the coefficient symmetry along with different-order subfilters reduces the number of independent VFD filter coefficients by more than 50%, and thus reduces the hardware cost and the number of multipliers by more than 50%. Another objective is to briefly derive the maximally flat (MF) VFD filters from Nth-degree polynomial interpolation, and then present two kinds of transformation matrices for transforming causal odd-order MF VFD filters into symmetric structures such that the filter complexity can be reduced. As a result, both WLS and MF VFD filters can be implemented as the Farrow structure with significantly reduced complexity, which facilitates high-speed VFD filtering. Various examples are given to illustrate the effectiveness of the symmetry-based design and implementations. [ABSTRACT FROM AUTHOR]

We present transmission-line-based finite-impulse response (FIR) filters built using singly terminated delay lines and compare their performance with respect to circuit nonidealities. New topologies for FIR filters called bi-transversal structures, which are electrically equivalent to transversal equalizers, are introduced. We show that resistive shunt compensation of transmission lines is a useful technique that results in dramatic improvements in the performance of singly terminated transversal filters, making them excellent candidates for LMS algorithm based adaptive equalization at gigabit speeds. [ABSTRACT FROM AUTHOR]