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In-memory computing (IMC) is an effective solution for energy-efficient artificial intelligence applications. Analog IMC amortizes the power consumption of multiple sensing amplifiers with an analog-to-digital converter (ADC) and simultaneously completes the calculation of multi-line data with a high parallelism degree. Based on a universal one-transistor one-magnetic tunnel junction (MTJ) spin transfer torque magnetic RAM (STT-MRAM) cell, this paper demonstrates a novel tunneling magnetoresistance (TMR) ratio magnifying method to realize analog IMC. Previous concerns including low TMR ratio and analog calculation nonlinearity are addressed using device-circuit interaction. The TMR is magnified $7500\times $ using a latch structure in combination with the device. Peripheral circuits are minimally modified to enable in-memory matrix-vector multiplication. A current mirror with a feedback structure is implemented to enhance analog computing linearity and calculation accuracy. The proposed design maximumly supports 1024 2-bit input and 1-bit weight multiply-and-accumulate (MAC) computations simultaneously. The proposal is simulated using the 28-nm CMOS process and MTJ compact model. The integral nonlinearity is reduced by 57.6% compared with the conventional structure. 9.47-25.4 TOPS/W is realized with 2-bit input, 1-bit weight, and 4-bit output convolution neural network (CNN). [ABSTRACT FROM AUTHOR]

Magnetic tunnel junction (MTJ) with non-volatility, and near-zero leakage power features are believed to be the most prominent candidates for CMOS substitution. Logic-in-memory reduces the memory wall challenge and takes advantage of these features, but still has the challenge of writing to a magnetic device with regard to power consumption and device failure. Considering these challenges, we propose new designs in the approximate computing approach for magnetic device-based primitives. This paper proposes several power- and/or delay-efficient configurable Logic-in-Memory for Imprecise Tolerant Applications (LIMITA) based on spin transfer torque (STT) and STT-assisted voltage control magnetic anisotropy (VCMA) magnetic devices. Image processing is one of the most widely used imprecise tolerant applications with a high computational volume. Therefore, we map LIMITA with several approximation boundaries in Sobel, Sharpening, and Smoothing algorithms. To evaluate LIMITA at circuit and application levels, we did extensive simulations in HSPICE and MATLAB, respectively. Compared to the state-of-the-art works, the exact design of LIMITA improves the number of transistors in the logic tree up to 66% with 12% power overhead due to its configurability feature. In addition, in comparison with approximate primitives, LIMITA- $\text{F}_{\mathrm {i}}$ improves delay, power consumption, and the number of transistors by $4.5\times$ , $71.5\times$ , and $2\times$ respectively. [ABSTRACT FROM AUTHOR]

Continued scaling of Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology is slowing down due to physical limitations, while the static power of CMOS based memory is increasing as the transistors shrink. As an alternative memory technology, the Spin Transfer Torque Magnetic RAM (STT-MRAM) remains limited to low-level, high-capacity caches because of the high write power and still unsatisfactory write access speed. Spin Orbit Torque MRAM (SOT-MRAM), which has been proposed to tackle this issue, still faces some issues including the poor read margin due to low Tunnel Magnetoresistance (TMR) and undesirable use of a magnetic field for deterministic switching. This article proposes a novel 3T2SOT (three Transistors and two SOT magnetic tunnel junctions) based field-free MRAM, which can achieve higher read speed and reliability by adopting a self-referencing scheme, and lower write power benefiting from an advanced switching mechanism. Detailed circuit-level simulation results show that the write latency of the proposed design can be reduced to $0.3~ns$ , and the write power is two orders of magnitude lower than STT-MRAM. Additionally, compared to SRAM, for 8 MB cache memory, the read speed of 3T2SOT MRAM is enhanced by 38.9%. Compared to conventional 2T1SOT MRAM, the read performance is similar and the read error rate is dropped by 96.1% at least. [ABSTRACT FROM AUTHOR]

While spintronic memories, for example, spin transfer torque magnetic random access memory (STT-MRAM), have shown huge potential for building next-generation memory due to their attractive characteristics, the relatively large write latency and deficient read mechanism preclude their further application for emerging concepts, such as in-memory-processing and neuromorphic computing. A toggle spin torque (TST) MRAM combining STT and spin orbit torque (SOT) has recently been proposed to alleviate the write issue. However, the sensing featuring a good balance between the reliability and speed has not been addressed. In this paper, we propose a self-matching complementary-reference (SMCR) sensing scheme, which provides not only a maximum sensing margin (SM) but also a high-speed read operation. Through applying it in the TST-MRAM, advantageous performance in terms of both write and read processes can be realized. To validate the functionality of our proposal, we design and evaluate an 8Kb TST-MRAM array, in which a read delay of 1 ns and a read bit error rate (BER) of $1.02\times 10^{-13}$ are achieved. Moreover, when being operated at 0.8 V supply voltage, it can reduce the read access energy by 7.5% and 20%, compared with conventional voltage sensing and dynamic reference sensing schemes, respectively. [ABSTRACT FROM AUTHOR]

A hybrid device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. A hierarchical top-down design approach is used to develop a hybrid spin/charge based FPGA (HSC-FPGA) starting from the configurable logic block (CLB) and slice structures down to LUT circuits and the corresponding device fabrication challenges. Circuit-level simulations indicate at least 40% and 83% read and standby power reduction, respectively, for MRAM-LUTs compared to SRAM-LUTs. However, MRAM-LUTs using spin transfer torque (STT) switching approach suffers from significant write energy consumption. Therefore, we have designed spin Hall effect (SHE)-assisted MRAM-LUTs realizing more than 67% and 61% reduction in reconfiguration energy and area consumption, respectively. Fabric-level simulations exhibit that HSC-FPGA achieves 70% and 30% reductions in standby and read power, respectively, compared to SRAM-based FPGAs for various ISCAS-89 and ITC-99 benchmark circuits. Finally, a multi-level method spanning device-sizing, circuit modular-redundancy, and component-level reconfiguration is developed to increase the process variation resiliency of the MRAM-LUTs. The power consumption and area utilization are analyzed to formulate tradeoffs resulting in recommendations toward future multi-device-based reconfigurable fabrics. [ABSTRACT FROM AUTHOR]

In this paper, we discuss the potential foundry announced integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FDSOI). The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next-generation voltage-controlled magnetic anisotropy MTJ are separately integrated into a 28-nm FDSOI process as the MRAM or magnetoelectric random access memory (MeRAM)-on-FDSOI integration. Micromagnetic and electrical simulations are used to evaluate the performance of hybrid circuits. Circuit-level design strategies are explored that use FDSOI leverage and spin-device characteristic to realize writing and sensing power-delay efficiency, robust, and reliable performance in the one-transistor one-MTJ MRAM/MeRAM bit-cell and sensing circuits. Reliability issues are discussed. Process variation and aging resilience strategies, e.g., step-wise back-bias, flip-well re-configuration, and write assist, are proposed to address failure and aging degradation in the MRAM/MeRAM-on-FDSOI integration. A qualitative summary demonstrates that the MRAM/MeRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration. [ABSTRACT FROM AUTHOR]

This paper introduces the concept of time-based sensing (TBS) for bitcell read in spin transfer torque magnetic RAMs arrays. The TBS scheme converts the bitline voltage into time, then the sense amplifier discriminates the two bitcell levels in the time domain. The TBS scheme substantially improves the read yield compared to conventional voltage sensing (CVS). As further advantage, TBS requires no analog reference generation and distribution by leveraging the implicit timing reference set by the gate delay in the sense amplifier. Monte Carlo simulations in 65 nm show that the proposed TBS improves the read bit error rate (BER) by two-three orders of magnitude, compared to CVS. This is achieved at the cost of less than 1% area penalty and 13–14% performance degradation, and insignificant (2%) energy penalty when designed at iso-area (minimum delay). Compared to other sensing schemes at iso-BER, the proposed TBS scheme achieves a more favorable area-robustness-energy-performance tradeoff. [ABSTRACT FROM AUTHOR]

Energy becomes an inevitable challenge when using a large die-stacking dynamic random access memory (DRAM) cache. Although emerging spin-transfer-torque-RAM (STT-RAM) technology can efficiently reduce the static energy of large cache, it cannot completely replace DRAM cache due to the high write energy of STT-RAM. Recently, researchers have observed that there are many redundant bits written in the row buffer and futile bits written back to STT-RAM cells, which do not change the cells’ value but still cost high write energy. In this paper, we first design a large hybrid cache architecture with the DRAM region and the STT-RAM region to reduce the high static energy of DRAM cache. The selective write back to row buffer and selective write back to cell array optimizations are proposed to reduce high write energy of the STT-RAM region by removing the unnecessary bit-writes. Furthermore, we propose reuse distance-oriented data movement to reduce write operations in the STT-RAM region. Finally, we propose a novel tag design for the hybrid cache by moving all tag arrays to the STT-RAM region. The SPEC CPU2006 benchmarks show an average 28.3% energy reduction and 6.7% performance improvement for the write optimizations and 7.3% energy savings and 27.5% instructions per cycle speedups for the proposed tag design. [ABSTRACT FROM AUTHOR]

As process technology downscales, read reliability has become a critical barrier for spin transfer torque magnetic random access memory (STT-MRAM), owing to the increasing process-temperature-voltage (PVT) variations, decreasing critical switching current of magnetic tunnel junction (MTJ) and supply voltage. To deal with the read reliability challenge, we propose herein a dynamic dual-reference sensing (DDRS) scheme. The key features of the proposed DDRS scheme include: (a) two reference signals, generated by two reference cells with the same structures as those of the data cells, are provided to the sensing circuit; (b) the reference signals are adaptively dynamical depending on the content stored in the target data cell; (c) two output signals are obtained to decide the sensing result, adding redundancy for supporting self-error detection (SED) capability. The proposed DDRS scheme can achieve a great improvement in sensing margin (SM) and bit error rate (BER), in comparison with conventional sensing schemes. In addition, no regularity problems exist in the proposed DDRS scheme, as the reference cells maintain exactly the same structures as those of the data cells. Our simulation results show that the proposed DDRS scheme can achieve a $\sim 7\times $ increase in average SM, and a ~ 70% reduction in average BER, compared with conventional sensing schemes. [ABSTRACT FROM PUBLISHER]

Spin-transfer torque (STT) mechanisms in vertical and lateral spin valves and magnetization reversal/domain wall motion with spin-orbit torque (SOT) have opened up new possibilities of efficiently mimicking “neural” and “synaptic” functionalities with much lower area and energy consumption compared to CMOS implementations. In this paper, we review various STT/SOT devices that can provide a compact and area-efficient implementation of artificial neurons and synapses. We provide a device-circuit-system perspective and envision design of an All-Spin neuromorphic processor (with different degrees of bio-fidelity) that can be potentially appealing for ultra-low power cognitive applications. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel boosted voltage sensing (BVS) scheme that substantially improves the resiliency of STT-MRAMs against variations in read accesses based on bitline voltage sensing, and on a wide range of voltages. The BVS scheme mitigates the impact of variations in the senseamp and the reference voltage generation, and is based on switched-capacitor voltage boosters. The related area-performance-energy-resiliency tradeoff is explored, and design guidelines are derived to improve the read margin at minimum overhead. [ABSTRACT FROM PUBLISHER]

As technology scales down, the sensing margin of spin-transfer-torque random access memory is significantly degraded because of the increased process variation and decreased supply voltage. The sensing current, which is limited to prevent read disturbance, further degrades the sensing margin. To improve the sensing margin, various reference schemes have been proposed. However, it is essential to be selective because the read stability, write ability, and array efficiency are very different according to the reference schemes. This paper presents the study of a variety of reference schemes and outlines five requirements for an optimized reference scheme as follows: 1) no parasitic mismatch, 2) no regularity problem, 3) no read disturbance, 4) no write-current degradation, and 5) small area overhead. A novel reference scheme that satisfies all the requirements for the optimized reference scheme is proposed using four 1T1MTJ cells and a reference word line structure with the same parasitic scheme. [ABSTRACT FROM AUTHOR]

The high leakage power due to process nodes scaling down has been one of the critical issues in CMOS circuits, especially the sleep power critical systems. The conventional retention CMOS register based approaches cannot fully address the high standby energy issue in long time standby systems. The recent non-volatile Flip-Flop (nvFF) based approaches may achieve zero sleep power consumption, but still face the challenges of high saving power and area overhead, and low data reliability. This paper presents a new resistive Non-Volatile Memory (NVM) based circuit architecture with zero leakage power dissipation. It stores the states of the registers in the localized spin-torque-transfer magnetic random access memory (STT-MRAM) array through scan chains, which has reduced by more than 20% sleep energy than conventional nvFF schemes, and saved by more than 99.8% sleep energy compared to the retention CMOS register based approaches when the sleep time is longer than 1 s. Moreover, the proposed pipelined quad-phase saving scheme maximizes the saving speed, while reduces the peak saving current. [ABSTRACT FROM AUTHOR]

Accurate modeling of magnetic tunnel junction (MTJ) is critical for design of memories such as spin-transfer-torque magnetoresistive random access memory (STT-MRAM) and spin logic circuits such as spin flip flops. This paper reviews several static and dynamic models for the MTJ and compares them for their capabilities and limitations. Furthermore, a Verilog-A model is developed to predict dynamic characteristics of the MTJ. These models are used in simulating a prototype circuit to illustrate their strengths and weaknesses. [ABSTRACT FROM AUTHOR]

Advanced computing systems suffer from high static power due to the rapidly rising leakage currents in deep sub-micron MOS technologies. Fast access non-volatile memories (NVM) are under intense investigation to be integrated in Flip-Flops or computing memories to allow system power-off in standby state and save power. Spin Transfer Torque MRAM (STT-MRAM) is considered the most promising NVM to address this issue thanks to its high speed, low power, and infinite endurance. However, one of the disadvantages of STT-MRAM for the computing purpose is its relatively high write energy to build up Magnetic Flip-Flop (MFF). In this paper, we propose a power-efficient MFF design architecture to address this challenge based on the combination of checkpointing operation, power gating and self-enable mechanisms. Multi non-volatile storages can be integrated locally in a conventional FF without significant area overhead benefiting from the 3-D implementation of STT-MRAM. We performed electrical simulations (i.e. transient and statistical) to validate its functional behaviors and evaluate its performance by using an accurate spice model of STT-MRAM and an industrial 40 nm CMOS design kit. The simulation results confirm its lower power consumption compared to conventional CMOS FF and the other structures. [ABSTRACT FROM AUTHOR]

Spin-based devices, in which information is carried via electron spin rather than electron charge, are potential candidates to complement CMOS technology due to the promise of non-volatility and compact implementation of logic gates. One class of such devices is all-spin logic (ASL) which is based on switching ferromagnets by spin transfer torque and conduction of spin-polarized current. Using previously developed physics-based circuit models for ASL, we develop a complete logic family for static ASL comprising of majority logic gates. We compare its performance metrics by means of circuit simulations using our Verilog-A compact models. We also show the novel implementations of sequencing elements (e.g., latch and D flip-flop) to enable clocked ASL. We also refine the models for ferromagnets to include spin relaxation inside ferromagnetic metals (FMs). [ABSTRACT FROM AUTHOR]

With the continuing scaling of MTJ, the high-speed reading of STT-RAM becomes increasingly difficult. Recently, a body-voltage sensing circuit (BVSC) has been proposed for boosting the sensing speed. This paper analyzes the effectiveness of using the reference calibration technique to compensate for the device mismatches and improve the read margin of BVSC. HSPICE simulation results show that a 2-bit reference calibration can improve the worst-case read margin in a 1-Mb memory by over 3 times. This leads to up to 30% higher yield across all process corners. In order to maintain the yield improvement even in the worst-case corner, independent calibration circuitry has to be deployed for each memory array. [ABSTRACT FROM PUBLISHER]

This paper presents a three-terminal Magnetic Tunnel Junction (MTJ) and its associated two transistor cell structure for use as a Spin Torque Transfer Magnetoresistive Random Access Memory (STT-MRAM) cell. The proposed cell is shown to have guaranteed read-disturbance immunity; during a read operation, the net torque acting on the storage cell always acts in a direction to refresh the data stored in the cell. A simulation study is then performed to compare the merits of the proposed device against a conventional 1-Transistor-1-MTJ (1T1MTJ) cell, as well as a differential 2-Transistor 2-MTJ (2T2MTJ) cell. We also investigate In-Plane Anisotropy (IPA) and Perpendicular-to-Plane Anisotropy (PPA) versions of the proposed device. Simulation results confirm that the proposed device offers disturbance-free read operation while still offering significant performance advantages over the conventional 1T1MTJ cell in terms of average access time. The proposed cell also shows superior performance to the 2T2MTJ cell, particularly when the cells are targeted for read-mostly applications. [ABSTRACT FROM PUBLISHER]

Dipolar magnetic coupling between single layer nanomagnets is used in nanomagnetic logic (NML). Apart from writing and reading, nanomagnets are also clocked using external magnetic fields generated by current carrying wires. The related current ranges in mA and consumes large power. Also, the fields cannot sharply terminate at boundaries between nanomagnets that are required to be in different clock zones. The above concerns motivated us to look into alternate magnetic devices to realize magnetic logic. We therefore suggested miltilayer magnetic tunnel junctions (MTJs) for logic. We have observed that MTJ free layers can interact with their neighbors through magnetic coupling. In this paper we have proposed use of this coupling for effective logic computation. MTJs are also CMOS friendly, a property that we used to write, clock and read from logic. CMOS integration also improves control over individual elements in logic. In this paper we have used these properties to present a novel CMOS-MTJ integrated architecture that: a) computes logic using magnetic coupling between MTJs and b) writes, clocks and reads from logic using spin transfer torque (STT) current that is more energy efficient. A feasibility study of this CMOS-MTJ integration in 22 nm CMOS technology node is also presented. The proposed architecture achieves an energy reduction >95% in adders and multipliers when compared to traditional designs using single layer nanomagnets. [ABSTRACT FROM PUBLISHER]