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In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interference. Moreover, by filtering the feedback signal in the discrete-time domain, the jitter robustness of the modulator is greatly improved and most importantly the slewing requirements on the OpAmps in the modulator’s loop filter are greatly relaxed up to a level that the OpAmps can be scaled down toward their ultimate noise limited power level. Furthermore, this LPSC-DAC does not suffer from the SCR-DAC’s disadvantageous trade-off between the modulator’s jitter, slewing, and anti-aliasing performance. We also show how to compensate for the extra pole of the LPSC-DAC, such that the CTSDM’s loop filter, noise- and signal-transfer function remains unchanged. As a result, this technique is completely transparent to the system level designer and established system-level design techniques for sigma delta modulators remain applicable. [ABSTRACT FROM AUTHOR]

Delta-sigma modulators spectrally shape quantization noise in discrete systems and are used extensively in communications and signal-processing systems. They are implemented using a loop-filter that processes the input and feed-back signals such that the closed loop behavior has a separate signal transfer function (STF) and noise transfer function (NTF). Loop-filter design often relies on special cases for the NTF or simplified loop-filter structures. This paper presents a method for generalized loop-filter synthesis that can implement a chosen NTF and STF independent of internal loop-filter structure or filter order. The transfer functions are formulated as polynomials of integration, $(z-1)^{-n}$ , instead of delay, $z^{-n}$ , to enable practical numerical loop-filter synthesis even for high-order and highly oversampled loop-filters. An example design shows how to use this synthesis method to design a high-order modulator that directly filters and re-modulates a direct stream digital audio signal. [ABSTRACT FROM AUTHOR]

This paper presents the analysis and design of a quadrature charge-domain down-conversion sampling mixer with embedded finite-impulse-response (FIR), infinite-impulse-response (IIR), and 4-path bandpass filters. An in-depth investigation of the principles of periodic impulse sampling, periodic windowed sampling, and periodic N-path windowed sampling is presented and their characteristics are compared. A detailed mathematical treatment of charge-domain windowed samplers with built-in sinc, FIR and IIR filters is provided. A quadrature charge-domain sampler with embedded FIR, IIR, and 4-path band-pass filters is proposed and its performance including the effect of the non-idealities of devices is investigated. The proposed design is implemented in an IBM 130 nm 1.2 V CMOS technology. Simulation results demonstrate that the proposed design is tunable over 50–250 MHz frequency range. For an 100 MHz input, the proposed design exhibits 70 dB aliasing rejection, 60 dB stop band attenuation while consuming current of 145 \muA. The performance of the proposed design is further validated using the results of on-wafer measurement of the fabricated microchip. [ABSTRACT FROM AUTHOR]

An active electronically scanned array (AESA) beamforming method that provides enhanced selectivity (interference rejection) for the same number of antennas compared to conventional delay-and-sum (DAS) beamforming is proposed. Conventional DAS 2-D transfer function is modified by introducing complex pole-manifolds based on recently proposed 2-D infinite impulse response (IIR) beam filters, at guaranteed stability. A continuous-time domain signal flow graph is proposed based on first order all-pass filters that eliminate the need of transmission line-based delays used in conventional DAS beamformers. Improved interference rejection is verified using closed-form signal processing models. For an array of 64 antennas, with desired signal direction of arrival (DOA) 10^\circ and interference DOA -60^\circ from array broadside, the proposed scheme shows an improvement in the signal-to-interference ratio (SIR) around 7 dB for the same number of antennas, compared to DAS beamforming. The improvement in interference rejection is observed for both uniform and non-uniform aperture weights in terms of side lobe performance. A feasibility study is presented on potential CMOS circuit implementation of the proposed AESA for a linear array of eight antennas and maximum operational frequency of 1 GHz. [ABSTRACT FROM AUTHOR]

In this paper, both methods of magnitude-oriented design and delay-oriented design for variable fractional-delay (VFD) infinite impulse response (IIR) filters are proposed. In the former, the objective error function is formed by including root-mean-square error function of variable frequency response and the stability error constrained function, such that the designed filters are stable. As for the second part of this paper, it is desirable to minimize the root-mean-square error of variable group-delay response while the magnitude response and stability can be preserved. Hence, except those stated above, the root-mean-square error function of variable group-delay response is further included in the objective error function. However, these induced problems are highly nonlinear, so iterative methods are proposed to overcome them. Several design examples are presented to demonstrate the features of these design methods, including concerns among VFD finite impulse response (FIR) filters, VFD allpass filters and VFD IIR filters as well as the designed results of both methods. [ABSTRACT FROM PUBLISHER]