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This paper proposes a high-performance bidirectional architecture for the quasi-comparison-free sorting algorithm. Our architecture improves the performance of the conventional unidirectional architecture by reducing the total number of sorting cycles via bidirectional sorting along with two auxiliary methods. Bidirectional sorting allows the sorting tasks to be conducted concurrently in the high- and low-index parts of our architecture. The first auxiliary method is boundary finding, which shortens the range for index searching by finding the boundaries of the range. The second auxiliary method is queue storing, which stores each useful index in a queue in advance to reduce the number of miss cycles during index searching. The performance of our architecture highly depends on the distribution of input data. For each set of input data to be sorted, five Gaussian distributions of the input data and four standard derivations for each distribution were adopted in our experiments. The results show that at the expense of some additional area cost, the number of sorting cycles and the energy consumption are significantly reduced by our method. [ABSTRACT FROM AUTHOR]

This paper presents the hardware design and implementation of 1-D median filter that uses modular architecture, which produces median results hierarchically. Different types of submodules could be applied to form a customized architecture in order to meet different constraints and requirements. Complete analysis and hardware-oriented optimization were performed to achieve the optimal configurations when the input size and data length were changed. As the data length increases, the required resources and latency increase linearly, while the maximal operation frequency is nearly independent to data length. When our filter is synthesized using 90-nm process technology, its operating frequency could achieve more than 2000 MHz and resource consumption is reduced by 23.29% when compared with the state-of-the-art design. The experimental results show that the proposed cascaded architecture is superior to existing designs in terms of maximal operating speed and resource costs. [ABSTRACT FROM PUBLISHER]

A robust distributed estimation scheme for fusion center in the presence of sensor faults via collaborative sensor fault detection (CSFD) was proposed in our previous research. The scheme can identify the faulty nodes efficiently and improve the accuracy of the estimates significantly. It achieves very good performance at the expense of such extensive computations as logarithm and division in the detecting process. In many real-time WSN applications, the fusion center might be implemented with the ASIC and included in a standalone device. Therefore, a simple and efficient distributed estimation scheme requiring lower hardware cost and power consumption is extremely desired for fusion center. In this paper, we propose the efficient collaborative sensor fault detection (ECSFD) scheme and its VLSI architecture. Given the low circuit complexity, it is suitable for hardware implementation. The circuit of ECSFD contains 22589 gates and requires a core size of 571\,\times\,559 \mum^2 by using TSMC 0.18 \mum cell library. Simulation results indicate the accuracy of the estimates obtained from the ECSFD is better than that obtained from a conventional approach. [ABSTRACT FROM PUBLISHER]