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Approximate multipliers are used in error-tolerant applications, sacrificing the accuracy of results to minimize power or delay. In this paper we investigate approximate multipliers using static segmentation. In these circuits a set of $m$ contiguous bits (a segment of $m$ bits) is extracted from each of the two $n$ -bits operand, the two segments are in input to a small $m\times m$ internal multiplier whose output is suitably shifted to obtain the result. We investigate both signed and unsigned multipliers, and for the latter we propose a new segmentation approach. We also present simple and effective correction techniques that can significantly reduce the approximation error with reduced hardware costs. We perform a detailed comparison with previously proposed approximate multipliers, considering a hardware implementation in 28 nm technology. The comparison shows that static segmented multipliers with the proposed correction technique have the desirable characteristic of being on (or close to) the Pareto-optimal frontier for both power vs normalized mean error distance and power vs mean relative error distance trade-off plots. These multipliers, therefore, are promising candidates for applications where their error performance is acceptable. This is confirmed by the results obtained for image processing and image classification applications. [ABSTRACT FROM AUTHOR]

Information exchanges among interacting agents play a significant role in guaranteeing successful completion of the desired coordinated control tasks for a multi-agent system (MAS). Furthermore, these information exchanges are often performed over some open and resource-constrained communication networks, thereby making security and resource efficiency vitally important for various multi-agent coordinated control problems. This paper addresses a secure dynamic event-trigger-based resilient consensus control problem for an MAS in the presence of both sensor and actuator attacks. First, a distributed adaptive compensator is introduced for prediction of unavailable system states. Due to the existence of sensor and actuator attack signals, a secure dynamic event-triggered mechanism is then proposed, and a resilient control strategy is further devised for the paralyzed MAS. It is theoretically proved that the controlled MAS is asymptotically stable and asymptotic consensus is eventually achieved among the coordinated agents regardless of the attacks and constrained resources. Finally, three examples are provided to illustrate the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

For massive multiple-input multiple-output (MIMO) systems, linear minimum mean-square error (MMSE) detection has been shown to achieve near-optimal performance but suffers from excessively high complexity due to the large-scale matrix inversion. Being matrix inversion free, detection algorithms based on the Gauss–Seidel (GS) method have been proved more efficient than conventional Neumann series expansion-based ones. In this paper, an efficient GS-based soft-output data detector for massive MIMO and a corresponding VLSI architecture are proposed. To accelerate the convergence of the GS method, a new initial solution is proposed. Several optimizations on the VLSI architecture level are proposed to further reduce the processing latency and area. Our reference implementation results on a Xilinx Virtex-7 XC7VX690T FPGA for a 128 base-station antenna and eight user massive MIMO system show that our GS-based data detector achieves a throughput of 732 Mb/s with close-to-MMSE error-rate performance. Our implementation results demonstrate that the proposed solution has advantages over the existing designs in terms of complexity and efficiency, especially under challenging propagation conditions. [ABSTRACT FROM AUTHOR]

Sparse code multiple access (SCMA) is a promising multiple access technology candidate for the next-generation communication system, which can dramatically improve spectral efficiency. However, the major challenge of SCMA is the very high detection complexity. Stochastic computing is a new number representation, which can carry out complex computations with very simple logics. In this paper, we extend the application of stochastic computing to SCMA detection and propose a low complexity stochastic SCMA detector. We also design three novel stochastic logic architectures: a new low hardware cost bit stream generation architecture, a low hardware cost stochastic function node update architecture and a fast converging stochastic variable node update architecture. Analysis and simulation results show that the proposed stochastic SCMA detector saves 69% complexity compared with the traditional SCMA detectors with a comparable bit error rate performance. The synthesis results with SIMC 65-nm CMOS technology show that the proposed stochastic SCMA detector achieves 640 Mbps total system throughput with only 1.45-mm $^{{{2}}}$ cell area. [ABSTRACT FROM PUBLISHER]

This paper presents a linear current-reuse sampling phase detector for a single-loop type-I phase-locked loop (PLL) to simultaneously achieve a wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28-nm CMOS, the PLL prototype measures an integrated jitter of 440 fsRMS, and a spur level of −63.9 dBc at 3.296 GHz. It draws 3.3 mW at a 0.9-V supply and scores a jitter-power figure-of-merit (FoM) of −241.9 dB. With a 103-MHz reference input, a bandwidth of ~20 MHz aids suppressing significantly the ring VCO’s phase noise (PN), leading to an in-band PN of −116 dBc/Hz at 1-MHz offset. The die size is 0.003 mm2. [ABSTRACT FROM AUTHOR]

Soft-input soft-output (SISO) detector for the iterative detection and decoding of coded spatial modulation (SM) signals needs to compute the extrinsic bit log-likelihood ratio (LLR) associated with each detected bit. The maximum logarithmic maximum a posteriori (max-log-MAP) detector is known to perform closely to the optimal logarithmic maximum a posteriori (log-MAP) detector with much lower computational complexity. In this paper, we first apply several mathematical tricks to derive a new and low-complexity algorithm for the max-log-MAP detector. The proposed algorithm features a new tree pruning technique to visit few lattice points and a smart list administration technique to retain a max-log-MAP detector. By following the proposed algorithm, we then design a hardware architecture for SISO detection of coded SM signals over the scenario of 64-QAM symbols, 8 transmit antennas, and 4 receive antennas. Under the TSMC 40 nm CMOS technology, the VLSI implementation results reveal that our architecture requires 46.4K gates and leads to detection throughput 450 Mbps, while operating at clock frequency 400 MHz and consuming power 46 mW. Being the first hardware architecture for SISO detection of coded SM signals, our proposed low-cost max-log-MAP detector is very attractive. [ABSTRACT FROM AUTHOR]

This paper presents a compact impulse-radio ultra-wide band non-coherent receiver architecture for high data rate wireless neural recordings from active high-density CMOS-probes. The system is capable of receiving, synchronizing, and demodulating a continuous on–off keying pulse stream at 1 Gb/s and 4 GHz center frequency using an active area of 0.34 mm2 and a single 31.25 MHz crystal reference. An asynchronous threshold energy detector, including a pulse enhancement baseband with an all-digital back-end, recovers incoming transmitter clock (CDR) and acquires packet synchronization based on a data-aided mechanism (DPR). Results shows that a prototype of the receiver integrated in a 130 nm CMOS process recovers synchronization in 30 ns. The system includes I/O output buffers and driver logic at 1.8 V supply operating at 1 GHz on a 50 $\Omega $ load and crystal oscillator. Overall, it consumes 115 pJ/pulse, while the receiver core only consumes 12 pJ/pulse. This paper presents the receiver architecture, and experimental results show a sensitivity of −38 dBm at 10−3 packet error ratio. [ABSTRACT FROM AUTHOR]

This paper deals with the extended five moduli set $ \left({{2^{2n+p}, 2^{n}-1, 2^{n}+1, 2^{n}-2^{\frac {n+1}{2}}+1, 2^{n}+2^{\frac {n+1}{2}}+1}}\right)$ where n$ is a positive odd integer and p$ is nonnegative integer such that . The paper proposes an efficient residue-to-binary converter along with a converter-based sign detector for this extended set. The paper also presents a residue-to-residue transformer that transforms the same five-moduli set to the three-moduli set (2^{2n+p}, 2^{2n}-1, 2^{2n}+1) . Such a transformer enables the five-moduli set to utilize components that are (or will be) designed for the three-moduli set such as sign detectors. [ABSTRACT FROM AUTHOR]

Practical data detectors for future wireless systems with hundreds of antennas at the base station must achieve high throughput and low error rate at low complexity. Since the complexity of maximum-likelihood (ML) data detection is prohibitive for such large wireless systems, approximate methods are necessary. In this paper, we propose a novel data detection algorithm referred to as Triangular Approximate SEmidefinite Relaxation (TASER), which is suitable for two application scenarios: i) coherent data detection in large multi-user multiple-input multiple-output (MU-MIMO) wireless systems and ii) joint channel estimation and data detection in large single-input multiple-output (SIMO) wireless systems. For both scenarios, we show that TASER achieves near-ML error-rate performance at low complexity by relaxing the associated ML-detection problems into a semidefinite program, which we solve approximately using a preconditioned forward-backward splitting procedure. Since the resulting problem is non-convex, we provide convergence guarantees for our algorithm. To demonstrate the efficacy of TASER in practice, we design a systolic architecture that enables our algorithm to achieve high throughput at low hardware complexity, and we develop reference field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs for various antenna configurations. [ABSTRACT FROM PUBLISHER]

A 400 Mb/s∼2.5 Gb/s referenceless clock and data recovery (CDR) IC is presented. This paper shows that the half-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability in itself. By using this intrinsic frequency detection capability of the half-rate linear PD, a CDR can be implemented in the single loop architecture without both an external reference clock and a separate frequency detector. For verification, a prototype CDR IC was fabricated in a 0.13 \mu\textm CMOS process. With 2.5 Gb/s, 2^31 - 1 pseudorandom binary sequence (PRBS), the measurement results show that the frequency acquisition time is 17 \mu\texts, the bit error rate (BER) is better than 10−12, the jitter of the recovered clock is 8.6 \textps\mathrm{rms} and the out-of-band jitter tolerance is 0.32 \textUI\mathrm{pp}. [ABSTRACT FROM PUBLISHER]

This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digital locking loop that avoids look-up table (LUT) and finite state machine-based (FSM) locking schemes. Measurements show that the output signal spot noise at 20 MHz from the carrier is −150.7 dBc/Hz while the best locking time, for a coarse step of 364 MHz, is 115 $\mu \text{s}$ , overcoming the locking time limitations and avoiding cycle slips that usually affect the 1-bit phase detector PLL. [ABSTRACT FROM AUTHOR]

Fully passive sensors (FPS) are widely used as a simple and inexpensive alternative of their active counterparts in many applications. However, measurement of FPSs relies on extremely bulky and complicated reader circuitry. In some cases the readout method depends on measurement distance. In this paper, we propose a readout technique based on a two-mode LC-oscillator formed with two coupled resonators, i.e., the FPS and the LC tank in the reader. We show that such a configuration can offer robust measurement of fully passive resistive and capacitive sensors provided that the system operates under strong coupling. We examine measurement errors due to non-idealities of the system (finite coil $Q$ and frequency mismatch) and provide design guidelines to ameliorate these unwanted effects. Although applied to sensing in this work, this analysis can be extended to wireless power transfer and impedance transformation. [ABSTRACT FROM AUTHOR]

Recently, massive multiple-input multiple-output (MIMO) detection schemes based on message passing detection (MPD) have attracted extensive attention due to their good performance-complexity tradeoff. In this paper, to facilitate a high-throughput detector design, we introduce a layered updating schedule and propose an improved layered MPD (ILMPD) algorithm. In the new algorithm, several algorithmic transformations or approximations are derived for lower complexity. For instance, by exploiting the property of quadratic functions, the numbers of multiplications and additions in the constellation matching are both reduced by half; Through reasonable approximations, the multiplication, addition, and sorting operations in the initialization are all removed. Moreover, a lightweight early termination strategy is explored, reducing the number of detection iterations by nearly 20%. Based on the proposed ILMPD algorithm, an area-efficient architecture is devised, where several optimization methods are proposed for fewer resources and higher clock frequency. Compared with the state-of-the-art design, the presented ILMPD detector can deliver a nearly $3\times $ higher area efficiency. A reconfigurable version of the proposed detector has also been developed, which can well support modulations QPSK to 256-QAM and still exhibits a superior area efficiency. [ABSTRACT FROM AUTHOR]

For massive multiuser multiple-input multiple-output (MIMO) systems, linear detectors, such as minimum mean square error (MMSE), suffer from unbearable computational pressure due to the large-scale matrix inversions. Various iterative detectors, such as Jacobi and steepest descent (SD) as well as their enhanced variants, are applied to improve the performance and complexity trade-off. However, their benefits would not maintain when: 1) the number of users is close to that of the base station antennas and 2) channel correlation is considered. To address this problem, an iterative detector based on SD and Barzilai–Borwein (BB) algorithms entitled SDBB is introduced in this paper. Furthermore, a novel enhanced SDBB (ESDBB) detector is proposed, which combines SDBB with SD to achieve better performance in the challenging scenarios. Both theoretical and numerical results are detailed to demonstrate the advantages of ESDBB in balancing the performance and complexity. Specifically, attaining faster convergence and better bit error rate (BER) results, ESDBB outperforms methods, including adaptive Jacobi and successive over relaxation (SOR). An efficient hardware architecture for the ESDBB detector is also proposed. Implementation results on a Xilinx Virtex-7 XC7VX690T FPGA show the advantages of the proposed ESDBB detector compared to the state of the art (SOA) in terms of throughput (31.3 Mb/s) and efficiency. [ABSTRACT FROM AUTHOR]

Machine learning has become ubiquitous in applications including object detection, image/video classification, and natural language processing. While machine learning algorithms have been successfully used in many practical applications, accurate, fast, and low-power hardware implementations of such algorithms is still a challenging task, especially for mobile systems such as Internet of Things (IoT), autonomous vehicles, and smart drones. This paper presents an energy-efficient programmable ASIC accelerator for object detection. Our ASIC accelerator supports multi-class (e.g., face, traffic sign, car license plate, and pedestrian) that are programmable, many-object (up to 50) in one image with different sizes (17-scale support with 6 down-/11 up-scaling), and high accuracy (AP of 0.87/0.81/0.72/0.76 for FDDB/AFW/BTSD/Caltech datasets). We designed an integral channel detector with 2,000 classifiers for rigid boosted templates, where the number of stages used for classification can be adaptively controlled depending on the content of the search window. This can be implemented with a more modular hardware, compared to support vector machine (SVM) and deformable parts model (DPM) designs. By jointly optimizing the algorithm and the efficient hardware architecture, the prototype chip implemented in 65nm CMOS demonstrates real-time object detection of 20–50 frames/s with low power consumption of 22.5–181.7 mW (0.54–1.75 nJ/pixel) at 0.58–1.1 V supply. [ABSTRACT FROM AUTHOR]

This paper proposes a sub-harmonically injection-locked all-digital PLL (SIL-ADPLL). The SIL-ADPLL includes five main circuit blocks: injection-locked digitally controlled oscillator with single-ended injection technique (SILDCO), injection-locked frequency divider (ILFD), timing-adjusted phase detector (TPD), multiplexed time-to-digital converter (MTDC), and the pulse generator (PG). The single-ended injection technique relaxes the pulse width constraint of the injection pulse and thus reduces the design complexity of PG. The proposed ILFD aided injection timing alignment technique can align the injection timing adaptively at output frequency higher than 20 GHz. The ILFD block is inserted between the SILDCO and the TPD without much penalty of power consumption. The proposed MTDC can quantize the output of TPD with only one TDC core to further save power consumption. The proposed PG can relax the trade-off between the phase noise suppression and the power consumption. Implemented in 65 nm CMOS process with a core area of 0.462 mm2, the SIL-ADPLL achieves 18- to 23-GHz frequency range, 57.4-fs rms jitter at 20 GHz, 13.7-mW power consumption, and −253.5-dB FoM. The measurement results also show robustness over environment variation. [ABSTRACT FROM AUTHOR]

Compressed sensing (CS) analog to information converters (AICs) offer key benefits for signal reception or detection when the input signal is sparse. So far AICs have been demonstrated in environments with controlled input signal conditions and with fixed sparsity levels. This paper investigates how to make AICs effectively operate in dynamic environments with changing signal conditions and thus changing sparsity levels. We focus on RF spectrum scanning, where signals or interferers need to be detected across a wide dynamic RF spectrum, but the presented concepts are widely applicable for low-pass and band-pass CS AICs. The number of measurements and hence the number of branches required in a CS RF front end scales with the sparsity level, i.e. the number of signals that need to be detected. In practice this leads to excessively large silicon area for more than a few signals (e.g., six). We introduce the time-segmented quadrature analog-to-information converter (TS-QAIC), a scalable architecture for signal detection in dynamically changing spectrum environments. While our TS-QAIC prototype implements a fixed number of hardware branches, we experimentally demonstrate adaptive thresholding and adaptive time segmentation to adjust its signal detection capability to the sparsity level of the input signal. [ABSTRACT FROM PUBLISHER]

System-on-chip (SoC) miniaturization of radiometric sensors could dramatically improve quantitatively the study of Earth’s atmosphere in the microwave- and millimeter-wave frequency regions, enabling cost and weight reductions both for ground- and space-based observation instruments. This paper reports the analysis, design, implementation, and experimental characterization of the first K-band SoC Dicke radiometric receiver implemented in a commercial silicon–germanium technology under Space evaluations. The radiometric receiver exhibits a responsivity of about 760 kV/W and a noise equivalent power of about 232 fW/ $\surd $ Hz at the center frequency of 25.75 GHz. For a bandwidth of 2.5 GHz, the system achieves a resolution of 9 K for a relatively short integration time (1 s), 2.8 K for a medium integration time (10 s), and 0.9 K for a relatively long integration time (100 s). [ABSTRACT FROM AUTHOR]

This paper presents a 46 nF/10 $\text{M}\Omega $ -range, digital-intensive, reconfigurable RC-to-digital converter (R2CDC) that can readout multiple C and R sensors in a time-interleaved fashion. Ratio-metric conversion using swing-boosted period-modulation (SB-PM) front-end by the R2CDC results in 114 aFrms/ $0.37 \Omega _{\text {rms}}$ resolutions and a worst-case temperature-drift of 64.2 ppm/°C over −40 to 125°C. Femto-farad capacitances can be sensed with a relative code-deviation less than 0.16 % even when parasitics vary 30 times the baseline. Implemented in a $0.18 ~\mu \text{m}$ standard CMOS process, the R2CDC consumes 140 $\mu \text{A}$ from a 1 V supply, occupying an active area of $0.175 ~\mu \text{m} ^{\mathrm{ 2}}$. [ABSTRACT FROM AUTHOR]

This paper proposes a fingerprint scanning analog front-end (AFE) for a $41\times32$ under-glass mutual-capacitive fingerprint sensor. As the mutual-capacitive fingerprint sensor is a smaller version of a projected-capacitive touch screen, this transparent fingerprint sensor can be mounted underneath screen cover glass. However, such glass significantly diminishes the signal-to-noise ratio (SNR) of fingerprint scanning AFE in proportion with increasing glass thickness. Moreover, external noise interferences from the display and charger are severe in displays with thin form factor. The proposed fingerprint scanning AFE can achieve a 17 atto-farad capacitance resolution using high-voltage (20 V) transmitters and multi-channel receivers comprising a pipelined readout amplifier, mixer, and second-order low-pass filter (128 kHz). A differential sensing structure and band-pass filtering are employed in the receiver front-end to enhance the noise immunity. A differential phase-encoded sequential driving transmitter with a proposed on-chip replica channel mitigate random offsets in the readout amplifier with high matching accuracy. Measurement results show that the fingerprint scanning integrated circuit (IC) fabricated by a $0.18 ~\mu \text{m}$ BCD (Bipolar-CMOS-DMOS) process achieved a 13.4 dB SNR at a frame rate of 120 Hz under a 0.2 mm-thick cover glass. The prototype IC provides 20 VPP noise immunity from 0 to 500 kHz and consumes 23.2 mW from a 3.3 V supply. [ABSTRACT FROM AUTHOR]

This paper investigates the secure consensus tracking problem for continuous-time nonlinear multiagent systems with sensor attacks. By designing a secure data selector, the unattacked output data is extracted from a group of output measurements under sparse sensor attacks. Then, by virtue of the obtained data and neural networks, a state observer is constructed to estimate the unavailable system states, where the convex combination theory is introduced to reduce the difficulty of solving observation gains. To utilize the limited communication resources reasonably, a novel saturated threshold event-triggered control strategy is proposed to reduce control updates, and then each update is encoded into a binary signal (0 or 1) to further reduce the occupation of communication bandwidth. The designed control scheme ensures that all closed-loop signals are semi-globally uniformly ultimately bounded, and its effectiveness is verified via a simulation of attitude control of unmanned aerial vehicles. [ABSTRACT FROM AUTHOR]

Sphere decoders allow receivers in multiple-input multiple-output (MIMO) communications systems to detect QAM symbols with quasi-optimal accuracy and low complexity compared with the ideal maximum likelihood detector. However, their high complexity relative to simple linear detectors means that the latter are still usually adopted, despite their lower detection performance. Configurable sphere decoders, such as selective spanning fast enumeration (SSFE), allow complexity to be reduced at the cost of lower performance and are hence ideal for transceivers for Internet-of-Things equipment, where scale, operating context and resource, and energy budgets vary dramatically. However, SSFE still suffers performance limitations due to the internal heuristics employed for symbol selection and enumeration and real time, and software-defined realizations for even moderately demanding MIMO standards, such as 802.11n, have not been recorded. This paper presents a new variant of SSFE which, by employing novel fast symbol enumeration and modulation dictionary spanning heuristics, increases performance and computational efficiency to the point where very substantial reductions in resource can be achieved without impacting detection accuracy relative to SSFE. This is demonstrated via a series of field programmable gate array-based detectors $2 \times 2$ and $4 \times 4$ , 16-QAM 802.11n MIMO. [ABSTRACT FROM PUBLISHER]

Sign detection and magnitude comparison are two difficult operations in Residue Number System (RNS). Existing algorithms mainly tackle either problem independently. Magnitude comparison in RNS is typically solved by parity check or transcoding the residues into weighted representation. Comparison of signed integers in residue domain is supplemented by separately designed RNS sign detector. In this paper, a radically different quantization approach for comparing signed integers in the four-moduli supersets, S1\equiv\{2^{n+k},2^{n}-1,2^{n}+1,2^{n+1}-1\} and S2\equiv\{2^{n+k},2^{n}-1,2^{n}+1,2^{n-1}-1\}, is proposed. The dynamic range of the target moduli set is quantized into equal divisions, and the ranks of the divisions resided by the integers in comparison are identified and compared from their residue representations. The sign of a residue representation can be directly extracted from the most significant bit of its rank, or with simple logic function if it resides in the middle rank. Comparing with the best existing signed magnitude comparator applicable to these two moduli sets, our synthesis results on 65 nm CMOS technology show that the proposed design is at least 22.48% smaller, 19.08% faster and 27.66% more energy-efficient for S1 and 18.75% smaller, 16.41% faster and 23.30% more energy-efficient for S2. [ABSTRACT FROM AUTHOR]

This paper proposes an intra-iterative interference cancellation (IIC) detector based on convex optimization for large-scale MIMO systems. By utilizing Newton's method to solve the optimization problem, a hardware-friendly detector is implemented in a 65 nm CMOS technology. The proposed detector has a throughput of 3.6 Gb/s with a 600 MHz operating frequency. The simulation results indicate that the block-error rate (BLER) performance of the proposed method can approach that of the minimum mean square error (MMSE) detector. The design is found to be more efficient than other recently proposed MIMO detector implementations. [ABSTRACT FROM PUBLISHER]

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/ƒ noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency (ƒch) same as the sampling frequency (ƒs). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/√Hz input-referred noise density, 1.9 μ V offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mVpp. With −110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique. [ABSTRACT FROM AUTHOR]

The article introduces the special section on sensors published in the January 2007 issue of the journal "IEEE Transactions on Circuits & Systems." The articles in this special section cover a wide range of topics including CMOS imagers, neuromorphic sensory systems, bio and biomedical sensors and other smart sensors like capacitive sensors and interface circuits.

For a coded massive multi-user multiple-input multiple-output (MIMO) system, a soft-output MIMO detector is essential since it can provide a significant coding gain, e.g., 3 dB, compared with a hard-output detector. However, the computational complexity of the soft-output MIMO detector is usually much greater than that of the hard-output detector. This paper presents the first soft-output message-passing detector (MPD), which is also integrated with a high-throughput polar decoder. The algorithm and architecture are designed concurrently to improve the hardware performance. The proposed techniques, including the adaptive variance estimation and reliable symbol detection, reduce the complexity of the MPD by 98.3%, and enable soft output for the outer polar decoder. Compared to the state-of-the-art hard-output design, the proposed MPD achieves a $5.86\times $ higher throughput-to-area ratio (TAR) with 54.3% lower energy dissipation, despite the soft output. The proposed bidirectional-propagation belief propagation decoder is devised to reduce the critical path and to increase the throughput. The proposed polar decoder can improve the TAR by 35% with a comparable area and energy compared with the state-of-the-art polar decoder. A polar-coded massive MIMO receiver that supports a length-1024 rate-1/2 polar code, 128 receive antennas, and eight users is designed and implemented, and delivers a throughput of 7.61 Gb/s. [ABSTRACT FROM AUTHOR]

This paper embeds a “phase-reset” scheme into a bang-bang clock and data recovery (CDR) to periodically realign the clock phase to the data rising edge using a gated-VCO. This reduces both the CDR lock time and bit errors during pull-in, while increasing the CDR capture range. The CDR is fabricated in 65-nm CMOS, operates at 8-11 Gb/s, and demonstrates a 9 × increase in capture range. The CDR consumes 84 mW during lock, and 48 mW in steady state. [ABSTRACT FROM AUTHOR]

This paper presents a hardware-efficient architecture for 4×4 and 8×8 high-throughput MIMO detectors. The adopted non-constant K-best algorithm tends to keep more survival nodes in top search tree layers and reduce computational complexity in bottom layers as opposed to the conventional K-best algorithm. A pipelined architecture is used to generate one detection output per clock cycle, thus meeting multi-gigabit throughput requirements for advanced wireless communication systems. The proposed efficient folding scheme strikes a suitable balance between complexity and throughput. This paper also presents a discussion on the scalability of this architecture with respect to the setting of QAM size, K values, and antenna number. One 4×4 MIMO detector IC has been manufactured and one 8×8 MIMO detector layout has been realized, both in 90-nm CMOS technology. The 4×4 detector IC has 232 kilogates (KG). Its maximum measured throughput is 4.08 Gbps at 170-MHz operating frequency and 1.3-V core voltage. The 8×8 detector has 665 KG. Its post-layout simulation results show that it achieves 4.37-Gbps throughput at 182-MHz operating frequency and 0.9-V core voltage. Compared to earlier hard-output detectors, both implemented detectors demonstrate good normalized power and normalized hardware efficiencies. [ABSTRACT FROM AUTHOR]

This paper presents an integrated ultra-low-power (ULP) wireless sensor system-on-chip (SoC) that can be used for voltage sensing in both Internet of Things applications and bio-potential monitoring. In order to increase the energy efficiency of the analog front-end (AFE), we propose a noise and power efficient push-pull low noise instrumentation amplifier (LNIA) with a built-in ripple reduction loop based on capacitor reuse. A low-power ISM-band harmonic injection locked on-off-keying transmitter (OOK-TX) is also implemented for energy efficient wireless connectivity. Circuit implementations, design considerations, and detailed analysis are presented to improve the overall energy efficiencies of the SoC including the AFE, TX and, the power management unit. The proposed ULP-SoC is fabricated in 130 nm CMOS technology with a total area of 1.92 mm2. The total power consumption of the proposed system-on-chip is 197.1 μW which is one of the lowest among state-of-the-art wireless sensor SoC. [ABSTRACT FROM AUTHOR]

A novel galvanic isolated amplifier based on CMOS integrated Hall sensors is presented in this paper. Two serially connected Hall-effect sensors are integrated along with their instrumentation amplifiers using the TSMC 65nm process. A printed-circuit board is employed to validate the proposed isolation amplifier by assembling the chip with chopper modulator, coil driver, miniature coil, variable gain amplifier, and anti-aliasing filter. Because of the miniaturized size of isolation components, this approach can be packaged in chip for industrial applications. This solution replaces the need of bulky/frequency dependent current transformers, complex isolation amplifiers with embedded analog to digital converters, and allows proposed sensors to be used in voltage and current sensing applications. The introduced prototype achieves an input referred offset of 1 mV, 50 dB full-scale signal-to-noise ratio in a 10 kHz bandwidth, and spurious-free dynamic range of 53 dB, while satisfying continuous isolation working voltage of 550 V. [ABSTRACT FROM AUTHOR]

Disturbances, uncertainties, noises and device faults commonly exist in microgrids and often undermine the system stability. To meet these challenges, robust control methods have been recently employed in microgrids systems. In this paper, an active fault-tolerant control scheme is proposed for DC islanded microgrids subjected to sensor fault and external disturbance. Firstly, a distributed ${H_\infty }$ observer is designed to estimate the uncorrupted voltage and current with high accuracy. Then, an observer based state feedback controller is proposed to ensure stability of voltage regulation for the system. A consensus based control layer in the secondary level is provided to realize current sharing. For the plug-and-play operation of DC microgrids, decentralized parameters design approaches for the observer and controller are both discussed. Finally, simulation studies and experiments are carried out on a DC microgrid system to evaluate the effectiveness of the proposed fault-tolerant control scheme. The simulation and experiment results show that compared with previous works, the proposed observer based control strategy can significantly improve the reliability and resilience of DC microgrid systems. [ABSTRACT FROM AUTHOR]

This paper presents an ultrasound rangefinder system able to find relative distances among energy-constrained sensor nodes. The nodes build a swarm that is operated in collision and multipath rich environments. A new distance measurement technique combining Wake-up and Frequency Modulated Continuous Wave (FMCW) is proposed to enable the ranging while neglecting the echoes from passive reflectors in the environment. The building blocks of the sensor nodes comprise a transmitter, a wake-up receiver, and a ranging receiver, all implemented in a 65 nm CMOS technology. The transmitter includes two switched-capacitor converters and an output multiplexer to generate a four-level driving signal and broadcast either a wake-up sequence or a digitally synthesized ultrasound Chirp. The transmitter dissipates $0.43~\mu \text{J}$ and ${0.82~\mu \text {J}}$ to broadcast the wake-up signal and the Chirp, respectively. A mixer first architecture is exploited in the wake-up receiver to reduce the always-on power consumption of the nodes. The ranging receiver uses a heterodyne architecture suited for the FMCW. The power consumption of the wake-up receiver and ranging receiver is 23.6 nW and $0.56~\mu \text{W}$ , respectively. The proposed rangefinder is experimentally characterized up to a 1 m distance in air and dissipates $1.25~\mu \text {J}$ per measurement, achieving a resolution of 18.7 mm at 0.55 m. [ABSTRACT FROM AUTHOR]

On-chip process monitor/sensor circuits capture the process corner of a chip in the postfabrication stage. Logic-NMOS and logic-PMOS based sensors, however, fail to capture the process corners for memories, as bitcells have a different implant from logic cells. In this paper, a novel on-chip bitcell-based process monitor (BPMON) circuit is implemented that distinguishes between and detects the standard global corner of memories in any chip. It leverages a current-mirror and a near-threshold biased bitcell array structure that changes the output voltage of the circuit in accordance with changes in the process corner. BPMON separately tracks bitcell NMOS and bitcell PMOS process corners. Silicon data from over 100 chips from five wafers in 28 nm CMOS shows correct bitcell process corner predictions. These predictions show the expected strong correlation with read and write vccmin, enabling vccmin to be lowered below specifications while still achieving a 100% yield. [ABSTRACT FROM PUBLISHER]

This paper covers the development and testing of a high temperature signal conditioning unit capable of sensing wide dynamic range signals from rotating sensors. The unit includes a current peak detector block, a digital pulse generator, ESD (electrostatic discharge) protection and generates an output current proportional to the peak value of the applied input signal. The digital data from the unit can be directly utilized by the FADEC (Full Authority Digital Electronic Control) system or the EHMS (Engine Health Monitoring System) on an aeroengine. The mixed signal unit presented in this paper was designed and fabricated on 1 \mu\textm silicon-on-insulator (SOI) CMOS (complementary metal oxide semiconductor) technology and has been shown to function up to 235 ^\circ Celsius with very high linearity of the output signal. This is the highest operating temperature of an integrated signal conditioning unit developed for a civil aircraft. The mixed signal unit was mounted on a high temperature hybrid module and helps reducing the weight of the aeroengine by several kilograms. [ABSTRACT FROM AUTHOR]

The evolution of electronics towards compact and highly energy-efficient systems requires joint efforts in developing both innovative system architectures and novel devices. Recent developments show that time-based sensor interfaces yield highly-digital architectures, which are compatible with advanced silicon CMOS at highly-scaled technology nodes. Advancements in CMOS time-based sensor interfaces show that new circuit techniques can help to increase performance and robustness. Furthermore, these architectures have successfully been implemented in carbon nanotube technology, a promising technology to further reduce the energy consumption in electronics. In addition, CNTs are excellent candidates to be functionalized as sensors, and can potentially improve the energy efficiency of sensors and sensor interfaces for future autonomy-demanding applications. This paper presents an overview of time-based sensor interfaces implemented in CMOS and CNT technologies, allowing for scalable and robust designs. Several CMOS and VLSI-compatible CNFET-based sensor interface circuits have been fabricated and validated through measurements, demonstrating the feasibility of these solutions. [ABSTRACT FROM AUTHOR]

This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit with an asynchronous baud-rate sampling to achieve an adaptive equalization as well as a data rate acquisition. The proposed scheme also enables the use of a successive approximation register (SAR) based approach in the frequency acquisition and results in a fast coarse lock process. The CDR guarantees a robust operation of a fine locking even in the presence of large input data jitter due to the adaptive equalization and a jitter-tolerable rotation frequency detector (RFD) that eliminates a dead-zone problem with a simple circuitry. The fabricated CDR in 65 nm CMOS shows a wide lock range of 0.65-to-10.5 Gb/s at a bit error rate (BER) of 10^-12. The CDR consumes 26 mW from a single supply voltage of 1 V at 10 Gb/s including the power consumption for equalizer. By an adaptive current bias control, the power consumption is also linearly scaled down with the data rate, exhibiting a slope of about 2 mW decrease per Gb/s. [ABSTRACT FROM AUTHOR]

This paper presents the design and experimental characterization of a Proton Sound Detector (ProSD), a device that physically captures and senses the weak acoustic signal emitted by the fast energy deposition at the end of the same proton beam range. The measured acoustic signal Time-of-Flight provides a very accurate ($13~\mu \text{m}$ accuracy) measure of the proton beam penetration depth in water, improving the proton range verification accuracy w.r.t. previous works in pre-clinical scenarios. This suggests interesting possibilities for high-accuracy and real-time beam monitoring and calibration in hadron-therapy for cancer treatment. The detector has been fully characterized and tested with a physical 20 MeV proton beam in a water energy absorber. The ProSD and the water tank have been mounted in front of the exit layer of a 20 MeV 120 ns pulse time-width proton beam. A clear sinusoidal-like acoustic signal of 5 Pa and 2.3 MHz frequency has been detected at 12 dB SNR with 0.8 Gy single shot dose. After averaging 10 beam shots the achieved Signal-to-Noise-Ratio is 22 dB allowing a $\pm 7.5~\mu \text{m}$ precision vs. previously reported $\pm 45~\mu \text{m}$ ionoacoustic precision. [ABSTRACT FROM AUTHOR]

In this paper, a computational digital pixel sensor (DPS) equipped with an on-chip image-processing capability has been developed. In order to resolve the interconnection bottleneck between the sensor array and on-chip processing units, a new block-readout architecture has been proposed and implemented on the chip. The data from the sensor array are read out in a form of a pixel block compatible to kernel image processing, and they are processed in parallel by on-chip processing units. Such an architecture has enabled us to carry out an efficient kernel processing using a linear array of single-instruction-multiple-data processing units. In order to demonstrate the advantage of such an architecture, a rank-order filtering circuit has been implemented on the chip as a case study of the on-chip image processing. In this paper, a binary-search rank-order filtering algorithm has been implemented in a simple circuitry. A proof-of-concept chip having an array of 64 x 48 pixels was designed and fabricated using a 0.35-μm CMOS technology, and the concept has been verified by the measurement of fabricated chips. [ABSTRACT FROM AUTHOR]

In this paper, a new technique to enhance the sensitivity of microwave resonators is introduced. Double split ring resonators are implemented as the core of a loss-compensated resonator. It is illustrated that regenerative oscillators when mixed together can produce higher order intermodulation products (IMP) at the output. The variations in sensing tone are multiplied and exhibit considerably higher sensitivities at 3rd, 5th, and 7th IMP components compared to the main resonant frequency. The sensor is also integrated into wireless platform with ultra-wideband bowtie antennas. Common fluids such as Toluene, n-Heptane, IPA, Ethanol, Methanol, Acetone, and Water are tested in fluidic channel and demonstrated that the sensitivity for intermodulation products are significantly increased proportional to the order of IMP. The proposed sensor is also examined with glucose concentration sensing for the range of 0– 600 mg/dL and significant variation for 7th IMP sensor is observed as opposed to saturation of conventional sensor. Also, asphaltene concentrations down to 6 ppm are recognizable when precipitated from toluene solution using the proposed sensor. Moreover, a rigorous analytical study is presented for phase noise of the IMP originated from reference signals. [ABSTRACT FROM AUTHOR]

Aiming at reducing the complexity of minimum mean square error (MMSE) detection in massive multiple-input multiple-output (MIMO) systems, this paper proposes a detection algorithm with high convergence rate and an efficient hardware architecture based on second-order Richardson iteration (SORI). In the proposed algorithm, a pre-iteration-based initialization method is presented to accelerate the convergence without extra complexity. In addition, the approximation of relaxation factor and the log-likelihood ratio (LLR) is introduced to further reduce computing load. Theoretical analysis demonstrates the advantages of the proposed algorithm in fast convergence and low complexity, and simulation results show that the proposed algorithm can efficiently approach MMSE performance. Based on this algorithm, a flexible hardware architecture is designed, which is deeply pipelined to support $128\times U$ ($8\leq U\leq 32$) massive MIMO detection with the configurable number of iterations, and a folded dual-mode systolic array (DMSA) is fully utilized to achieve the flexibility with low hardware consumption. Implemented on Xilinx Virtex-7 FPGA and SMIC 40nm CMOS technology, the proposed detector is competitive in terms of energy and area efficiency compared to state-of-the-art iterative detectors, and it can adapt to the varied channel condition and the number of users in massive MIMO systems. [ABSTRACT FROM AUTHOR]

This paper introduces a fully integrated switched-capacitor (SC) DC-DC boost converter suitable for energy harvesting in miniature sensor systems with varying harvesting source and battery voltages. Unlike the conventional SC DC-DC boost converters, where efficiency is optimized only for a few topology-dependent voltage conversion ratios (VCRs), the proposed soft-charging-based SC converter achieved VCR-insensitive evenly high efficiency for a wide range of input and output voltages. A test chip was fabricated in 180nm process, and the measured peak efficiency and average efficiency are 85.3% and 83.6%, respectively, for 1.8V regulated output voltage and a wide range of input voltages (0.95–1.8 V). Also, a peak efficiency of 88.9% and average efficiency of 87.6% are achieved for a wide range of battery output voltages (3.0–4.2 V) and a 1.2V harvesting source input voltage. [ABSTRACT FROM AUTHOR]

When operating at a gigahertz-level frequency, a high-frequency signal is distorted and degraded through the channel. To meet the demand of low cost and the low power consumption for consumer electronic products, this paper proposes a power-saving adaptive equalizer with digital-controlled self-slope detection to compensate channel losses. Reducing and shutting down high-speed circuits in addition to digitization are the most effective methods for minimizing both power and cost. This study also proposes a serial processing for reducing one high-speed detection circuit. The main concept is to use a self-slope detection circuit, which compares two continuous serial slopes, instead of a previous detection circuit, which uses a slicer. After compensation, a shutdown mechanism switches OFF the control circuit to reduce power. A serial processing enables channeling the data through the same circuit and path to avoid swing balancing and mismatch problems. An experimental chip was implemented using 90-nm 1P9M CMOS technology. In the experiment, the equalizer is operated at a supply power of 1 V with 4.35 mW. The core area occupies of $120~\mu \text{m} \times 189~\mu \text{m}$ , and the peak-to-peak jitter measured at 5 Gb/s by using the PRBS31 pattern through a 1.5-m channel is 0.36 UI. [ABSTRACT FROM AUTHOR]

A 1.5–3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency range and small intrinsic delay. The inverter-based fine delay line is controlled by an XOR-based up/down counter with dead-zone free phase detector to overcome the dead-zone problem of conventional phase detectors. The D-type flip-flops in the phase detector are modified to detect sub-ps level delay difference between the input and output clocks, so that a delay resolution of better than 1 ps is achieved in the proposed design. The combination of both coarse and fine locking processes gives outstanding performance in terms of residual phase difference and output jitter. The overall design occupies 0.0077 mm2 area. The experimental results show that the peak-to-peak and root mean square jitters are 12 and 1.629 ps at 3.3 GHz, respectively, while the input jitter is 2.6 ps peak-to-peak and 612 fs rms. [ABSTRACT FROM PUBLISHER]

An on-chip implementable algorithm for allocation of an X-ray photon imprint, called a hit, to a single pixel in the presence of charge sharing in a highly segmented pixel detector is described. Its proof-of-principle implementation is also given supported by the results of tests using a highly collimated X-ray photon beam from a synchrotron source. The algorithm handles asynchronous arrivals of X-ray photons. Activation of groups of pixels, comparisons of peak amplitudes of pulses within an active neighborhood and finally latching of the results of these comparisons constitute the three procedural steps of the algorithm. A grouping of pixels to one virtual pixel, that recovers composite signals and event driven strobes, to control comparisons of fractional signals between neighboring pixels are the actuators of the algorithm. The circuitry necessary to implement the algorithm requires an extensive inter-pixel connection grid of analog and digital signals, that are exchanged between pixels. A test-circuit implementation of the algorithm was achieved with a small array of $32\times 32$ pixels and the device was exposed to an 8 keV highly collimated to a diameter of 3- \mu \text{m} X-ray beam. The results of these tests are given in this paper assessing physical implementation of the algorithm. [ABSTRACT FROM AUTHOR]

This paper introduces a novel low-complexity multiple-input multiple-output (MIMO) detector tailored for single-carrier frequency division-multiple access (SC-FDMA) systems, suitable for efficient hardware implementations. The proposed detector starts with an initial estimate of the transmitted signal based on a minimum mean square error (MMSE) detector. Subsequently, it recognizes less reliable symbols for which more candidates in the constellation are browsed to improve the initial estimate. An efficient high-throughput VLSI architecture is also introduced achieving a superior performance compared to the conventional MMSE detectors with less than 28% added complexity. The performance of the proposed design is close to the existing maximum likelihood post-detection processing (ML-PDP) scheme, while resulting in a significantly lower complexity, i.e., 4.5\times 10^2 and 7\times 10^4 times fewer Euclidean distance (ED) calculations in the 16-QAM and 64-QAM schemes, respectively. The proposed design for the 16-QAM scheme is fabricated in a 0.13\mum CMOS technology and fully tested, achieving a 1.332 Gbps throughput, reporting the first fabricated design for SC-FDMA MIMO detectors to-date. A soft version of the proposed architecture is also introduced, which is customized for coded systems. [ABSTRACT FROM AUTHOR]

With the advent of technology over the recent years, the low-density parity-check (LDPC) codes, which were once seen as an impractical concept, are now poised to be the next big thing in the communication standards of today for their near-capacity performances. Nonetheless, the physical implementation of LDPC decoders is more often than not encumbered by the arithmetic of its decoding algorithm. Entangled by numerous computations of minima, LDPC decoders not only require considerable amount of resources to the implement cascaded pair-wise comparators, but also yield low decoding throughputs. In this paper, we propound a novel design for the computation of minimum and subminimum in LDPC decoding, known as the cognitive-amplification detector (CAD). By leveraging on the finite precision of fixed-point binary representation in actual hardware, our CAD proposition renders significant gains in decoding throughput and savings in resource consumption of up to 20% and 15%, respectively, not to mention negligible trade-offs in error-correcting capabilities. [ABSTRACT FROM AUTHOR]

Compact integrated thermal sensors are utilized to measure hot / cold spots in CPU cores in multiple locations and are important for the power/performance of the chip. Bipolar junction transistors (BJT) are the industry standard for temperature sensing elements because of their predictable physics. This paper reports on one of the smallest PNP BJT bandgap based thermal sensors to date. Miniaturization was achieved by using switched capacitor circuits with very small capacitors as opposed to the standard resistor-based bandgaps. Digitally controlled trims enable either a higher resolution or a nearly linear response to temperature. This ultra-miniature 0.003 mm2, PNP thermal- based sensor is fabricated in TSMC 65nm. It achieves a measured total ${\pm 3\sigma }$ error of ±1.35°C with a resolution of 65mK and a 4.1ms conversion time. The sensor is optimized for dense CPU thermal mapping. [ABSTRACT FROM AUTHOR]

This paper presents an Analog Front-End for integrated Wake-Up Radios. The proposed Analog Front-End is composed of an envelope detector, a Schmitt trigger and a biasing block and has three distinctive features: i) clockless solution, which does not require an always-on oscillator; ii) an envelope detector with band-pass response which leads to smaller capacitance, thus easier integration, and low-frequency noise suppression; iii) temperature compensated biasing scheme. An active scheme for the detector is used based on MOSFETs operated in the subthreshold region with a self-biased topology. Advantages and drawbacks of the proposed architecture are analyzed. A prototype was fabricated in the STMicroelectronics 90-nm BCD technology. The overall power consumption, excluding the biasing block, is 36 nW at 1.2 V. A 10 −3 Bit Error Rate is measured with a 771-MHz, 2-kbit/s OOK modulated input signal with −46 dBm power at room temperature and at −20 °C, and with almost −43 dBm power at 60 °C. [ABSTRACT FROM AUTHOR]

Hardware acceleration substantially enhances both energy efficiency and performance, but raises major challenges for programmability. This is especially true in the domain of approximate computing, where energy-approximation tradeoffs at the hardware level are extremely difficult to encapsulate in interfaces to the software level. The programmability challenges have motivated co-design of accelerators with program-synthesis frameworks, where the structured computations resulting from synthesis are exploited towards hardware specialization. This paper proposes energy-aware code synthesis targeting heterogeneous architectures for approximate computing. A heterogeneous architecture for embedded sensor inference is employed, demonstrated in custom silicon, where programmable feature extraction is mapped to an accelerator via genetic programming. The high level of accelerator specialization and structured mapping of computations to the accelerator enable robust energy models, which are then employed in a genetic-programming algorithm to improve the energy-approximation Pareto frontier. The proposed algorithm is demonstrated in an electroencephalogram-based seizure-detection application and an electrocardiogram-based arrhythmia-detection application. At the same level of baseline inference performance, the energy consumption of genetic-programming models executed on the accelerator is 57.4% and 21.8% lower, respectively, with the proposed algorithm, compared to a conventional algorithm without incorporating energy models for execution on the accelerator. [ABSTRACT FROM AUTHOR]