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This paper provides a review of design approaches towards artificial intelligence (AI) System-on-Chip. AI algorithms have progressed over the past decades from perceptron-based neural network (NN) and neuro-fuzzy (NF) system to today’s deep neural network (DNN) and neuromorphic computing. Recent DNN hardware accelerators focus on energy-efficient integration of digital circuits to realize real-time DNN operation while neuromorphic processors deploy new memory technologies with analog computation for low power consumption. However, different design approaches can be applied to such processor implementation with their pros and cons. This paper reviews from the early processor designs for NN and NF in both mixed-mode and digital implementations to the recent DNN SoC designs that we have proposed for a decade. The former content deals with NN and NF processors used as a functional building block of a machine vision SoC, while the latter concentrates on integration of the whole DNN function. We also provide a discussion on the approaches, and provide perspective on future research directions. [ABSTRACT FROM AUTHOR]

In this paper, using a method based on nonsmooth analysis and the Lyapunov method, several new sufficient conditions are derived to ensure existence and global asymptotic stability of the equilibrium point for delayed Cohen-Grossberg neural networks. The obtained criteria can be checked easily in practice and have a distinguished feature from previous studies, and our results do not need the smoothness of the behaved function, boundedness of the activation function and the symmetry of the connection matrices. Moreover, two examples are exploited to illustrate the effectiveness of the proposed criteria in comparison with some existing results. [ABSTRACT FROM AUTHOR]

A neural network is said to be convergent (or completely stable) when each trajectory tends to an equilibrium point (a stationary state). A stronger property is that of absolute stability, which means that convergence holds for any choice of the neural network parameters, and any choice of the nonlinear functions, within specified and well characterized sets. In particular, the property of absolute stability requires that the neural network be convergent also when, for some parameter values, it possesses nonisolated equilibrium points (e.g., a manifold of equilibria). Such a property, which is really well suited for solving several classes of signal processing tasks in real time, cannot be in general established via the classical LaSalle approach, due to its inherent limitations to study convergence in situations where the neural network has nonisolated equilibrium points. In this paper, a new method to address absolute stability is developed, based on proving that the total length of the neural network trajectories is finite. A fundamental result on absolute stability is given, under the hypothesis that the neural network possesses a Lyapunov function, and the nonlinearities involved (neuron activations, inhibitions, etc.) are modeled by analytic functions. At the core of the proof of finiteness of trajectory length is the use of some basic inequalities for analytic functions due to Łojasiewicz. The result is applicable to a large class of neural networks, which includes the networks pro- posed by Vidyasagar, the Hopfield neural networks, and the standard cellular neural networks introduced by Chua and Yang. [ABSTRACT FROM AUTHOR]

In this paper, we show that any N × M-dimensional delayed cellular neural network described using cloning templates can have no more than 3N×M isolated equilibrium points and 2 N×M of these equilibrium points located in saturation regions are locally exponentially stable. In addition, we give the conditions for the equilibrium points to be locally exponentially stable when the equilibrium points locate the designated saturation region. These conditions improve and extend the existing stability results in the literature. The conditions are also very easy to be verified and can be checked by direct examination of the templates, regardless of the number of cells. Finally, the validity and performance of the results are illustrated by use of two numerical examples. [ABSTRACT FROM AUTHOR]

In this paper, two new architectures for high-speed CMOS wave-pipelined current-mode A/D converters (WP-LADCs) are proposed and analyzed. In the new WP-IADC architectures, the wave-pipelined theory is applied to both pipeline structures, called full WP-IADC (FWP-IADC) and Indirect transfer WP-IADC (ITW-IADC). In the FWP-IADC, each stage uses the full current-mode wave-pipelined structure without Switched-current cell circuits. In the ITWP-LADC, the switched-current cells are incorporated into the wave-pipelined stages which are divided into several sections with controlled clocks. Therefore, the proposed ITWP-IADC performs optimally in terms of speed and accuracy in the WP-IADCs. Generally, the proposed WP-LADCs have the advantages of high speed, high input frequency, high efficiency of timing usage, high clock-period flexibility in switched-current cells for precision enhancement, and reduced number of switched-current cells in the overall data path for linearity improvement. According to the theoretical analysis on the proposed WP-LADC structures, the minimum sampling clock period is proportional to the intrinsic delay of the current mirror and the increased rise/fall time in each wave-pipelined stage. The HSPICE simulation results reveal that, under Nyquist rate sampling in 8-b resolution, a sampling rate of 20 and 54 MHz can he achieved for FWP-IADC and two-section ITWP-IADC, respectively, if four wave-pipelined sections are used, the ITWP-LADC can be operated at 166 MHz at En input frequency of 8 MHz. To experimentally verify the correct function of the proposed WP-IADC structures, the proposed new architecture of the FWP-LADC Is implements by using 0.35-μm CMOS technology. The measurement results successfully demonstrate the feasibility of wave-pipelined IADC architectures in applications of high-speed ADCs. [ABSTRACT FROM AUTHOR]

Recent years have seen an increasing interest in the development of artificial intelligence circuits and systems for edge computing applications. In-memory computing mixed-signal neuromorphic architectures provide promising ultra-low-power solutions for edge-computing sensory-processing applications, thanks to their ability to emulate spiking neural networks in real-time. The fine-grain parallelism offered by this approach allows such neural circuits to process the sensory data efficiently by adapting their dynamics to the ones of the sensed signals, without having to resort to the time-multiplexed computing paradigm of von Neumann architectures. To reduce power consumption even further, we present a set of mixed-signal analog/digital circuits that exploit the features of advanced Fully-Depleted Silicon on Insulator (FDSOI) integration processes. Specifically, we explore the options of advanced FDSOI technologies to address analog design issues and optimize the design of the synapse integrator and of the adaptive neuron circuits accordingly. We present circuit post-layout simulation results and demonstrate the circuit’s ability to produce biologically plausible neural dynamics with compact designs, optimized for the realization of large-scale spiking neural networks in neuromorphic processors. [ABSTRACT FROM AUTHOR]

Neuromorphic computing is an attractive avenue of research for processing and learning complex real-world data. With technology migration into nano and molecular scales several area and power efficient approaches to the design and implementation of artificial neural networks have been proposed. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems by facilitating the implementation of multilevel logic. Specifically, the innate reconfigurability of memristors can be exploited to realize synapses in artificial neural networks. This work focuses on the development of a variation-tolerant training methodology to efficiently reconfigure memristive synapses in a Trainable Threshold Gate Array (TTGA) system. The training process is inspired from the gradient descent machine learning algorithm commonly used to train artificial threshold neural networks, perceptrons. The design and CMOS/Nano implementation of the TTGA system from trainable perceptron based threshold gates is detailed and results are provided to showcase the training process and performance characteristics of the proposed system. Also shown are the results for training a 1T1M (1 Transistor and 1 Memristor) multilevel memristive memory and its performance characteristics. [ABSTRACT FROM PUBLISHER]