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An odd-element half-wave-rectification superposition (OHS) technique is presented and verified for designing the high-multiplication factor frequency multipliers. The proposed OHS technique superposes N odd-element phase-shifted half-wave-rectification (HWR) fundamental signals ($f_{0}$) to extract the 2N-order harmonic (2N $f_{0}$) while canceling the fundamental ($f_{0}$) and the 2nd to (2N-1)th harmonics without extra filtering. Compared with the reported even-element half-wave-rectification superposition technique (EHS) technique, the proposed OHS technique can realize the same multiplication factor but requires only a half number of the input HWR signals. Thus, the proposed OHS technique can be applied to design the high-multiplication factor frequency multiplier that is difficult to be implemented using the reported EHS technique. To verify the validity of the proposed OHS technique, a differential $\times 6$ frequency multiplier with the input frequency range of 5-7GHz and output frequency range of 30–42 GHz was implemented in 65 nm CMOS process. The experimental results indicate that the implemented $\times 6$ frequency multiplier exhibits more than 23 dBc rejection to the fundamental and 2nd to 5th harmonics without the extra filter. The DC power consumption is 4.6 mW for the core circuit. [ABSTRACT FROM AUTHOR]